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tlb.h (91782) tlb.h (91783)
1/*-
2 * Copyright (c) 2001 Jake Burkholder.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 9 unchanged lines hidden (view full) ---

18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
1/*-
2 * Copyright (c) 2001 Jake Burkholder.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 9 unchanged lines hidden (view full) ---

18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/sparc64/include/tlb.h 91782 2002-03-07 05:25:15Z jake $
26 * $FreeBSD: head/sys/sparc64/include/tlb.h 91783 2002-03-07 06:01:40Z jake $
27 */
28
29#ifndef _MACHINE_TLB_H_
30#define _MACHINE_TLB_H_
31
27 */
28
29#ifndef _MACHINE_TLB_H_
30#define _MACHINE_TLB_H_
31
32#define TLB_SLOT_COUNT 64
32#define TLB_SLOT_COUNT 64 /* XXX */
33
34#define TLB_SLOT_TSB_KERNEL_MIN 62 /* XXX */
33
34#define TLB_SLOT_TSB_KERNEL_MIN 62 /* XXX */
35#define TLB_SLOT_KERNEL 63
35#define TLB_SLOT_KERNEL 63 /* XXX */
36
37#define TLB_DAR_SLOT_SHIFT (3)
38#define TLB_DAR_SLOT(slot) ((slot) << TLB_DAR_SLOT_SHIFT)
39
40#define TAR_VPN_SHIFT (13)
41#define TAR_CTX_MASK ((1 << TAR_VPN_SHIFT) - 1)
42
43#define TLB_TAR_VA(va) ((va) & ~TAR_CTX_MASK)

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84#define MMU_SFSR_CT_SIZE (2)
85
86#define MMU_SFSR_W (1L << MMU_SFSR_W_SHIFT)
87
88extern int kernel_tlb_slots;
89extern struct tte *kernel_ttes;
90
91/*
36
37#define TLB_DAR_SLOT_SHIFT (3)
38#define TLB_DAR_SLOT(slot) ((slot) << TLB_DAR_SLOT_SHIFT)
39
40#define TAR_VPN_SHIFT (13)
41#define TAR_CTX_MASK ((1 << TAR_VPN_SHIFT) - 1)
42
43#define TLB_TAR_VA(va) ((va) & ~TAR_CTX_MASK)

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84#define MMU_SFSR_CT_SIZE (2)
85
86#define MMU_SFSR_W (1L << MMU_SFSR_W_SHIFT)
87
88extern int kernel_tlb_slots;
89extern struct tte *kernel_ttes;
90
91/*
92 * Some tlb operations must be atomical, so no interrupt or trap can be allowed
92 * Some tlb operations must be atomic, so no interrupt or trap can be allowed
93 * while they are in progress. Traps should not happen, but interrupts need to
94 * be explicitely disabled. critical_enter() cannot be used here, since it only
95 * disables soft interrupts.
93 * while they are in progress. Traps should not happen, but interrupts need to
94 * be explicitely disabled. critical_enter() cannot be used here, since it only
95 * disables soft interrupts.
96 * XXX: is something like this needed elsewhere, too?
97 */
98
99static __inline void
96 */
97
98static __inline void
100tlb_dtlb_context_primary_demap(void)
99tlb_context_demap(struct pmap *pm)
101{
100{
102 stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_DMMU_DEMAP, 0);
103 membar(Sync);
104}
101 void *cookie;
102 u_long s;
105
103
106static __inline void
107tlb_dtlb_page_demap(struct pmap *pm, vm_offset_t va)
108{
109 u_int ctx;
110
111 ctx = pm->pm_context[PCPU_GET(cpuid)];
112 if (ctx == TLB_CTX_KERNEL) {
113 stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE,
114 ASI_DMMU_DEMAP, 0);
104 cookie = ipi_tlb_context_demap(pm);
105 if (pm->pm_active & PCPU_GET(cpumask)) {
106 KASSERT(pm->pm_context[PCPU_GET(cpuid)] != -1,
107 ("tlb_context_demap: inactive pmap?"));
108 s = intr_disable();
109 stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_DMMU_DEMAP, 0);
110 stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_IMMU_DEMAP, 0);
115 membar(Sync);
111 membar(Sync);
116 } else if (ctx != -1) {
117 stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE,
118 ASI_DMMU_DEMAP, 0);
119 membar(Sync);
112 intr_restore(s);
120 }
113 }
114 ipi_wait(cookie);
121}
122
123static __inline void
115}
116
117static __inline void
124tlb_dtlb_store(vm_offset_t va, u_long ctx, struct tte tte)
118tlb_page_demap(u_int tlb, struct pmap *pm, vm_offset_t va)
125{
119{
126 u_long pst;
120 u_long flags;
121 void *cookie;
122 u_long s;
127
123
128 pst = intr_disable();
129 stxa(AA_DMMU_TAR, ASI_DMMU,
130 TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
131 stxa(0, ASI_DTLB_DATA_IN_REG, tte.tte_data);
132 membar(Sync);
133 intr_restore(pst);
134}
135
136static __inline void
137tlb_dtlb_store_slot(vm_offset_t va, u_long ctx, struct tte tte, int slot)
138{
139 u_long pst;
140
141 pst = intr_disable();
142 stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
143 stxa(TLB_DAR_SLOT(slot), ASI_DTLB_DATA_ACCESS_REG, tte.tte_data);
144 membar(Sync);
145 intr_restore(pst);
146}
147
148static __inline void
149tlb_itlb_context_primary_demap(void)
150{
151 stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_IMMU_DEMAP, 0);
152 membar(Sync);
153}
154
155static __inline void
156tlb_itlb_page_demap(struct pmap *pm, vm_offset_t va)
157{
158 u_int ctx;
159
160 ctx = pm->pm_context[PCPU_GET(cpuid)];
161 if (ctx == TLB_CTX_KERNEL) {
162 stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE,
163 ASI_IMMU_DEMAP, 0);
164 flush(KERNBASE);
165 } else if (ctx != -1) {
166 stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE,
167 ASI_IMMU_DEMAP, 0);
168 membar(Sync);
124 cookie = ipi_tlb_page_demap(tlb, pm, va);
125 if (pm->pm_active & PCPU_GET(cpumask)) {
126 KASSERT(pm->pm_context[PCPU_GET(cpuid)] != -1,
127 ("tlb_page_demap: inactive pmap?"));
128 if (pm == kernel_pmap)
129 flags = TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE;
130 else
131 flags = TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE;
132
133 s = intr_disable();
134 if (tlb & TLB_DTLB) {
135 stxa(TLB_DEMAP_VA(va) | flags, ASI_DMMU_DEMAP, 0);
136 membar(Sync);
137 }
138 if (tlb & TLB_ITLB) {
139 stxa(TLB_DEMAP_VA(va) | flags, ASI_IMMU_DEMAP, 0);
140 membar(Sync);
141 }
142 intr_restore(s);
169 }
143 }
144 ipi_wait(cookie);
170}
171
172static __inline void
145}
146
147static __inline void
173tlb_itlb_store(vm_offset_t va, u_long ctx, struct tte tte)
148tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end)
174{
149{
175 u_long pst;
150 vm_offset_t va;
151 void *cookie;
152 u_long flags;
153 u_long s;
176
154
177 pst = intr_disable();
178 stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
179 stxa(0, ASI_ITLB_DATA_IN_REG, tte.tte_data);
180 if (ctx == TLB_CTX_KERNEL)
181 flush(va);
182 else {
183 /*
184 * flush probably not needed and impossible here, no access to
185 * user page.
186 */
187 membar(Sync);
155 cookie = ipi_tlb_range_demap(pm, start, end);
156 if (pm->pm_active & PCPU_GET(cpumask)) {
157 KASSERT(pm->pm_context[PCPU_GET(cpuid)] != -1,
158 ("tlb_range_demap: inactive pmap?"));
159 if (pm == kernel_pmap)
160 flags = TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE;
161 else
162 flags = TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE;
163
164 s = intr_disable();
165 for (va = start; va < end; va += PAGE_SIZE) {
166 stxa(TLB_DEMAP_VA(va) | flags, ASI_DMMU_DEMAP, 0);
167 stxa(TLB_DEMAP_VA(va) | flags, ASI_IMMU_DEMAP, 0);
168 membar(Sync);
169 }
170 intr_restore(s);
188 }
171 }
189 intr_restore(pst);
172 ipi_wait(cookie);
190}
191
173}
174
192static __inline void
193tlb_context_demap(struct pmap *pm)
194{
195 u_int ctx;
175#define tlb_tte_demap(tte, pm) \
176 tlb_page_demap(TD_GET_TLB((tte).tte_data), pm, \
177 TV_GET_VA((tte).tte_vpn));
196
178
197 ctx = pm->pm_context[PCPU_GET(cpuid)];
198 if (ctx != -1) {
199 tlb_dtlb_context_primary_demap();
200 tlb_itlb_context_primary_demap();
201 }
202}
203
204static __inline void
205tlb_itlb_store_slot(vm_offset_t va, u_long ctx, struct tte tte, int slot)
206{
207 u_long pst;
208
209 pst = intr_disable();
210 stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
211 stxa(TLB_DAR_SLOT(slot), ASI_ITLB_DATA_ACCESS_REG, tte.tte_data);
212 flush(va);
213 intr_restore(pst);
214}
215
216static __inline void
217tlb_page_demap(u_int tlb, struct pmap *pm, vm_offset_t va)
218{
219 if (tlb & TLB_DTLB)
220 tlb_dtlb_page_demap(pm, va);
221 if (tlb & TLB_ITLB)
222 tlb_itlb_page_demap(pm, va);
223}
224
225static __inline void
226tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end)
227{
228 for (; start < end; start += PAGE_SIZE)
229 tlb_page_demap(TLB_DTLB | TLB_ITLB, pm, start);
230}
231
232static __inline void
233tlb_tte_demap(struct tte tte, struct pmap *pm)
234{
235 tlb_page_demap(TD_GET_TLB(tte.tte_data), pm, TV_GET_VA(tte.tte_vpn));
236}
237
238static __inline void
239tlb_store(u_int tlb, vm_offset_t va, u_long ctx, struct tte tte)
240{
241 KASSERT(ctx != -1, ("tlb_store: invalid context"));
242 if (tlb & TLB_DTLB)
243 tlb_dtlb_store(va, ctx, tte);
244 if (tlb & TLB_ITLB)
245 tlb_itlb_store(va, ctx, tte);
246}
247
248static __inline void
249tlb_store_slot(u_int tlb, vm_offset_t va, u_long ctx, struct tte tte, int slot)
250{
251 KASSERT(ctx != -1, ("tlb_store_slot: invalid context"));
252 if (tlb & TLB_DTLB)
253 tlb_dtlb_store_slot(va, ctx, tte, slot);
254 if (tlb & TLB_ITLB)
255 tlb_itlb_store_slot(va, ctx, tte, slot);
256}
257
258#endif /* !_MACHINE_TLB_H_ */
179#endif /* !_MACHINE_TLB_H_ */