| smp.h (170846) | smp.h (178048) |
|---|---|
| 1/*- 2 * Copyright (c) 2001 Jake Burkholder. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 2001 Jake Burkholder. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/sparc64/include/smp.h 170846 2007-06-16 23:26:00Z marius $ | 26 * $FreeBSD: head/sys/sparc64/include/smp.h 178048 2008-04-09 21:14:01Z marius $ |
| 27 */ 28 29#ifndef _MACHINE_SMP_H_ 30#define _MACHINE_SMP_H_ 31 32#define CPU_CLKSYNC 1 33#define CPU_INIT 2 34#define CPU_BOOTSTRAP 3 --- 11 unchanged lines hidden (view full) --- 46#define IDR_CHEETAH_MAX_BN_PAIRS 32 47#define IDR_JALAPENO_MAX_BN_PAIRS 4 48 49#define IDC_ITID_SHIFT 14 50#define IDC_BN_SHIFT 24 51 52#define IPI_AST PIL_AST 53#define IPI_RENDEZVOUS PIL_RENDEZVOUS | 27 */ 28 29#ifndef _MACHINE_SMP_H_ 30#define _MACHINE_SMP_H_ 31 32#define CPU_CLKSYNC 1 33#define CPU_INIT 2 34#define CPU_BOOTSTRAP 3 --- 11 unchanged lines hidden (view full) --- 46#define IDR_CHEETAH_MAX_BN_PAIRS 32 47#define IDR_JALAPENO_MAX_BN_PAIRS 4 48 49#define IDC_ITID_SHIFT 14 50#define IDC_BN_SHIFT 24 51 52#define IPI_AST PIL_AST 53#define IPI_RENDEZVOUS PIL_RENDEZVOUS |
| 54#define IPI_PREEMPT PIL_PREEMPT |
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| 54#define IPI_STOP PIL_STOP 55 56#define IPI_RETRIES 5000 57 58struct cpu_start_args { 59 u_int csa_count; 60 u_int csa_mid; 61 u_int csa_state; --- 210 unchanged lines hidden --- | 55#define IPI_STOP PIL_STOP 56 57#define IPI_RETRIES 5000 58 59struct cpu_start_args { 60 u_int csa_count; 61 u_int csa_mid; 62 u_int csa_state; --- 210 unchanged lines hidden --- |