| iommureg.h (171730) | iommureg.h (185008) |
|---|---|
| 1/*- 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * --- 19 unchanged lines hidden (view full) --- 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)sbusreg.h 8.1 (Berkeley) 6/11/93 34 * from: NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp 35 * | 1/*- 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * --- 19 unchanged lines hidden (view full) --- 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)sbusreg.h 8.1 (Berkeley) 6/11/93 34 * from: NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp 35 * |
| 36 * $FreeBSD: head/sys/sparc64/include/iommureg.h 171730 2007-08-05 11:56:44Z marius $ | 36 * $FreeBSD: head/sys/sparc64/include/iommureg.h 185008 2008-11-16 19:53:49Z marius $ |
| 37 */ 38 39#ifndef _MACHINE_IOMMUREG_H_ 40#define _MACHINE_IOMMUREG_H_ 41 42/* 43 * UltraSPARC IOMMU registers, common to both the PCI and SBus 44 * controllers. --- 4 unchanged lines hidden (view full) --- 49#define IMR_TSB 0x0008 /* IOMMU TSB base register */ 50#define IMR_FLUSH 0x0010 /* IOMMU flush register */ 51 52/* streaming buffer registers */ 53#define ISR_CTL 0x0000 /* streaming buffer control reg */ 54#define ISR_PGFLUSH 0x0008 /* streaming buffer page flush */ 55#define ISR_FLUSHSYNC 0x0010 /* streaming buffer flush sync */ 56 | 37 */ 38 39#ifndef _MACHINE_IOMMUREG_H_ 40#define _MACHINE_IOMMUREG_H_ 41 42/* 43 * UltraSPARC IOMMU registers, common to both the PCI and SBus 44 * controllers. --- 4 unchanged lines hidden (view full) --- 49#define IMR_TSB 0x0008 /* IOMMU TSB base register */ 50#define IMR_FLUSH 0x0010 /* IOMMU flush register */ 51 52/* streaming buffer registers */ 53#define ISR_CTL 0x0000 /* streaming buffer control reg */ 54#define ISR_PGFLUSH 0x0008 /* streaming buffer page flush */ 55#define ISR_FLUSHSYNC 0x0010 /* streaming buffer flush sync */ 56 |
| 57/* streaming buffer diagnostics registers. */ | 57/* streaming buffer diagnostics registers */ |
| 58#define ISD_DATA_DIAG 0x0000 /* streaming buffer data RAM diag 0..127 */ 59#define ISD_ERROR_DIAG 0x0400 /* streaming buffer error status diag 0..127 */ 60#define ISD_PG_TAG_DIAG 0x0800 /* streaming buffer page tag diag 0..15 */ 61#define ISD_LN_TAG_DIAG 0x0900 /* streaming buffer line tag diag 0..15 */ 62 63/* streaming buffer control register */ 64#define STRBUF_EN 0x0000000000000001UL 65#define STRBUF_D 0x0000000000000002UL | 58#define ISD_DATA_DIAG 0x0000 /* streaming buffer data RAM diag 0..127 */ 59#define ISD_ERROR_DIAG 0x0400 /* streaming buffer error status diag 0..127 */ 60#define ISD_PG_TAG_DIAG 0x0800 /* streaming buffer page tag diag 0..15 */ 61#define ISD_LN_TAG_DIAG 0x0900 /* streaming buffer line tag diag 0..15 */ 62 63/* streaming buffer control register */ 64#define STRBUF_EN 0x0000000000000001UL 65#define STRBUF_D 0x0000000000000002UL |
| 66#define STRBUF_RR_DIS 0x0000000000000004UL |
|
| 66 67#define IOMMU_MAXADDR(bits) ((1UL << (bits)) - 1) 68 69/* 70 * control register bits 71 */ 72/* Nummber of entries in IOTSB */ 73#define IOMMUCR_TSBSZ_SHIFT 16 --- 12 unchanged lines hidden (view full) --- 86/* 64K iommu page size */ 87#define IOMMUCR_64KPG 0x0000000000000004UL 88/* Diag enable */ 89#define IOMMUCR_DE 0x0000000000000002UL 90/* Enable IOMMU */ 91#define IOMMUCR_EN 0x0000000000000001UL 92 93/* | 67 68#define IOMMU_MAXADDR(bits) ((1UL << (bits)) - 1) 69 70/* 71 * control register bits 72 */ 73/* Nummber of entries in IOTSB */ 74#define IOMMUCR_TSBSZ_SHIFT 16 --- 12 unchanged lines hidden (view full) --- 87/* 64K iommu page size */ 88#define IOMMUCR_64KPG 0x0000000000000004UL 89/* Diag enable */ 90#define IOMMUCR_DE 0x0000000000000002UL 91/* Enable IOMMU */ 92#define IOMMUCR_EN 0x0000000000000001UL 93 94/* |
| 94 * Diagnostic register definitions. | 95 * Diagnostic register definitions |
| 95 */ 96#define IOMMU_DTAG_VPNBITS 19 97#define IOMMU_DTAG_VPNMASK ((1 << IOMMU_DTAG_VPNBITS) - 1) 98#define IOMMU_DTAG_VPNSHIFT 13 99#define IOMMU_DTAG_ERRBITS 3 100#define IOMMU_DTAG_ERRSHIFT 22 101#define IOMMU_DTAG_ERRMASK \ 102 (((1 << IOMMU_DTAG_ERRBITS) - 1) << IOMMU_DTAG_ERRSHIFT) --- 18 unchanged lines hidden (view full) --- 121#define IOTTE_LOCAL 0x0800000000000000UL 122/* Let's assume this is correct */ 123#define IOTTE_PAMASK 0x000007ffffffe000UL 124/* Accesses to cacheable space */ 125#define IOTTE_C 0x0000000000000010UL 126/* Writeable */ 127#define IOTTE_W 0x0000000000000002UL 128 | 96 */ 97#define IOMMU_DTAG_VPNBITS 19 98#define IOMMU_DTAG_VPNMASK ((1 << IOMMU_DTAG_VPNBITS) - 1) 99#define IOMMU_DTAG_VPNSHIFT 13 100#define IOMMU_DTAG_ERRBITS 3 101#define IOMMU_DTAG_ERRSHIFT 22 102#define IOMMU_DTAG_ERRMASK \ 103 (((1 << IOMMU_DTAG_ERRBITS) - 1) << IOMMU_DTAG_ERRSHIFT) --- 18 unchanged lines hidden (view full) --- 122#define IOTTE_LOCAL 0x0800000000000000UL 123/* Let's assume this is correct */ 124#define IOTTE_PAMASK 0x000007ffffffe000UL 125/* Accesses to cacheable space */ 126#define IOTTE_C 0x0000000000000010UL 127/* Writeable */ 128#define IOTTE_W 0x0000000000000002UL 129 |
| 129/* log2 of the IOMMU TTE size. */ | 130/* log2 of the IOMMU TTE size */ |
| 130#define IOTTE_SHIFT 3 131 | 131#define IOTTE_SHIFT 3 132 |
| 132/* Streaming buffer line size. */ | 133/* Streaming buffer line size */ |
| 133#define STRBUF_LINESZ 64 134 135/* 136 * Number of bytes written by a stream buffer flushsync operation to indicate 137 * completion. 138 */ 139#define STRBUF_FLUSHSYNC_NBYTES STRBUF_LINESZ 140 --- 39 unchanged lines hidden --- | 134#define STRBUF_LINESZ 64 135 136/* 137 * Number of bytes written by a stream buffer flushsync operation to indicate 138 * completion. 139 */ 140#define STRBUF_FLUSHSYNC_NBYTES STRBUF_LINESZ 141 --- 39 unchanged lines hidden --- |