1/*-
2 * Copyright (c) 2003 Jake Burkholder.
3 * Copyright (c) 2005 Marius Strobl <marius@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2003 Jake Burkholder.
3 * Copyright (c) 2005 Marius Strobl <marius@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
|
29__FBSDID("$FreeBSD: head/sys/sparc64/fhc/fhc.c 200874 2009-12-22 21:02:46Z marius $");
| 29__FBSDID("$FreeBSD: head/sys/sparc64/fhc/fhc.c 206018 2010-03-31 22:19:00Z marius $");
|
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/bus.h>
34#include <sys/kernel.h>
35#include <sys/malloc.h>
36#include <sys/module.h>
37#include <sys/pcpu.h>
38
39#include <dev/led/led.h>
40#include <dev/ofw/ofw_bus.h>
41#include <dev/ofw/ofw_bus_subr.h>
42#include <dev/ofw/openfirm.h>
43
44#include <machine/bus.h>
45#include <machine/bus_common.h>
46#include <machine/resource.h>
47
48#include <sys/rman.h>
49
50#include <sparc64/fhc/fhcreg.h>
51#include <sparc64/sbus/ofw_sbus.h>
52
53struct fhc_devinfo {
54 struct ofw_bus_devinfo fdi_obdinfo;
55 struct resource_list fdi_rl;
56};
57
58struct fhc_softc {
59 struct resource *sc_memres[FHC_NREG];
60 int sc_nrange;
61 struct sbus_ranges *sc_ranges;
62 int sc_ign;
63 struct cdev *sc_led_dev;
64};
65
66static device_probe_t fhc_probe;
67static device_attach_t fhc_attach;
68static bus_print_child_t fhc_print_child;
69static bus_probe_nomatch_t fhc_probe_nomatch;
70static bus_setup_intr_t fhc_setup_intr;
71static bus_alloc_resource_t fhc_alloc_resource;
72static bus_get_resource_list_t fhc_get_resource_list;
73static ofw_bus_get_devinfo_t fhc_get_devinfo;
74
75static void fhc_intr_enable(void *);
76static void fhc_intr_disable(void *);
77static void fhc_intr_assign(void *);
78static void fhc_intr_clear(void *);
79static void fhc_led_func(void *, int);
80static int fhc_print_res(struct fhc_devinfo *);
81
82static device_method_t fhc_methods[] = {
83 /* Device interface */
84 DEVMETHOD(device_probe, fhc_probe),
85 DEVMETHOD(device_attach, fhc_attach),
86 DEVMETHOD(device_shutdown, bus_generic_shutdown),
87 DEVMETHOD(device_suspend, bus_generic_suspend),
88 DEVMETHOD(device_resume, bus_generic_resume),
89
90 /* Bus interface */
91 DEVMETHOD(bus_print_child, fhc_print_child),
92 DEVMETHOD(bus_probe_nomatch, fhc_probe_nomatch),
93 DEVMETHOD(bus_alloc_resource, fhc_alloc_resource),
94 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
95 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
96 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
97 DEVMETHOD(bus_setup_intr, fhc_setup_intr),
98 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
99 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
100 DEVMETHOD(bus_get_resource_list, fhc_get_resource_list),
101 DEVMETHOD(bus_child_pnpinfo_str, ofw_bus_gen_child_pnpinfo_str),
102
103 /* ofw_bus interface */
104 DEVMETHOD(ofw_bus_get_devinfo, fhc_get_devinfo),
105 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
106 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
107 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
108 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
109 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
110
111 KOBJMETHOD_END
112};
113
114static driver_t fhc_driver = {
115 "fhc",
116 fhc_methods,
117 sizeof(struct fhc_softc),
118};
119
120static devclass_t fhc_devclass;
121
122EARLY_DRIVER_MODULE(fhc, central, fhc_driver, fhc_devclass, 0, 0,
123 BUS_PASS_BUS);
124MODULE_DEPEND(fhc, central, 1, 1, 1);
125EARLY_DRIVER_MODULE(fhc, nexus, fhc_driver, fhc_devclass, 0, 0,
126 BUS_PASS_BUS);
127MODULE_DEPEND(fhc, nexus, 1, 1, 1);
128MODULE_VERSION(fhc, 1);
129
130static const struct intr_controller fhc_ic = {
131 fhc_intr_enable,
132 fhc_intr_disable,
133 fhc_intr_assign,
134 fhc_intr_clear
135};
136
137struct fhc_icarg {
138 struct fhc_softc *fica_sc;
139 struct resource *fica_memres;
140};
141
142static int
143fhc_probe(device_t dev)
144{
145
146 if (strcmp(ofw_bus_get_name(dev), "fhc") == 0) {
147 device_set_desc(dev, "fhc");
148 return (0);
149 }
150 return (ENXIO);
151}
152
153static int
154fhc_attach(device_t dev)
155{
156 char ledname[sizeof("boardXX")];
157 struct fhc_devinfo *fdi;
158 struct fhc_icarg *fica;
159 struct fhc_softc *sc;
160 struct sbus_regs *reg;
161 phandle_t child;
162 phandle_t node;
163 device_t cdev;
164 uint32_t board;
165 uint32_t ctrl;
166 uint32_t *intr;
167 uint32_t iv;
168 char *name;
169 int central;
170 int error;
171 int i;
172 int j;
173
174 sc = device_get_softc(dev);
175 node = ofw_bus_get_node(dev);
176
177 central = 0;
178 if (strcmp(device_get_name(device_get_parent(dev)), "central") == 0)
179 central = 1;
180
181 for (i = 0; i < FHC_NREG; i++) {
182 j = i;
183 sc->sc_memres[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
184 &j, RF_ACTIVE);
185 if (sc->sc_memres[i] == NULL) {
186 device_printf(dev, "cannot allocate resource %d\n", i);
187 error = ENXIO;
188 goto fail_memres;
189 }
190 }
191
192 if (central != 0) {
193 board = bus_read_4(sc->sc_memres[FHC_INTERNAL], FHC_BSR);
194 board = ((board >> 16) & 0x1) | ((board >> 12) & 0xe);
195 } else {
196 if (OF_getprop(node, "board#", &board, sizeof(board)) == -1) {
197 device_printf(dev, "cannot get board number\n");
198 error = ENXIO;
199 goto fail_memres;
200 }
201 }
202
203 device_printf(dev, "board %d, ", board);
204 if (OF_getprop_alloc(node, "board-model", 1, (void **)&name) != -1) {
205 printf("model %s\n", name);
206 free(name, M_OFWPROP);
207 } else
208 printf("model unknown\n");
209
210 for (i = FHC_FANFAIL; i <= FHC_TOD; i++) {
| 30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/bus.h>
34#include <sys/kernel.h>
35#include <sys/malloc.h>
36#include <sys/module.h>
37#include <sys/pcpu.h>
38
39#include <dev/led/led.h>
40#include <dev/ofw/ofw_bus.h>
41#include <dev/ofw/ofw_bus_subr.h>
42#include <dev/ofw/openfirm.h>
43
44#include <machine/bus.h>
45#include <machine/bus_common.h>
46#include <machine/resource.h>
47
48#include <sys/rman.h>
49
50#include <sparc64/fhc/fhcreg.h>
51#include <sparc64/sbus/ofw_sbus.h>
52
53struct fhc_devinfo {
54 struct ofw_bus_devinfo fdi_obdinfo;
55 struct resource_list fdi_rl;
56};
57
58struct fhc_softc {
59 struct resource *sc_memres[FHC_NREG];
60 int sc_nrange;
61 struct sbus_ranges *sc_ranges;
62 int sc_ign;
63 struct cdev *sc_led_dev;
64};
65
66static device_probe_t fhc_probe;
67static device_attach_t fhc_attach;
68static bus_print_child_t fhc_print_child;
69static bus_probe_nomatch_t fhc_probe_nomatch;
70static bus_setup_intr_t fhc_setup_intr;
71static bus_alloc_resource_t fhc_alloc_resource;
72static bus_get_resource_list_t fhc_get_resource_list;
73static ofw_bus_get_devinfo_t fhc_get_devinfo;
74
75static void fhc_intr_enable(void *);
76static void fhc_intr_disable(void *);
77static void fhc_intr_assign(void *);
78static void fhc_intr_clear(void *);
79static void fhc_led_func(void *, int);
80static int fhc_print_res(struct fhc_devinfo *);
81
82static device_method_t fhc_methods[] = {
83 /* Device interface */
84 DEVMETHOD(device_probe, fhc_probe),
85 DEVMETHOD(device_attach, fhc_attach),
86 DEVMETHOD(device_shutdown, bus_generic_shutdown),
87 DEVMETHOD(device_suspend, bus_generic_suspend),
88 DEVMETHOD(device_resume, bus_generic_resume),
89
90 /* Bus interface */
91 DEVMETHOD(bus_print_child, fhc_print_child),
92 DEVMETHOD(bus_probe_nomatch, fhc_probe_nomatch),
93 DEVMETHOD(bus_alloc_resource, fhc_alloc_resource),
94 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
95 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
96 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
97 DEVMETHOD(bus_setup_intr, fhc_setup_intr),
98 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
99 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
100 DEVMETHOD(bus_get_resource_list, fhc_get_resource_list),
101 DEVMETHOD(bus_child_pnpinfo_str, ofw_bus_gen_child_pnpinfo_str),
102
103 /* ofw_bus interface */
104 DEVMETHOD(ofw_bus_get_devinfo, fhc_get_devinfo),
105 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
106 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
107 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
108 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
109 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
110
111 KOBJMETHOD_END
112};
113
114static driver_t fhc_driver = {
115 "fhc",
116 fhc_methods,
117 sizeof(struct fhc_softc),
118};
119
120static devclass_t fhc_devclass;
121
122EARLY_DRIVER_MODULE(fhc, central, fhc_driver, fhc_devclass, 0, 0,
123 BUS_PASS_BUS);
124MODULE_DEPEND(fhc, central, 1, 1, 1);
125EARLY_DRIVER_MODULE(fhc, nexus, fhc_driver, fhc_devclass, 0, 0,
126 BUS_PASS_BUS);
127MODULE_DEPEND(fhc, nexus, 1, 1, 1);
128MODULE_VERSION(fhc, 1);
129
130static const struct intr_controller fhc_ic = {
131 fhc_intr_enable,
132 fhc_intr_disable,
133 fhc_intr_assign,
134 fhc_intr_clear
135};
136
137struct fhc_icarg {
138 struct fhc_softc *fica_sc;
139 struct resource *fica_memres;
140};
141
142static int
143fhc_probe(device_t dev)
144{
145
146 if (strcmp(ofw_bus_get_name(dev), "fhc") == 0) {
147 device_set_desc(dev, "fhc");
148 return (0);
149 }
150 return (ENXIO);
151}
152
153static int
154fhc_attach(device_t dev)
155{
156 char ledname[sizeof("boardXX")];
157 struct fhc_devinfo *fdi;
158 struct fhc_icarg *fica;
159 struct fhc_softc *sc;
160 struct sbus_regs *reg;
161 phandle_t child;
162 phandle_t node;
163 device_t cdev;
164 uint32_t board;
165 uint32_t ctrl;
166 uint32_t *intr;
167 uint32_t iv;
168 char *name;
169 int central;
170 int error;
171 int i;
172 int j;
173
174 sc = device_get_softc(dev);
175 node = ofw_bus_get_node(dev);
176
177 central = 0;
178 if (strcmp(device_get_name(device_get_parent(dev)), "central") == 0)
179 central = 1;
180
181 for (i = 0; i < FHC_NREG; i++) {
182 j = i;
183 sc->sc_memres[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
184 &j, RF_ACTIVE);
185 if (sc->sc_memres[i] == NULL) {
186 device_printf(dev, "cannot allocate resource %d\n", i);
187 error = ENXIO;
188 goto fail_memres;
189 }
190 }
191
192 if (central != 0) {
193 board = bus_read_4(sc->sc_memres[FHC_INTERNAL], FHC_BSR);
194 board = ((board >> 16) & 0x1) | ((board >> 12) & 0xe);
195 } else {
196 if (OF_getprop(node, "board#", &board, sizeof(board)) == -1) {
197 device_printf(dev, "cannot get board number\n");
198 error = ENXIO;
199 goto fail_memres;
200 }
201 }
202
203 device_printf(dev, "board %d, ", board);
204 if (OF_getprop_alloc(node, "board-model", 1, (void **)&name) != -1) {
205 printf("model %s\n", name);
206 free(name, M_OFWPROP);
207 } else
208 printf("model unknown\n");
209
210 for (i = FHC_FANFAIL; i <= FHC_TOD; i++) {
|
211 bus_write_4(sc->sc_memres[i], FHC_ICLR, 0x0);
| 211 bus_write_4(sc->sc_memres[i], FHC_ICLR, INTCLR_IDLE);
|
212 (void)bus_read_4(sc->sc_memres[i], FHC_ICLR);
213 }
214
215 sc->sc_ign = board << 1;
216 bus_write_4(sc->sc_memres[FHC_IGN], 0x0, sc->sc_ign);
217 sc->sc_ign = bus_read_4(sc->sc_memres[FHC_IGN], 0x0);
218
219 ctrl = bus_read_4(sc->sc_memres[FHC_INTERNAL], FHC_CTRL);
220 if (central == 0)
221 ctrl |= FHC_CTRL_IXIST;
222 ctrl &= ~(FHC_CTRL_AOFF | FHC_CTRL_BOFF | FHC_CTRL_SLINE);
223 bus_write_4(sc->sc_memres[FHC_INTERNAL], FHC_CTRL, ctrl);
224 (void)bus_read_4(sc->sc_memres[FHC_INTERNAL], FHC_CTRL);
225
226 sc->sc_nrange = OF_getprop_alloc(node, "ranges",
227 sizeof(*sc->sc_ranges), (void **)&sc->sc_ranges);
228 if (sc->sc_nrange == -1) {
229 device_printf(dev, "cannot get ranges\n");
230 error = ENXIO;
231 goto fail_memres;
232 }
233
234 /*
235 * Apparently only the interrupt controller of boards hanging off
236 * of central(4) is indented to be used, otherwise we would have
237 * conflicts registering the interrupt controllers for all FHC
238 * boards as the board number and thus the IGN isn't unique.
239 */
240 if (central == 1) {
241 /*
242 * Hunt through all the interrupt mapping regs and register
243 * our interrupt controller for the corresponding interrupt
244 * vectors. We do this early in order to be able to catch
245 * stray interrupts.
246 */
247 for (i = FHC_FANFAIL; i <= FHC_TOD; i++) {
248 fica = malloc(sizeof(*fica), M_DEVBUF, M_NOWAIT);
249 if (fica == NULL)
250 panic("%s: could not allocate interrupt "
251 "controller argument", __func__);
252 fica->fica_sc = sc;
253 fica->fica_memres = sc->sc_memres[i];
254#ifdef FHC_DEBUG
255 device_printf(dev, "intr map %d: %#lx, clr: %#lx\n", i,
256 (u_long)bus_read_4(fica->fica_memres, FHC_IMAP),
257 (u_long)bus_read_4(fica->fica_memres, FHC_ICLR));
258#endif
259 /*
260 * XXX we only pick the INO rather than the INR
261 * from the IMR since the firmware may not provide
262 * the IGN and the IGN is constant for all devices
263 * on that FireHose controller.
264 */
265 j = intr_controller_register(INTMAP_VEC(sc->sc_ign,
266 INTINO(bus_read_4(fica->fica_memres, FHC_IMAP))),
267 &fhc_ic, fica);
268 if (j != 0)
269 device_printf(dev, "could not register "
270 "interrupt controller for map %d (%d)\n",
271 i, j);
272 }
273 } else {
274 snprintf(ledname, sizeof(ledname), "board%d", board);
275 sc->sc_led_dev = led_create(fhc_led_func, sc, ledname);
276 }
277
278 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
279 fdi = malloc(sizeof(*fdi), M_DEVBUF, M_WAITOK | M_ZERO);
280 if (ofw_bus_gen_setup_devinfo(&fdi->fdi_obdinfo, child) != 0) {
281 free(fdi, M_DEVBUF);
282 continue;
283 }
284 i = OF_getprop_alloc(child, "reg", sizeof(*reg),
285 (void **)®);
286 if (i == -1) {
287 device_printf(dev, "<%s>: incomplete\n",
288 fdi->fdi_obdinfo.obd_name);
289 ofw_bus_gen_destroy_devinfo(&fdi->fdi_obdinfo);
290 free(fdi, M_DEVBUF);
291 continue;
292 }
293 resource_list_init(&fdi->fdi_rl);
294 for (j = 0; j < i; j++)
295 resource_list_add(&fdi->fdi_rl, SYS_RES_MEMORY, j,
296 reg[j].sbr_offset, reg[j].sbr_offset +
297 reg[j].sbr_size, reg[j].sbr_size);
298 free(reg, M_OFWPROP);
299 if (central == 1) {
300 i = OF_getprop_alloc(child, "interrupts",
301 sizeof(*intr), (void **)&intr);
302 if (i != -1) {
303 for (j = 0; j < i; j++) {
304 iv = INTMAP_VEC(sc->sc_ign, intr[j]);
305 resource_list_add(&fdi->fdi_rl,
306 SYS_RES_IRQ, j, iv, iv, 1);
307 }
308 free(intr, M_OFWPROP);
309 }
310 }
311 cdev = device_add_child(dev, NULL, -1);
312 if (cdev == NULL) {
313 device_printf(dev, "<%s>: device_add_child failed\n",
314 fdi->fdi_obdinfo.obd_name);
315 resource_list_free(&fdi->fdi_rl);
316 ofw_bus_gen_destroy_devinfo(&fdi->fdi_obdinfo);
317 free(fdi, M_DEVBUF);
318 continue;
319 }
320 device_set_ivars(cdev, fdi);
321 }
322
323 return (bus_generic_attach(dev));
324
325 fail_memres:
326 for (i = 0; i < FHC_NREG; i++)
327 if (sc->sc_memres[i] != NULL)
328 bus_release_resource(dev, SYS_RES_MEMORY,
329 rman_get_rid(sc->sc_memres[i]), sc->sc_memres[i]);
330 return (error);
331}
332
333static int
334fhc_print_child(device_t dev, device_t child)
335{
336 int rv;
337
338 rv = bus_print_child_header(dev, child);
339 rv += fhc_print_res(device_get_ivars(child));
340 rv += bus_print_child_footer(dev, child);
341 return (rv);
342}
343
344static void
345fhc_probe_nomatch(device_t dev, device_t child)
346{
347 const char *type;
348
349 device_printf(dev, "<%s>", ofw_bus_get_name(child));
350 fhc_print_res(device_get_ivars(child));
351 type = ofw_bus_get_type(child);
352 printf(" type %s (no driver attached)\n",
353 type != NULL ? type : "unknown");
354}
355
356static void
357fhc_intr_enable(void *arg)
358{
359 struct intr_vector *iv = arg;
360 struct fhc_icarg *fica = iv->iv_icarg;
361
362 bus_write_4(fica->fica_memres, FHC_IMAP,
363 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
364 (void)bus_read_4(fica->fica_memres, FHC_IMAP);
365}
366
367static void
368fhc_intr_disable(void *arg)
369{
370 struct intr_vector *iv = arg;
371 struct fhc_icarg *fica = iv->iv_icarg;
372
373 bus_write_4(fica->fica_memres, FHC_IMAP, iv->iv_vec);
374 (void)bus_read_4(fica->fica_memres, FHC_IMAP);
375}
376
377static void
378fhc_intr_assign(void *arg)
379{
380 struct intr_vector *iv = arg;
381 struct fhc_icarg *fica = iv->iv_icarg;
382
383 bus_write_4(fica->fica_memres, FHC_IMAP, INTMAP_TID(
384 bus_read_4(fica->fica_memres, FHC_IMAP), iv->iv_mid));
385 (void)bus_read_4(fica->fica_memres, FHC_IMAP);
386}
387
388static void
389fhc_intr_clear(void *arg)
390{
391 struct intr_vector *iv = arg;
392 struct fhc_icarg *fica = iv->iv_icarg;
393
| 212 (void)bus_read_4(sc->sc_memres[i], FHC_ICLR);
213 }
214
215 sc->sc_ign = board << 1;
216 bus_write_4(sc->sc_memres[FHC_IGN], 0x0, sc->sc_ign);
217 sc->sc_ign = bus_read_4(sc->sc_memres[FHC_IGN], 0x0);
218
219 ctrl = bus_read_4(sc->sc_memres[FHC_INTERNAL], FHC_CTRL);
220 if (central == 0)
221 ctrl |= FHC_CTRL_IXIST;
222 ctrl &= ~(FHC_CTRL_AOFF | FHC_CTRL_BOFF | FHC_CTRL_SLINE);
223 bus_write_4(sc->sc_memres[FHC_INTERNAL], FHC_CTRL, ctrl);
224 (void)bus_read_4(sc->sc_memres[FHC_INTERNAL], FHC_CTRL);
225
226 sc->sc_nrange = OF_getprop_alloc(node, "ranges",
227 sizeof(*sc->sc_ranges), (void **)&sc->sc_ranges);
228 if (sc->sc_nrange == -1) {
229 device_printf(dev, "cannot get ranges\n");
230 error = ENXIO;
231 goto fail_memres;
232 }
233
234 /*
235 * Apparently only the interrupt controller of boards hanging off
236 * of central(4) is indented to be used, otherwise we would have
237 * conflicts registering the interrupt controllers for all FHC
238 * boards as the board number and thus the IGN isn't unique.
239 */
240 if (central == 1) {
241 /*
242 * Hunt through all the interrupt mapping regs and register
243 * our interrupt controller for the corresponding interrupt
244 * vectors. We do this early in order to be able to catch
245 * stray interrupts.
246 */
247 for (i = FHC_FANFAIL; i <= FHC_TOD; i++) {
248 fica = malloc(sizeof(*fica), M_DEVBUF, M_NOWAIT);
249 if (fica == NULL)
250 panic("%s: could not allocate interrupt "
251 "controller argument", __func__);
252 fica->fica_sc = sc;
253 fica->fica_memres = sc->sc_memres[i];
254#ifdef FHC_DEBUG
255 device_printf(dev, "intr map %d: %#lx, clr: %#lx\n", i,
256 (u_long)bus_read_4(fica->fica_memres, FHC_IMAP),
257 (u_long)bus_read_4(fica->fica_memres, FHC_ICLR));
258#endif
259 /*
260 * XXX we only pick the INO rather than the INR
261 * from the IMR since the firmware may not provide
262 * the IGN and the IGN is constant for all devices
263 * on that FireHose controller.
264 */
265 j = intr_controller_register(INTMAP_VEC(sc->sc_ign,
266 INTINO(bus_read_4(fica->fica_memres, FHC_IMAP))),
267 &fhc_ic, fica);
268 if (j != 0)
269 device_printf(dev, "could not register "
270 "interrupt controller for map %d (%d)\n",
271 i, j);
272 }
273 } else {
274 snprintf(ledname, sizeof(ledname), "board%d", board);
275 sc->sc_led_dev = led_create(fhc_led_func, sc, ledname);
276 }
277
278 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
279 fdi = malloc(sizeof(*fdi), M_DEVBUF, M_WAITOK | M_ZERO);
280 if (ofw_bus_gen_setup_devinfo(&fdi->fdi_obdinfo, child) != 0) {
281 free(fdi, M_DEVBUF);
282 continue;
283 }
284 i = OF_getprop_alloc(child, "reg", sizeof(*reg),
285 (void **)®);
286 if (i == -1) {
287 device_printf(dev, "<%s>: incomplete\n",
288 fdi->fdi_obdinfo.obd_name);
289 ofw_bus_gen_destroy_devinfo(&fdi->fdi_obdinfo);
290 free(fdi, M_DEVBUF);
291 continue;
292 }
293 resource_list_init(&fdi->fdi_rl);
294 for (j = 0; j < i; j++)
295 resource_list_add(&fdi->fdi_rl, SYS_RES_MEMORY, j,
296 reg[j].sbr_offset, reg[j].sbr_offset +
297 reg[j].sbr_size, reg[j].sbr_size);
298 free(reg, M_OFWPROP);
299 if (central == 1) {
300 i = OF_getprop_alloc(child, "interrupts",
301 sizeof(*intr), (void **)&intr);
302 if (i != -1) {
303 for (j = 0; j < i; j++) {
304 iv = INTMAP_VEC(sc->sc_ign, intr[j]);
305 resource_list_add(&fdi->fdi_rl,
306 SYS_RES_IRQ, j, iv, iv, 1);
307 }
308 free(intr, M_OFWPROP);
309 }
310 }
311 cdev = device_add_child(dev, NULL, -1);
312 if (cdev == NULL) {
313 device_printf(dev, "<%s>: device_add_child failed\n",
314 fdi->fdi_obdinfo.obd_name);
315 resource_list_free(&fdi->fdi_rl);
316 ofw_bus_gen_destroy_devinfo(&fdi->fdi_obdinfo);
317 free(fdi, M_DEVBUF);
318 continue;
319 }
320 device_set_ivars(cdev, fdi);
321 }
322
323 return (bus_generic_attach(dev));
324
325 fail_memres:
326 for (i = 0; i < FHC_NREG; i++)
327 if (sc->sc_memres[i] != NULL)
328 bus_release_resource(dev, SYS_RES_MEMORY,
329 rman_get_rid(sc->sc_memres[i]), sc->sc_memres[i]);
330 return (error);
331}
332
333static int
334fhc_print_child(device_t dev, device_t child)
335{
336 int rv;
337
338 rv = bus_print_child_header(dev, child);
339 rv += fhc_print_res(device_get_ivars(child));
340 rv += bus_print_child_footer(dev, child);
341 return (rv);
342}
343
344static void
345fhc_probe_nomatch(device_t dev, device_t child)
346{
347 const char *type;
348
349 device_printf(dev, "<%s>", ofw_bus_get_name(child));
350 fhc_print_res(device_get_ivars(child));
351 type = ofw_bus_get_type(child);
352 printf(" type %s (no driver attached)\n",
353 type != NULL ? type : "unknown");
354}
355
356static void
357fhc_intr_enable(void *arg)
358{
359 struct intr_vector *iv = arg;
360 struct fhc_icarg *fica = iv->iv_icarg;
361
362 bus_write_4(fica->fica_memres, FHC_IMAP,
363 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
364 (void)bus_read_4(fica->fica_memres, FHC_IMAP);
365}
366
367static void
368fhc_intr_disable(void *arg)
369{
370 struct intr_vector *iv = arg;
371 struct fhc_icarg *fica = iv->iv_icarg;
372
373 bus_write_4(fica->fica_memres, FHC_IMAP, iv->iv_vec);
374 (void)bus_read_4(fica->fica_memres, FHC_IMAP);
375}
376
377static void
378fhc_intr_assign(void *arg)
379{
380 struct intr_vector *iv = arg;
381 struct fhc_icarg *fica = iv->iv_icarg;
382
383 bus_write_4(fica->fica_memres, FHC_IMAP, INTMAP_TID(
384 bus_read_4(fica->fica_memres, FHC_IMAP), iv->iv_mid));
385 (void)bus_read_4(fica->fica_memres, FHC_IMAP);
386}
387
388static void
389fhc_intr_clear(void *arg)
390{
391 struct intr_vector *iv = arg;
392 struct fhc_icarg *fica = iv->iv_icarg;
393
|
394 bus_write_4(fica->fica_memres, FHC_ICLR, 0x0);
| 394 bus_write_4(fica->fica_memres, FHC_ICLR, INTCLR_IDLE);
|
395 (void)bus_read_4(fica->fica_memres, FHC_ICLR);
396}
397
398static int
399fhc_setup_intr(device_t bus, device_t child, struct resource *r, int flags,
400 driver_filter_t *filt, driver_intr_t *func, void *arg, void **cookiep)
401{
402 struct fhc_softc *sc;
403 u_long vec;
404
405 sc = device_get_softc(bus);
406 /*
407 * Make sure the vector is fully specified and we registered
408 * our interrupt controller for it.
409 */
410 vec = rman_get_start(r);
411 if (INTIGN(vec) != sc->sc_ign || intr_vectors[vec].iv_ic != &fhc_ic) {
412 device_printf(bus, "invalid interrupt vector 0x%lx\n", vec);
413 return (EINVAL);
414 }
415 return (bus_generic_setup_intr(bus, child, r, flags, filt, func,
416 arg, cookiep));
417}
418
419static struct resource *
420fhc_alloc_resource(device_t bus, device_t child, int type, int *rid,
421 u_long start, u_long end, u_long count, u_int flags)
422{
423 struct resource_list *rl;
424 struct resource_list_entry *rle;
425 struct fhc_softc *sc;
426 struct resource *res;
427 bus_addr_t coffset;
428 bus_addr_t cend;
429 bus_addr_t phys;
430 int isdefault;
431 int passthrough;
432 int i;
433
434 isdefault = (start == 0UL && end == ~0UL);
435 passthrough = (device_get_parent(child) != bus);
436 res = NULL;
437 rle = NULL;
438 rl = BUS_GET_RESOURCE_LIST(bus, child);
439 sc = device_get_softc(bus);
440 switch (type) {
441 case SYS_RES_IRQ:
442 return (resource_list_alloc(rl, bus, child, type, rid, start,
443 end, count, flags));
444 case SYS_RES_MEMORY:
445 if (!passthrough) {
446 rle = resource_list_find(rl, type, *rid);
447 if (rle == NULL)
448 return (NULL);
449 if (rle->res != NULL)
450 panic("%s: resource entry is busy", __func__);
451 if (isdefault) {
452 start = rle->start;
453 count = ulmax(count, rle->count);
454 end = ulmax(rle->end, start + count - 1);
455 }
456 }
457 for (i = 0; i < sc->sc_nrange; i++) {
458 coffset = sc->sc_ranges[i].coffset;
459 cend = coffset + sc->sc_ranges[i].size - 1;
460 if (start >= coffset && end <= cend) {
461 start -= coffset;
462 end -= coffset;
463 phys = sc->sc_ranges[i].poffset |
464 ((bus_addr_t)sc->sc_ranges[i].pspace << 32);
465 res = bus_generic_alloc_resource(bus, child,
466 type, rid, phys + start, phys + end,
467 count, flags);
468 if (!passthrough)
469 rle->res = res;
470 break;
471 }
472 }
473 break;
474 }
475 return (res);
476}
477
478static struct resource_list *
479fhc_get_resource_list(device_t bus, device_t child)
480{
481 struct fhc_devinfo *fdi;
482
483 fdi = device_get_ivars(child);
484 return (&fdi->fdi_rl);
485}
486
487static const struct ofw_bus_devinfo *
488fhc_get_devinfo(device_t bus, device_t child)
489{
490 struct fhc_devinfo *fdi;
491
492 fdi = device_get_ivars(child);
493 return (&fdi->fdi_obdinfo);
494}
495
496static void
497fhc_led_func(void *arg, int onoff)
498{
499 struct fhc_softc *sc;
500 uint32_t ctrl;
501
502 sc = (struct fhc_softc *)arg;
503
504 ctrl = bus_read_4(sc->sc_memres[FHC_INTERNAL], FHC_CTRL);
505 if (onoff)
506 ctrl |= FHC_CTRL_RLED;
507 else
508 ctrl &= ~FHC_CTRL_RLED;
509 ctrl &= ~(FHC_CTRL_AOFF | FHC_CTRL_BOFF | FHC_CTRL_SLINE);
510 bus_write_4(sc->sc_memres[FHC_INTERNAL], FHC_CTRL, ctrl);
511 (void)bus_read_4(sc->sc_memres[FHC_INTERNAL], FHC_CTRL);
512}
513
514static int
515fhc_print_res(struct fhc_devinfo *fdi)
516{
517 int rv;
518
519 rv = 0;
520 rv += resource_list_print_type(&fdi->fdi_rl, "mem", SYS_RES_MEMORY,
521 "%#lx");
522 rv += resource_list_print_type(&fdi->fdi_rl, "irq", SYS_RES_IRQ, "%ld");
523 return (rv);
524}
| 395 (void)bus_read_4(fica->fica_memres, FHC_ICLR);
396}
397
398static int
399fhc_setup_intr(device_t bus, device_t child, struct resource *r, int flags,
400 driver_filter_t *filt, driver_intr_t *func, void *arg, void **cookiep)
401{
402 struct fhc_softc *sc;
403 u_long vec;
404
405 sc = device_get_softc(bus);
406 /*
407 * Make sure the vector is fully specified and we registered
408 * our interrupt controller for it.
409 */
410 vec = rman_get_start(r);
411 if (INTIGN(vec) != sc->sc_ign || intr_vectors[vec].iv_ic != &fhc_ic) {
412 device_printf(bus, "invalid interrupt vector 0x%lx\n", vec);
413 return (EINVAL);
414 }
415 return (bus_generic_setup_intr(bus, child, r, flags, filt, func,
416 arg, cookiep));
417}
418
419static struct resource *
420fhc_alloc_resource(device_t bus, device_t child, int type, int *rid,
421 u_long start, u_long end, u_long count, u_int flags)
422{
423 struct resource_list *rl;
424 struct resource_list_entry *rle;
425 struct fhc_softc *sc;
426 struct resource *res;
427 bus_addr_t coffset;
428 bus_addr_t cend;
429 bus_addr_t phys;
430 int isdefault;
431 int passthrough;
432 int i;
433
434 isdefault = (start == 0UL && end == ~0UL);
435 passthrough = (device_get_parent(child) != bus);
436 res = NULL;
437 rle = NULL;
438 rl = BUS_GET_RESOURCE_LIST(bus, child);
439 sc = device_get_softc(bus);
440 switch (type) {
441 case SYS_RES_IRQ:
442 return (resource_list_alloc(rl, bus, child, type, rid, start,
443 end, count, flags));
444 case SYS_RES_MEMORY:
445 if (!passthrough) {
446 rle = resource_list_find(rl, type, *rid);
447 if (rle == NULL)
448 return (NULL);
449 if (rle->res != NULL)
450 panic("%s: resource entry is busy", __func__);
451 if (isdefault) {
452 start = rle->start;
453 count = ulmax(count, rle->count);
454 end = ulmax(rle->end, start + count - 1);
455 }
456 }
457 for (i = 0; i < sc->sc_nrange; i++) {
458 coffset = sc->sc_ranges[i].coffset;
459 cend = coffset + sc->sc_ranges[i].size - 1;
460 if (start >= coffset && end <= cend) {
461 start -= coffset;
462 end -= coffset;
463 phys = sc->sc_ranges[i].poffset |
464 ((bus_addr_t)sc->sc_ranges[i].pspace << 32);
465 res = bus_generic_alloc_resource(bus, child,
466 type, rid, phys + start, phys + end,
467 count, flags);
468 if (!passthrough)
469 rle->res = res;
470 break;
471 }
472 }
473 break;
474 }
475 return (res);
476}
477
478static struct resource_list *
479fhc_get_resource_list(device_t bus, device_t child)
480{
481 struct fhc_devinfo *fdi;
482
483 fdi = device_get_ivars(child);
484 return (&fdi->fdi_rl);
485}
486
487static const struct ofw_bus_devinfo *
488fhc_get_devinfo(device_t bus, device_t child)
489{
490 struct fhc_devinfo *fdi;
491
492 fdi = device_get_ivars(child);
493 return (&fdi->fdi_obdinfo);
494}
495
496static void
497fhc_led_func(void *arg, int onoff)
498{
499 struct fhc_softc *sc;
500 uint32_t ctrl;
501
502 sc = (struct fhc_softc *)arg;
503
504 ctrl = bus_read_4(sc->sc_memres[FHC_INTERNAL], FHC_CTRL);
505 if (onoff)
506 ctrl |= FHC_CTRL_RLED;
507 else
508 ctrl &= ~FHC_CTRL_RLED;
509 ctrl &= ~(FHC_CTRL_AOFF | FHC_CTRL_BOFF | FHC_CTRL_SLINE);
510 bus_write_4(sc->sc_memres[FHC_INTERNAL], FHC_CTRL, ctrl);
511 (void)bus_read_4(sc->sc_memres[FHC_INTERNAL], FHC_CTRL);
512}
513
514static int
515fhc_print_res(struct fhc_devinfo *fdi)
516{
517 int rv;
518
519 rv = 0;
520 rv += resource_list_print_type(&fdi->fdi_rl, "mem", SYS_RES_MEMORY,
521 "%#lx");
522 rv += resource_list_print_type(&fdi->fdi_rl, "irq", SYS_RES_IRQ, "%ld");
523 return (rv);
524}
|