1/*-
2 * Copyright (C) 2008 Semihalf, Rafal Jaworowski
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
| 1/*-
2 * Copyright (C) 2008 Semihalf, Rafal Jaworowski
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
|
28__FBSDID("$FreeBSD: head/sys/powerpc/mpc85xx/mpc85xx.c 189757 2009-03-13 06:28:20Z raj $");
| 28__FBSDID("$FreeBSD: head/sys/powerpc/mpc85xx/mpc85xx.c 209908 2010-07-11 21:08:29Z raj $");
|
29
30#include <sys/param.h>
31#include <sys/systm.h>
| 29
30#include <sys/param.h>
31#include <sys/systm.h>
|
| 32#include <sys/lock.h>
33#include <sys/mutex.h>
34#include <sys/rman.h>
|
32
33#include <vm/vm.h>
34#include <vm/vm_param.h>
35
36#include <machine/cpu.h>
37#include <machine/cpufunc.h>
38#include <machine/spr.h>
39
| 35
36#include <vm/vm.h>
37#include <vm/vm_param.h>
38
39#include <machine/cpu.h>
40#include <machine/cpufunc.h>
41#include <machine/spr.h>
42
|
40#include <powerpc/mpc85xx/ocpbus.h>
| |
41#include <powerpc/mpc85xx/mpc85xx.h>
42
43/*
44 * MPC85xx system specific routines
45 */
46
47uint32_t
48ccsr_read4(uintptr_t addr)
49{
50 volatile uint32_t *ptr = (void *)addr;
51
52 return (*ptr);
53}
54
55void
56ccsr_write4(uintptr_t addr, uint32_t val)
57{
58 volatile uint32_t *ptr = (void *)addr;
59
60 *ptr = val;
61 __asm __volatile("eieio; sync");
62}
63
64int
65law_getmax(void)
66{
67 uint32_t ver;
68
69 ver = SVR_VER(mfspr(SPR_SVR));
70 if (ver == SVR_MPC8572E || ver == SVR_MPC8572)
71 return (12);
72 else if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
73 return (10);
74 else
75 return (8);
76}
77
78#define _LAW_SR(trgt,size) (0x80000000 | (trgt << 20) | (ffsl(size) - 2))
79#define _LAW_BAR(addr) (addr >> 12)
80
81int
82law_enable(int trgt, u_long addr, u_long size)
83{
84 uint32_t bar, sr;
85 int i, law_max;
86
87 law_max = law_getmax();
88 bar = _LAW_BAR(addr);
89 sr = _LAW_SR(trgt, size);
90
91 /* Bail if already programmed. */
92 for (i = 0; i < law_max; i++)
93 if (sr == ccsr_read4(OCP85XX_LAWSR(i)) &&
94 bar == ccsr_read4(OCP85XX_LAWBAR(i)))
95 return (0);
96
97 /* Find an unused access window. */
98 for (i = 0; i < law_max; i++)
99 if ((ccsr_read4(OCP85XX_LAWSR(i)) & 0x80000000) == 0)
100 break;
101
102 if (i == law_max)
103 return (ENOSPC);
104
105 ccsr_write4(OCP85XX_LAWBAR(i), bar);
106 ccsr_write4(OCP85XX_LAWSR(i), sr);
107 return (0);
108}
109
110int
111law_disable(int trgt, u_long addr, u_long size)
112{
113 uint32_t bar, sr;
114 int i, law_max;
115
116 law_max = law_getmax();
117 bar = _LAW_BAR(addr);
118 sr = _LAW_SR(trgt, size);
119
120 /* Find and disable requested LAW. */
121 for (i = 0; i < law_max; i++)
122 if (sr == ccsr_read4(OCP85XX_LAWSR(i)) &&
123 bar == ccsr_read4(OCP85XX_LAWBAR(i))) {
124 ccsr_write4(OCP85XX_LAWBAR(i), 0);
125 ccsr_write4(OCP85XX_LAWSR(i), 0);
126 return (0);
127 }
128
129 return (ENOENT);
130}
131
| 43#include <powerpc/mpc85xx/mpc85xx.h>
44
45/*
46 * MPC85xx system specific routines
47 */
48
49uint32_t
50ccsr_read4(uintptr_t addr)
51{
52 volatile uint32_t *ptr = (void *)addr;
53
54 return (*ptr);
55}
56
57void
58ccsr_write4(uintptr_t addr, uint32_t val)
59{
60 volatile uint32_t *ptr = (void *)addr;
61
62 *ptr = val;
63 __asm __volatile("eieio; sync");
64}
65
66int
67law_getmax(void)
68{
69 uint32_t ver;
70
71 ver = SVR_VER(mfspr(SPR_SVR));
72 if (ver == SVR_MPC8572E || ver == SVR_MPC8572)
73 return (12);
74 else if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
75 return (10);
76 else
77 return (8);
78}
79
80#define _LAW_SR(trgt,size) (0x80000000 | (trgt << 20) | (ffsl(size) - 2))
81#define _LAW_BAR(addr) (addr >> 12)
82
83int
84law_enable(int trgt, u_long addr, u_long size)
85{
86 uint32_t bar, sr;
87 int i, law_max;
88
89 law_max = law_getmax();
90 bar = _LAW_BAR(addr);
91 sr = _LAW_SR(trgt, size);
92
93 /* Bail if already programmed. */
94 for (i = 0; i < law_max; i++)
95 if (sr == ccsr_read4(OCP85XX_LAWSR(i)) &&
96 bar == ccsr_read4(OCP85XX_LAWBAR(i)))
97 return (0);
98
99 /* Find an unused access window. */
100 for (i = 0; i < law_max; i++)
101 if ((ccsr_read4(OCP85XX_LAWSR(i)) & 0x80000000) == 0)
102 break;
103
104 if (i == law_max)
105 return (ENOSPC);
106
107 ccsr_write4(OCP85XX_LAWBAR(i), bar);
108 ccsr_write4(OCP85XX_LAWSR(i), sr);
109 return (0);
110}
111
112int
113law_disable(int trgt, u_long addr, u_long size)
114{
115 uint32_t bar, sr;
116 int i, law_max;
117
118 law_max = law_getmax();
119 bar = _LAW_BAR(addr);
120 sr = _LAW_SR(trgt, size);
121
122 /* Find and disable requested LAW. */
123 for (i = 0; i < law_max; i++)
124 if (sr == ccsr_read4(OCP85XX_LAWSR(i)) &&
125 bar == ccsr_read4(OCP85XX_LAWBAR(i))) {
126 ccsr_write4(OCP85XX_LAWBAR(i), 0);
127 ccsr_write4(OCP85XX_LAWSR(i), 0);
128 return (0);
129 }
130
131 return (ENOENT);
132}
133
|
| 134int
135law_pci_target(struct resource *res, int *trgt_mem, int *trgt_io)
136{
137 u_long start;
138 uint32_t ver;
139 int trgt, rv;
140
141 ver = SVR_VER(mfspr(SPR_SVR));
142
143 start = rman_get_start(res) & 0xf000;
144
145 rv = 0;
146 trgt = -1;
147 switch (start) {
148 case 0x8000:
149 trgt = 0;
150 break;
151 case 0x9000:
152 trgt = 1;
153 break;
154 case 0xa000:
155 if (ver == SVR_MPC8572E || ver == SVR_MPC8572)
156 trgt = 2;
157 else
158 rv = EINVAL;
159 break;
160 default:
161 rv = ENXIO;
162 }
163 *trgt_mem = *trgt_io = trgt;
164 return (rv);
165}
166
|
132void
133cpu_reset(void)
134{
135 uint32_t ver = SVR_VER(mfspr(SPR_SVR));
136
137 if (ver == SVR_MPC8572E || ver == SVR_MPC8572 ||
138 ver == SVR_MPC8548E || ver == SVR_MPC8548)
139 /* Systems with dedicated reset register */
140 ccsr_write4(OCP85XX_RSTCR, 2);
141 else {
142 /* Clear DBCR0, disables debug interrupts and events. */
143 mtspr(SPR_DBCR0, 0);
144 __asm __volatile("isync");
145
146 /* Enable Debug Interrupts in MSR. */
147 mtmsr(mfmsr() | PSL_DE);
148
149 /* Enable debug interrupts and issue reset. */
150 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM |
151 DBCR0_RST_SYSTEM);
152 }
153
154 printf("Reset failed...\n");
155 while (1);
156}
| 167void
168cpu_reset(void)
169{
170 uint32_t ver = SVR_VER(mfspr(SPR_SVR));
171
172 if (ver == SVR_MPC8572E || ver == SVR_MPC8572 ||
173 ver == SVR_MPC8548E || ver == SVR_MPC8548)
174 /* Systems with dedicated reset register */
175 ccsr_write4(OCP85XX_RSTCR, 2);
176 else {
177 /* Clear DBCR0, disables debug interrupts and events. */
178 mtspr(SPR_DBCR0, 0);
179 __asm __volatile("isync");
180
181 /* Enable Debug Interrupts in MSR. */
182 mtmsr(mfmsr() | PSL_DE);
183
184 /* Enable debug interrupts and issue reset. */
185 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM |
186 DBCR0_RST_SYSTEM);
187 }
188
189 printf("Reset failed...\n");
190 while (1);
191}
|