| spr.h (189757) | spr.h (190681) |
|---|---|
| 1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $ | 1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $ |
| 34 * $FreeBSD: head/sys/powerpc/include/spr.h 189757 2009-03-13 06:28:20Z raj $ | 34 * $FreeBSD: head/sys/powerpc/include/spr.h 190681 2009-04-04 00:22:44Z nwhitehorn $ |
| 35 */ 36#ifndef _POWERPC_SPR_H_ 37#define _POWERPC_SPR_H_ 38 39#ifndef _LOCORE 40#define mtspr(reg, val) \ 41 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) 42#define mfspr(reg) \ 43 ( { register_t val; \ 44 __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \ 45 val; } ) | 35 */ 36#ifndef _POWERPC_SPR_H_ 37#define _POWERPC_SPR_H_ 38 39#ifndef _LOCORE 40#define mtspr(reg, val) \ 41 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) 42#define mfspr(reg) \ 43 ( { register_t val; \ 44 __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \ 45 val; } ) |
| 46 47/* The following routines allow manipulation of the full 64-bit width 48 * of SPRs on 64 bit CPUs in bridge mode */ 49 50#define mtspr64(reg,valhi,vallo,scratch) \ 51 __asm __volatile(" \ 52 mfmsr %0; \ 53 insrdi %0,1,1,0; \ 54 mtmsrd %0; \ 55 isync; \ 56 \ 57 sld %1,%1,%4; \ 58 or %1,%1,%2; \ 59 mtspr %3,%1; \ 60 srd %1,%1,%4; \ 61 \ 62 clrldi %0,%0,1; \ 63 mtmsrd %0; \ 64 isync;" \ 65 : "=r"(scratch), "=r"(valhi) : "r"(vallo), "K"(reg), "r"(32)) 66 67#define mfspr64upper(reg,scratch) \ 68 ( { register_t val; \ 69 __asm __volatile(" \ 70 mfmsr %0; \ 71 insrdi %0,1,1,0; \ 72 mtmsrd %0; \ 73 isync; \ 74 \ 75 mfspr %1,%2; \ 76 srd %1,%1,%3; \ 77 \ 78 clrldi %0,%0,1; \ 79 mtmsrd %0; \ 80 isync;" \ 81 : "=r"(scratch), "=r"(val) : "K"(reg), "r"(32)); \ 82 val; } ) 83 |
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| 46#endif /* _LOCORE */ 47 48/* 49 * Special Purpose Register declarations. 50 * 51 * The first column in the comments indicates which PowerPC 52 * architectures the SPR is valid on - 4 for 4xx series, 53 * 6 for 6xx/7xx series and 8 for 8xx and 8xxx series. --- 53 unchanged lines hidden (view full) --- 107#define IBM403 0x0020 108#define IBM401A1 0x0021 109#define IBM401B2 0x0022 110#define IBM401C2 0x0023 111#define IBM401D2 0x0024 112#define IBM401E2 0x0025 113#define IBM401F2 0x0026 114#define IBM401G2 0x0027 | 84#endif /* _LOCORE */ 85 86/* 87 * Special Purpose Register declarations. 88 * 89 * The first column in the comments indicates which PowerPC 90 * architectures the SPR is valid on - 4 for 4xx series, 91 * 6 for 6xx/7xx series and 8 for 8xx and 8xxx series. --- 53 unchanged lines hidden (view full) --- 145#define IBM403 0x0020 146#define IBM401A1 0x0021 147#define IBM401B2 0x0022 148#define IBM401C2 0x0023 149#define IBM401D2 0x0024 150#define IBM401E2 0x0025 151#define IBM401F2 0x0026 152#define IBM401G2 0x0027 |
| 153#define IBM970 0x0039 154#define IBM970FX 0x003c |
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| 115#define IBMPOWER3 0x0041 | 155#define IBMPOWER3 0x0041 |
| 156#define IBM970MP 0x0044 157#define IBM970GX 0x0045 |
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| 116#define MPC860 0x0050 117#define MPC8240 0x0081 118#define IBM405GP 0x4011 119#define IBM405L 0x4161 120#define IBM750FX 0x7000 121#define MPC745X_P(v) ((v & 0xFFF8) == 0x8000) 122#define MPC7450 0x8000 123#define MPC7455 0x8001 --- 506 unchanged lines hidden --- | 158#define MPC860 0x0050 159#define MPC8240 0x0081 160#define IBM405GP 0x4011 161#define IBM405L 0x4161 162#define IBM750FX 0x7000 163#define MPC745X_P(v) ((v & 0xFFF8) == 0x8000) 164#define MPC7450 0x8000 165#define MPC7455 0x8001 --- 506 unchanged lines hidden --- |