| psl.h (176770) | psl.h (209950) |
|---|---|
| 1/*- 2 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 3 * Copyright (C) 1995, 1996 TooLs GmbH. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 15 unchanged lines hidden (view full) --- 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * $NetBSD: psl.h,v 1.5 2000/11/19 19:52:37 matt Exp $ | 1/*- 2 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 3 * Copyright (C) 1995, 1996 TooLs GmbH. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 15 unchanged lines hidden (view full) --- 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * $NetBSD: psl.h,v 1.5 2000/11/19 19:52:37 matt Exp $ |
| 32 * $FreeBSD: head/sys/powerpc/include/psl.h 176770 2008-03-03 13:20:52Z raj $ | 32 * $FreeBSD: head/sys/powerpc/include/psl.h 209950 2010-07-12 16:08:07Z nwhitehorn $ |
| 33 */ 34 35#ifndef _MACHINE_PSL_H_ 36#define _MACHINE_PSL_H_ 37 38#if defined(E500) 39/* 40 * Machine State Register (MSR) - e500 core --- 14 unchanged lines hidden (view full) --- 55#define PSL_FE0 0x00000800 /* Floating point exception mode 0 */ 56#define PSL_UBLE 0x00000400 /* BTB lock enable */ 57#define PSL_DE 0x00000200 /* Debug interrupt enable */ 58#define PSL_FE1 0x00000100 /* Floating point exception mode 1 */ 59#define PSL_IS 0x00000020 /* Instruction address space */ 60#define PSL_DS 0x00000010 /* Data address space */ 61#define PSL_PMM 0x00000004 /* Performance monitor mark */ 62 | 33 */ 34 35#ifndef _MACHINE_PSL_H_ 36#define _MACHINE_PSL_H_ 37 38#if defined(E500) 39/* 40 * Machine State Register (MSR) - e500 core --- 14 unchanged lines hidden (view full) --- 55#define PSL_FE0 0x00000800 /* Floating point exception mode 0 */ 56#define PSL_UBLE 0x00000400 /* BTB lock enable */ 57#define PSL_DE 0x00000200 /* Debug interrupt enable */ 58#define PSL_FE1 0x00000100 /* Floating point exception mode 1 */ 59#define PSL_IS 0x00000020 /* Instruction address space */ 60#define PSL_DS 0x00000010 /* Data address space */ 61#define PSL_PMM 0x00000004 /* Performance monitor mark */ 62 |
| 63#define PSL_FE_DFLT 0x00000004 /* default: no FP */ 64 |
|
| 63/* Initial kernel MSR, use IS=1 ad DS=1. */ 64#define PSL_KERNSET_INIT (PSL_IS | PSL_DS) 65#define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE) 66#define PSL_USERSET (PSL_KERNSET | PSL_PR) 67 68#else /* if defined(E500) */ 69/* 70 * Machine State Register (MSR) --- 48 unchanged lines hidden --- | 65/* Initial kernel MSR, use IS=1 ad DS=1. */ 66#define PSL_KERNSET_INIT (PSL_IS | PSL_DS) 67#define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE) 68#define PSL_USERSET (PSL_KERNSET | PSL_PR) 69 70#else /* if defined(E500) */ 71/* 72 * Machine State Register (MSR) --- 48 unchanged lines hidden --- |