1/*-
2 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
19 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
20 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
21 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
22 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
23 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25/*-
26 * Copyright (C) 2001 Benno Rice
27 * All rights reserved.
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
31 * are met:
32 * 1. Redistributions of source code must retain the above copyright
33 * notice, this list of conditions and the following disclaimer.
34 * 2. Redistributions in binary form must reproduce the above copyright
35 * notice, this list of conditions and the following disclaimer in the
36 * documentation and/or other materials provided with the distribution.
37 *
38 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
39 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
40 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
41 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
43 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
44 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
45 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
46 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
47 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $
49 */
50/*-
51 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
52 * Copyright (C) 1995, 1996 TooLs GmbH.
53 * All rights reserved.
54 *
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
57 * are met:
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
63 * 3. All advertising materials mentioning features or use of this software
64 * must display the following acknowledgement:
65 * This product includes software developed by TooLs GmbH.
66 * 4. The name of TooLs GmbH may not be used to endorse or promote products
67 * derived from this software without specific prior written permission.
68 *
69 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
72 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
73 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
74 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
75 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
76 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
77 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
78 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
79 */
80
81#include <sys/cdefs.h>
| 1/*-
2 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
19 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
20 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
21 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
22 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
23 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25/*-
26 * Copyright (C) 2001 Benno Rice
27 * All rights reserved.
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
31 * are met:
32 * 1. Redistributions of source code must retain the above copyright
33 * notice, this list of conditions and the following disclaimer.
34 * 2. Redistributions in binary form must reproduce the above copyright
35 * notice, this list of conditions and the following disclaimer in the
36 * documentation and/or other materials provided with the distribution.
37 *
38 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
39 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
40 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
41 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
43 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
44 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
45 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
46 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
47 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $
49 */
50/*-
51 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
52 * Copyright (C) 1995, 1996 TooLs GmbH.
53 * All rights reserved.
54 *
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
57 * are met:
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
63 * 3. All advertising materials mentioning features or use of this software
64 * must display the following acknowledgement:
65 * This product includes software developed by TooLs GmbH.
66 * 4. The name of TooLs GmbH may not be used to endorse or promote products
67 * derived from this software without specific prior written permission.
68 *
69 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
72 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
73 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
74 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
75 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
76 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
77 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
78 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
79 */
80
81#include <sys/cdefs.h>
|
83
84#include "opt_compat.h"
85#include "opt_ddb.h"
86#include "opt_kstack_pages.h"
87#include "opt_msgbuf.h"
88
89#include <sys/cdefs.h>
90#include <sys/types.h>
91#include <sys/param.h>
92#include <sys/proc.h>
93#include <sys/systm.h>
94#include <sys/time.h>
95#include <sys/bio.h>
96#include <sys/buf.h>
97#include <sys/bus.h>
98#include <sys/cons.h>
99#include <sys/cpu.h>
100#include <sys/kdb.h>
101#include <sys/kernel.h>
102#include <sys/lock.h>
103#include <sys/mutex.h>
104#include <sys/sysctl.h>
105#include <sys/exec.h>
106#include <sys/ktr.h>
107#include <sys/syscallsubr.h>
108#include <sys/sysproto.h>
109#include <sys/signalvar.h>
110#include <sys/sysent.h>
111#include <sys/imgact.h>
112#include <sys/msgbuf.h>
113#include <sys/ptrace.h>
114
115#include <vm/vm.h>
116#include <vm/pmap.h>
117#include <vm/vm_page.h>
118#include <vm/vm_object.h>
119#include <vm/vm_pager.h>
120
121#include <machine/cpu.h>
122#include <machine/kdb.h>
123#include <machine/reg.h>
124#include <machine/vmparam.h>
125#include <machine/spr.h>
126#include <machine/hid.h>
127#include <machine/psl.h>
128#include <machine/trap.h>
129#include <machine/md_var.h>
130#include <machine/mmuvar.h>
131#include <machine/sigframe.h>
132#include <machine/metadata.h>
133#include <machine/platform.h>
134
135#include <sys/linker.h>
136#include <sys/reboot.h>
137
138#include <dev/fdt/fdt_common.h>
139#include <dev/ofw/openfirm.h>
140
141#include <powerpc/mpc85xx/mpc85xx.h>
142
143#ifdef DDB
144extern vm_offset_t ksym_start, ksym_end;
145#endif
146
147#ifdef DEBUG
148#define debugf(fmt, args...) printf(fmt, ##args)
149#else
150#define debugf(fmt, args...)
151#endif
152
153extern unsigned char kernel_text[];
154extern unsigned char _etext[];
155extern unsigned char _edata[];
156extern unsigned char __bss_start[];
157extern unsigned char __sbss_start[];
158extern unsigned char __sbss_end[];
159extern unsigned char _end[];
160
161extern void dcache_enable(void);
162extern void dcache_inval(void);
163extern void icache_enable(void);
164extern void icache_inval(void);
165
166struct kva_md_info kmi;
167struct pcpu __pcpu[MAXCPU];
168struct trapframe frame0;
169int cold = 1;
170long realmem = 0;
171long Maxmem = 0;
172
173char machine[] = "powerpc";
174SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "");
175
176int cacheline_size = 32;
177
178SYSCTL_INT(_machdep, CPU_CACHELINE, cacheline_size,
179 CTLFLAG_RD, &cacheline_size, 0, "");
180
181int hw_direct_map = 0;
182
183static void cpu_e500_startup(void *);
184SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_e500_startup, NULL);
185
186void print_kernel_section_addr(void);
187void print_kenv(void);
188u_int e500_init(u_int32_t, u_int32_t, void *);
189
190static void
191cpu_e500_startup(void *dummy)
192{
193 int indx, size;
194
195 /* Initialise the decrementer-based clock. */
196 decr_init();
197
198 /* Good {morning,afternoon,evening,night}. */
199 cpu_setup(PCPU_GET(cpuid));
200
201 printf("real memory = %ld (%ld MB)\n", ptoa(physmem),
202 ptoa(physmem) / 1048576);
203 realmem = physmem;
204
205 /* Display any holes after the first chunk of extended memory. */
206 if (bootverbose) {
207 printf("Physical memory chunk(s):\n");
208 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
209 size = phys_avail[indx + 1] - phys_avail[indx];
210
211 printf("0x%08x - 0x%08x, %d bytes (%ld pages)\n",
212 phys_avail[indx], phys_avail[indx + 1] - 1,
213 size, size / PAGE_SIZE);
214 }
215 }
216
217 vm_ksubmap_init(&kmi);
218
219 printf("avail memory = %ld (%ld MB)\n", ptoa(cnt.v_free_count),
220 ptoa(cnt.v_free_count) / 1048576);
221
222 /* Set up buffers, so they can be used to read disk labels. */
223 bufinit();
224 vm_pager_bufferinit();
225}
226
227static char *
228kenv_next(char *cp)
229{
230
231 if (cp != NULL) {
232 while (*cp != 0)
233 cp++;
234 cp++;
235 if (*cp == 0)
236 cp = NULL;
237 }
238 return (cp);
239}
240
241void
242print_kenv(void)
243{
244 int len;
245 char *cp;
246
247 debugf("loader passed (static) kenv:\n");
248 if (kern_envp == NULL) {
249 debugf(" no env, null ptr\n");
250 return;
251 }
252 debugf(" kern_envp = 0x%08x\n", (u_int32_t)kern_envp);
253
254 len = 0;
255 for (cp = kern_envp; cp != NULL; cp = kenv_next(cp))
256 debugf(" %x %s\n", (u_int32_t)cp, cp);
257}
258
259void
260print_kernel_section_addr(void)
261{
262
263 debugf("kernel image addresses:\n");
264 debugf(" kernel_text = 0x%08x\n", (uint32_t)kernel_text);
265 debugf(" _etext (sdata) = 0x%08x\n", (uint32_t)_etext);
266 debugf(" _edata = 0x%08x\n", (uint32_t)_edata);
267 debugf(" __sbss_start = 0x%08x\n", (uint32_t)__sbss_start);
268 debugf(" __sbss_end = 0x%08x\n", (uint32_t)__sbss_end);
269 debugf(" __sbss_start = 0x%08x\n", (uint32_t)__bss_start);
270 debugf(" _end = 0x%08x\n", (uint32_t)_end);
271}
272
273u_int
274e500_init(u_int32_t startkernel, u_int32_t endkernel, void *mdp)
275{
276 struct pcpu *pc;
277 void *kmdp;
278 vm_offset_t dtbp, end;
279 uint32_t csr;
280
281 kmdp = NULL;
282
283 end = endkernel;
284 dtbp = (vm_offset_t)NULL;
285
286 /*
287 * Parse metadata and fetch parameters.
288 */
289 if (mdp != NULL) {
290 preload_metadata = mdp;
291 kmdp = preload_search_by_type("elf kernel");
292 if (kmdp != NULL) {
293 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
294 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *);
295 dtbp = MD_FETCH(kmdp, MODINFOMD_DTBP, vm_offset_t);
296 end = MD_FETCH(kmdp, MODINFOMD_KERNEND, vm_offset_t);
297#ifdef DDB
298 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
299 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
300#endif
301 }
302 } else {
303 /*
304 * We should scream but how? Cannot even output anything...
305 */
306
307 /*
308 * FIXME add return value and handle in the locore so we can
309 * return to the loader maybe? (this seems not very easy to
310 * restore everything as the TLB have all been reprogrammed
311 * in the locore etc...)
312 */
313 while (1);
314 }
315
316 if (OF_install(OFW_FDT, 0) == FALSE)
317 while (1);
318
319 if (OF_init((void *)dtbp) != 0)
320 while (1);
321
322 if (fdt_immr_addr(CCSRBAR_VA) != 0)
323 while (1);
324
325 OF_interpret("perform-fixup", 0);
326
327 /* Initialize TLB1 handling */
328 tlb1_init(fdt_immr_pa);
329
330 /* Reset Time Base */
331 mttb(0);
332
333 /* Init params/tunables that can be overridden by the loader. */
334 init_param1();
335
336 /* Start initializing proc0 and thread0. */
337 proc_linkup0(&proc0, &thread0);
338 thread0.td_frame = &frame0;
339
340 /* Set up per-cpu data and store the pointer in SPR general 0. */
341 pc = &__pcpu[0];
342 pcpu_init(pc, 0, sizeof(struct pcpu));
343 pc->pc_curthread = &thread0;
344 __asm __volatile("mtsprg 0, %0" :: "r"(pc));
345
346 /* Initialize system mutexes. */
347 mutex_init();
348
349 /* Initialize the console before printing anything. */
350 cninit();
351
352 /* Print out some debug info... */
353 debugf("e500_init: console initialized\n");
354 debugf(" arg1 startkernel = 0x%08x\n", startkernel);
355 debugf(" arg2 endkernel = 0x%08x\n", endkernel);
356 debugf(" arg3 mdp = 0x%08x\n", (u_int32_t)mdp);
357 debugf(" end = 0x%08x\n", (u_int32_t)end);
358 debugf(" boothowto = 0x%08x\n", boothowto);
359 debugf(" kernel ccsrbar = 0x%08x\n", CCSRBAR_VA);
360 debugf(" MSR = 0x%08x\n", mfmsr());
361 debugf(" HID0 = 0x%08x\n", mfspr(SPR_HID0));
362 debugf(" HID1 = 0x%08x\n", mfspr(SPR_HID1));
363 debugf(" BUCSR = 0x%08x\n", mfspr(SPR_BUCSR));
364
365 __asm __volatile("msync; isync");
366 csr = ccsr_read4(OCP85XX_L2CTL);
367 debugf(" L2CTL = 0x%08x\n", csr);
368
369 debugf(" dtbp = 0x%08x\n", (uint32_t)dtbp);
370
371 print_kernel_section_addr();
372 print_kenv();
373 //tlb1_print_entries();
374 //tlb1_print_tlbentries();
375
376 kdb_init();
377
378#ifdef KDB
379 if (boothowto & RB_KDB)
380 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
381#endif
382
383 /* Initialise platform module */
384 platform_probe_and_attach();
385
386 /* Initialise virtual memory. */
387 pmap_mmu_install(MMU_TYPE_BOOKE, 0);
388 pmap_bootstrap(startkernel, end);
389 debugf("MSR = 0x%08x\n", mfmsr());
390 //tlb1_print_entries();
391 //tlb1_print_tlbentries();
392
393 /* Initialize params/tunables that are derived from memsize. */
394 init_param2(physmem);
395
396 /* Finish setting up thread0. */
397 thread0.td_pcb = (struct pcb *)
398 ((thread0.td_kstack + thread0.td_kstack_pages * PAGE_SIZE -
399 sizeof(struct pcb)) & ~15);
400 bzero((void *)thread0.td_pcb, sizeof(struct pcb));
401 pc->pc_curpcb = thread0.td_pcb;
402
403 /* Initialise the message buffer. */
404 msgbufinit(msgbufp, MSGBUF_SIZE);
405
406 /* Enable Machine Check interrupt. */
407 mtmsr(mfmsr() | PSL_ME);
408 isync();
409
410 /* Enable D-cache if applicable */
411 csr = mfspr(SPR_L1CSR0);
412 if ((csr & L1CSR0_DCE) == 0) {
413 dcache_inval();
414 dcache_enable();
415 }
416
417 csr = mfspr(SPR_L1CSR0);
418 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0)
419 printf("L1 D-cache %sabled\n",
420 (csr & L1CSR0_DCE) ? "en" : "dis");
421
422 /* Enable L1 I-cache if applicable. */
423 csr = mfspr(SPR_L1CSR1);
424 if ((csr & L1CSR1_ICE) == 0) {
425 icache_inval();
426 icache_enable();
427 }
428
429 csr = mfspr(SPR_L1CSR1);
430 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0)
431 printf("L1 I-cache %sabled\n",
432 (csr & L1CSR1_ICE) ? "en" : "dis");
433
434 debugf("e500_init: SP = 0x%08x\n", ((uintptr_t)thread0.td_pcb - 16) & ~15);
435 debugf("e500_init: e\n");
436
437 return (((uintptr_t)thread0.td_pcb - 16) & ~15);
438}
439
440#define RES_GRANULE 32
441extern uint32_t tlb0_miss_locks[];
442
443/* Initialise a struct pcpu. */
444void
445cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz)
446{
447
448 pcpu->pc_tid_next = TID_MIN;
449
450#ifdef SMP
451 uint32_t *ptr;
452 int words_per_gran = RES_GRANULE / sizeof(uint32_t);
453
454 ptr = &tlb0_miss_locks[cpuid * words_per_gran];
455 pcpu->pc_booke_tlb_lock = ptr;
456 *ptr = TLB_UNLOCKED;
457 *(ptr + 1) = 0; /* recurse counter */
458#endif
459}
460
461/*
462 * Flush the D-cache for non-DMA I/O so that the I-cache can
463 * be made coherent later.
464 */
465void
466cpu_flush_dcache(void *ptr, size_t len)
467{
468 /* TBD */
469}
470
471void
472spinlock_enter(void)
473{
474 struct thread *td;
475 register_t msr;
476
477 td = curthread;
478 if (td->td_md.md_spinlock_count == 0) {
479 msr = intr_disable();
480 td->td_md.md_spinlock_count = 1;
481 td->td_md.md_saved_msr = msr;
482 } else
483 td->td_md.md_spinlock_count++;
484 critical_enter();
485}
486
487void
488spinlock_exit(void)
489{
490 struct thread *td;
491 register_t msr;
492
493 td = curthread;
494 critical_exit();
495 msr = td->td_md.md_saved_msr;
496 td->td_md.md_spinlock_count--;
497 if (td->td_md.md_spinlock_count == 0)
498 intr_restore(msr);
499}
500
501/* Shutdown the CPU as much as possible. */
502void
503cpu_halt(void)
504{
505
506 mtmsr(mfmsr() & ~(PSL_CE | PSL_EE | PSL_ME | PSL_DE));
507 while (1);
508}
509
510int
511ptrace_set_pc(struct thread *td, unsigned long addr)
512{
513 struct trapframe *tf;
514
515 tf = td->td_frame;
516 tf->srr0 = (register_t)addr;
517
518 return (0);
519}
520
521int
522ptrace_single_step(struct thread *td)
523{
524 struct trapframe *tf;
525
526 tf = td->td_frame;
527 tf->srr1 |= PSL_DE;
528 tf->cpu.booke.dbcr0 |= (DBCR0_IDM | DBCR0_IC);
529 return (0);
530}
531
532int
533ptrace_clear_single_step(struct thread *td)
534{
535 struct trapframe *tf;
536
537 tf = td->td_frame;
538 tf->srr1 &= ~PSL_DE;
539 tf->cpu.booke.dbcr0 &= ~(DBCR0_IDM | DBCR0_IC);
540 return (0);
541}
542
543void
544kdb_cpu_clear_singlestep(void)
545{
546 register_t r;
547
548 r = mfspr(SPR_DBCR0);
549 mtspr(SPR_DBCR0, r & ~DBCR0_IC);
550 kdb_frame->srr1 &= ~PSL_DE;
551}
552
553void
554kdb_cpu_set_singlestep(void)
555{
556 register_t r;
557
558 r = mfspr(SPR_DBCR0);
559 mtspr(SPR_DBCR0, r | DBCR0_IC | DBCR0_IDM);
560 kdb_frame->srr1 |= PSL_DE;
561}
562
563void
564bzero(void *buf, size_t len)
565{
566 caddr_t p;
567
568 p = buf;
569
570 while (((vm_offset_t) p & (sizeof(u_long) - 1)) && len) {
571 *p++ = 0;
572 len--;
573 }
574
575 while (len >= sizeof(u_long) * 8) {
576 *(u_long*) p = 0;
577 *((u_long*) p + 1) = 0;
578 *((u_long*) p + 2) = 0;
579 *((u_long*) p + 3) = 0;
580 len -= sizeof(u_long) * 8;
581 *((u_long*) p + 4) = 0;
582 *((u_long*) p + 5) = 0;
583 *((u_long*) p + 6) = 0;
584 *((u_long*) p + 7) = 0;
585 p += sizeof(u_long) * 8;
586 }
587
588 while (len >= sizeof(u_long)) {
589 *(u_long*) p = 0;
590 len -= sizeof(u_long);
591 p += sizeof(u_long);
592 }
593
594 while (len) {
595 *p++ = 0;
596 len--;
597 }
598}
599
| 83
84#include "opt_compat.h"
85#include "opt_ddb.h"
86#include "opt_kstack_pages.h"
87#include "opt_msgbuf.h"
88
89#include <sys/cdefs.h>
90#include <sys/types.h>
91#include <sys/param.h>
92#include <sys/proc.h>
93#include <sys/systm.h>
94#include <sys/time.h>
95#include <sys/bio.h>
96#include <sys/buf.h>
97#include <sys/bus.h>
98#include <sys/cons.h>
99#include <sys/cpu.h>
100#include <sys/kdb.h>
101#include <sys/kernel.h>
102#include <sys/lock.h>
103#include <sys/mutex.h>
104#include <sys/sysctl.h>
105#include <sys/exec.h>
106#include <sys/ktr.h>
107#include <sys/syscallsubr.h>
108#include <sys/sysproto.h>
109#include <sys/signalvar.h>
110#include <sys/sysent.h>
111#include <sys/imgact.h>
112#include <sys/msgbuf.h>
113#include <sys/ptrace.h>
114
115#include <vm/vm.h>
116#include <vm/pmap.h>
117#include <vm/vm_page.h>
118#include <vm/vm_object.h>
119#include <vm/vm_pager.h>
120
121#include <machine/cpu.h>
122#include <machine/kdb.h>
123#include <machine/reg.h>
124#include <machine/vmparam.h>
125#include <machine/spr.h>
126#include <machine/hid.h>
127#include <machine/psl.h>
128#include <machine/trap.h>
129#include <machine/md_var.h>
130#include <machine/mmuvar.h>
131#include <machine/sigframe.h>
132#include <machine/metadata.h>
133#include <machine/platform.h>
134
135#include <sys/linker.h>
136#include <sys/reboot.h>
137
138#include <dev/fdt/fdt_common.h>
139#include <dev/ofw/openfirm.h>
140
141#include <powerpc/mpc85xx/mpc85xx.h>
142
143#ifdef DDB
144extern vm_offset_t ksym_start, ksym_end;
145#endif
146
147#ifdef DEBUG
148#define debugf(fmt, args...) printf(fmt, ##args)
149#else
150#define debugf(fmt, args...)
151#endif
152
153extern unsigned char kernel_text[];
154extern unsigned char _etext[];
155extern unsigned char _edata[];
156extern unsigned char __bss_start[];
157extern unsigned char __sbss_start[];
158extern unsigned char __sbss_end[];
159extern unsigned char _end[];
160
161extern void dcache_enable(void);
162extern void dcache_inval(void);
163extern void icache_enable(void);
164extern void icache_inval(void);
165
166struct kva_md_info kmi;
167struct pcpu __pcpu[MAXCPU];
168struct trapframe frame0;
169int cold = 1;
170long realmem = 0;
171long Maxmem = 0;
172
173char machine[] = "powerpc";
174SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "");
175
176int cacheline_size = 32;
177
178SYSCTL_INT(_machdep, CPU_CACHELINE, cacheline_size,
179 CTLFLAG_RD, &cacheline_size, 0, "");
180
181int hw_direct_map = 0;
182
183static void cpu_e500_startup(void *);
184SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_e500_startup, NULL);
185
186void print_kernel_section_addr(void);
187void print_kenv(void);
188u_int e500_init(u_int32_t, u_int32_t, void *);
189
190static void
191cpu_e500_startup(void *dummy)
192{
193 int indx, size;
194
195 /* Initialise the decrementer-based clock. */
196 decr_init();
197
198 /* Good {morning,afternoon,evening,night}. */
199 cpu_setup(PCPU_GET(cpuid));
200
201 printf("real memory = %ld (%ld MB)\n", ptoa(physmem),
202 ptoa(physmem) / 1048576);
203 realmem = physmem;
204
205 /* Display any holes after the first chunk of extended memory. */
206 if (bootverbose) {
207 printf("Physical memory chunk(s):\n");
208 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
209 size = phys_avail[indx + 1] - phys_avail[indx];
210
211 printf("0x%08x - 0x%08x, %d bytes (%ld pages)\n",
212 phys_avail[indx], phys_avail[indx + 1] - 1,
213 size, size / PAGE_SIZE);
214 }
215 }
216
217 vm_ksubmap_init(&kmi);
218
219 printf("avail memory = %ld (%ld MB)\n", ptoa(cnt.v_free_count),
220 ptoa(cnt.v_free_count) / 1048576);
221
222 /* Set up buffers, so they can be used to read disk labels. */
223 bufinit();
224 vm_pager_bufferinit();
225}
226
227static char *
228kenv_next(char *cp)
229{
230
231 if (cp != NULL) {
232 while (*cp != 0)
233 cp++;
234 cp++;
235 if (*cp == 0)
236 cp = NULL;
237 }
238 return (cp);
239}
240
241void
242print_kenv(void)
243{
244 int len;
245 char *cp;
246
247 debugf("loader passed (static) kenv:\n");
248 if (kern_envp == NULL) {
249 debugf(" no env, null ptr\n");
250 return;
251 }
252 debugf(" kern_envp = 0x%08x\n", (u_int32_t)kern_envp);
253
254 len = 0;
255 for (cp = kern_envp; cp != NULL; cp = kenv_next(cp))
256 debugf(" %x %s\n", (u_int32_t)cp, cp);
257}
258
259void
260print_kernel_section_addr(void)
261{
262
263 debugf("kernel image addresses:\n");
264 debugf(" kernel_text = 0x%08x\n", (uint32_t)kernel_text);
265 debugf(" _etext (sdata) = 0x%08x\n", (uint32_t)_etext);
266 debugf(" _edata = 0x%08x\n", (uint32_t)_edata);
267 debugf(" __sbss_start = 0x%08x\n", (uint32_t)__sbss_start);
268 debugf(" __sbss_end = 0x%08x\n", (uint32_t)__sbss_end);
269 debugf(" __sbss_start = 0x%08x\n", (uint32_t)__bss_start);
270 debugf(" _end = 0x%08x\n", (uint32_t)_end);
271}
272
273u_int
274e500_init(u_int32_t startkernel, u_int32_t endkernel, void *mdp)
275{
276 struct pcpu *pc;
277 void *kmdp;
278 vm_offset_t dtbp, end;
279 uint32_t csr;
280
281 kmdp = NULL;
282
283 end = endkernel;
284 dtbp = (vm_offset_t)NULL;
285
286 /*
287 * Parse metadata and fetch parameters.
288 */
289 if (mdp != NULL) {
290 preload_metadata = mdp;
291 kmdp = preload_search_by_type("elf kernel");
292 if (kmdp != NULL) {
293 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
294 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *);
295 dtbp = MD_FETCH(kmdp, MODINFOMD_DTBP, vm_offset_t);
296 end = MD_FETCH(kmdp, MODINFOMD_KERNEND, vm_offset_t);
297#ifdef DDB
298 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
299 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
300#endif
301 }
302 } else {
303 /*
304 * We should scream but how? Cannot even output anything...
305 */
306
307 /*
308 * FIXME add return value and handle in the locore so we can
309 * return to the loader maybe? (this seems not very easy to
310 * restore everything as the TLB have all been reprogrammed
311 * in the locore etc...)
312 */
313 while (1);
314 }
315
316 if (OF_install(OFW_FDT, 0) == FALSE)
317 while (1);
318
319 if (OF_init((void *)dtbp) != 0)
320 while (1);
321
322 if (fdt_immr_addr(CCSRBAR_VA) != 0)
323 while (1);
324
325 OF_interpret("perform-fixup", 0);
326
327 /* Initialize TLB1 handling */
328 tlb1_init(fdt_immr_pa);
329
330 /* Reset Time Base */
331 mttb(0);
332
333 /* Init params/tunables that can be overridden by the loader. */
334 init_param1();
335
336 /* Start initializing proc0 and thread0. */
337 proc_linkup0(&proc0, &thread0);
338 thread0.td_frame = &frame0;
339
340 /* Set up per-cpu data and store the pointer in SPR general 0. */
341 pc = &__pcpu[0];
342 pcpu_init(pc, 0, sizeof(struct pcpu));
343 pc->pc_curthread = &thread0;
344 __asm __volatile("mtsprg 0, %0" :: "r"(pc));
345
346 /* Initialize system mutexes. */
347 mutex_init();
348
349 /* Initialize the console before printing anything. */
350 cninit();
351
352 /* Print out some debug info... */
353 debugf("e500_init: console initialized\n");
354 debugf(" arg1 startkernel = 0x%08x\n", startkernel);
355 debugf(" arg2 endkernel = 0x%08x\n", endkernel);
356 debugf(" arg3 mdp = 0x%08x\n", (u_int32_t)mdp);
357 debugf(" end = 0x%08x\n", (u_int32_t)end);
358 debugf(" boothowto = 0x%08x\n", boothowto);
359 debugf(" kernel ccsrbar = 0x%08x\n", CCSRBAR_VA);
360 debugf(" MSR = 0x%08x\n", mfmsr());
361 debugf(" HID0 = 0x%08x\n", mfspr(SPR_HID0));
362 debugf(" HID1 = 0x%08x\n", mfspr(SPR_HID1));
363 debugf(" BUCSR = 0x%08x\n", mfspr(SPR_BUCSR));
364
365 __asm __volatile("msync; isync");
366 csr = ccsr_read4(OCP85XX_L2CTL);
367 debugf(" L2CTL = 0x%08x\n", csr);
368
369 debugf(" dtbp = 0x%08x\n", (uint32_t)dtbp);
370
371 print_kernel_section_addr();
372 print_kenv();
373 //tlb1_print_entries();
374 //tlb1_print_tlbentries();
375
376 kdb_init();
377
378#ifdef KDB
379 if (boothowto & RB_KDB)
380 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
381#endif
382
383 /* Initialise platform module */
384 platform_probe_and_attach();
385
386 /* Initialise virtual memory. */
387 pmap_mmu_install(MMU_TYPE_BOOKE, 0);
388 pmap_bootstrap(startkernel, end);
389 debugf("MSR = 0x%08x\n", mfmsr());
390 //tlb1_print_entries();
391 //tlb1_print_tlbentries();
392
393 /* Initialize params/tunables that are derived from memsize. */
394 init_param2(physmem);
395
396 /* Finish setting up thread0. */
397 thread0.td_pcb = (struct pcb *)
398 ((thread0.td_kstack + thread0.td_kstack_pages * PAGE_SIZE -
399 sizeof(struct pcb)) & ~15);
400 bzero((void *)thread0.td_pcb, sizeof(struct pcb));
401 pc->pc_curpcb = thread0.td_pcb;
402
403 /* Initialise the message buffer. */
404 msgbufinit(msgbufp, MSGBUF_SIZE);
405
406 /* Enable Machine Check interrupt. */
407 mtmsr(mfmsr() | PSL_ME);
408 isync();
409
410 /* Enable D-cache if applicable */
411 csr = mfspr(SPR_L1CSR0);
412 if ((csr & L1CSR0_DCE) == 0) {
413 dcache_inval();
414 dcache_enable();
415 }
416
417 csr = mfspr(SPR_L1CSR0);
418 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0)
419 printf("L1 D-cache %sabled\n",
420 (csr & L1CSR0_DCE) ? "en" : "dis");
421
422 /* Enable L1 I-cache if applicable. */
423 csr = mfspr(SPR_L1CSR1);
424 if ((csr & L1CSR1_ICE) == 0) {
425 icache_inval();
426 icache_enable();
427 }
428
429 csr = mfspr(SPR_L1CSR1);
430 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0)
431 printf("L1 I-cache %sabled\n",
432 (csr & L1CSR1_ICE) ? "en" : "dis");
433
434 debugf("e500_init: SP = 0x%08x\n", ((uintptr_t)thread0.td_pcb - 16) & ~15);
435 debugf("e500_init: e\n");
436
437 return (((uintptr_t)thread0.td_pcb - 16) & ~15);
438}
439
440#define RES_GRANULE 32
441extern uint32_t tlb0_miss_locks[];
442
443/* Initialise a struct pcpu. */
444void
445cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz)
446{
447
448 pcpu->pc_tid_next = TID_MIN;
449
450#ifdef SMP
451 uint32_t *ptr;
452 int words_per_gran = RES_GRANULE / sizeof(uint32_t);
453
454 ptr = &tlb0_miss_locks[cpuid * words_per_gran];
455 pcpu->pc_booke_tlb_lock = ptr;
456 *ptr = TLB_UNLOCKED;
457 *(ptr + 1) = 0; /* recurse counter */
458#endif
459}
460
461/*
462 * Flush the D-cache for non-DMA I/O so that the I-cache can
463 * be made coherent later.
464 */
465void
466cpu_flush_dcache(void *ptr, size_t len)
467{
468 /* TBD */
469}
470
471void
472spinlock_enter(void)
473{
474 struct thread *td;
475 register_t msr;
476
477 td = curthread;
478 if (td->td_md.md_spinlock_count == 0) {
479 msr = intr_disable();
480 td->td_md.md_spinlock_count = 1;
481 td->td_md.md_saved_msr = msr;
482 } else
483 td->td_md.md_spinlock_count++;
484 critical_enter();
485}
486
487void
488spinlock_exit(void)
489{
490 struct thread *td;
491 register_t msr;
492
493 td = curthread;
494 critical_exit();
495 msr = td->td_md.md_saved_msr;
496 td->td_md.md_spinlock_count--;
497 if (td->td_md.md_spinlock_count == 0)
498 intr_restore(msr);
499}
500
501/* Shutdown the CPU as much as possible. */
502void
503cpu_halt(void)
504{
505
506 mtmsr(mfmsr() & ~(PSL_CE | PSL_EE | PSL_ME | PSL_DE));
507 while (1);
508}
509
510int
511ptrace_set_pc(struct thread *td, unsigned long addr)
512{
513 struct trapframe *tf;
514
515 tf = td->td_frame;
516 tf->srr0 = (register_t)addr;
517
518 return (0);
519}
520
521int
522ptrace_single_step(struct thread *td)
523{
524 struct trapframe *tf;
525
526 tf = td->td_frame;
527 tf->srr1 |= PSL_DE;
528 tf->cpu.booke.dbcr0 |= (DBCR0_IDM | DBCR0_IC);
529 return (0);
530}
531
532int
533ptrace_clear_single_step(struct thread *td)
534{
535 struct trapframe *tf;
536
537 tf = td->td_frame;
538 tf->srr1 &= ~PSL_DE;
539 tf->cpu.booke.dbcr0 &= ~(DBCR0_IDM | DBCR0_IC);
540 return (0);
541}
542
543void
544kdb_cpu_clear_singlestep(void)
545{
546 register_t r;
547
548 r = mfspr(SPR_DBCR0);
549 mtspr(SPR_DBCR0, r & ~DBCR0_IC);
550 kdb_frame->srr1 &= ~PSL_DE;
551}
552
553void
554kdb_cpu_set_singlestep(void)
555{
556 register_t r;
557
558 r = mfspr(SPR_DBCR0);
559 mtspr(SPR_DBCR0, r | DBCR0_IC | DBCR0_IDM);
560 kdb_frame->srr1 |= PSL_DE;
561}
562
563void
564bzero(void *buf, size_t len)
565{
566 caddr_t p;
567
568 p = buf;
569
570 while (((vm_offset_t) p & (sizeof(u_long) - 1)) && len) {
571 *p++ = 0;
572 len--;
573 }
574
575 while (len >= sizeof(u_long) * 8) {
576 *(u_long*) p = 0;
577 *((u_long*) p + 1) = 0;
578 *((u_long*) p + 2) = 0;
579 *((u_long*) p + 3) = 0;
580 len -= sizeof(u_long) * 8;
581 *((u_long*) p + 4) = 0;
582 *((u_long*) p + 5) = 0;
583 *((u_long*) p + 6) = 0;
584 *((u_long*) p + 7) = 0;
585 p += sizeof(u_long) * 8;
586 }
587
588 while (len >= sizeof(u_long)) {
589 *(u_long*) p = 0;
590 len -= sizeof(u_long);
591 p += sizeof(u_long);
592 }
593
594 while (len) {
595 *p++ = 0;
596 len--;
597 }
598}
599
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