| locore.S (236141) | locore.S (242526) |
|---|---|
| 1/*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 9 unchanged lines hidden (view full) --- 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 9 unchanged lines hidden (view full) --- 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/powerpc/booke/locore.S 236141 2012-05-27 10:25:20Z raj $ | 26 * $FreeBSD: head/sys/powerpc/booke/locore.S 242526 2012-11-03 22:02:12Z marcel $ |
| 27 */ 28 29#include "assym.s" 30 31#include <machine/asm.h> 32#include <machine/hid.h> 33#include <machine/param.h> 34#include <machine/spr.h> --- 86 unchanged lines hidden (view full) --- 121/* 122 * Locate the TLB1 entry that maps this code 123 */ 124 bl 1f 1251: mflr %r3 126 bl tlb1_find_current /* the entry found is returned in r29 */ 127 128 bl tlb1_inval_all_but_current | 27 */ 28 29#include "assym.s" 30 31#include <machine/asm.h> 32#include <machine/hid.h> 33#include <machine/param.h> 34#include <machine/spr.h> --- 86 unchanged lines hidden (view full) --- 121/* 122 * Locate the TLB1 entry that maps this code 123 */ 124 bl 1f 1251: mflr %r3 126 bl tlb1_find_current /* the entry found is returned in r29 */ 127 128 bl tlb1_inval_all_but_current |
| 129 |
|
| 129/* 130 * Create temporary mapping in AS=1 and switch to it 131 */ | 130/* 131 * Create temporary mapping in AS=1 and switch to it 132 */ |
| 133 addi %r3, %r29, 1 |
|
| 132 bl tlb1_temp_mapping_as1 133 134 mfmsr %r3 135 ori %r3, %r3, (PSL_IS | PSL_DS) 136 bl 2f 1372: mflr %r4 138 addi %r4, %r4, 20 139 mtspr SPR_SRR0, %r4 --- 97 unchanged lines hidden (view full) --- 237/* AP Boot page */ 238/************************************************************************/ 239 .text 240 .globl __boot_page 241 .align 12 242__boot_page: 243 bl 1f 244 | 134 bl tlb1_temp_mapping_as1 135 136 mfmsr %r3 137 ori %r3, %r3, (PSL_IS | PSL_DS) 138 bl 2f 1392: mflr %r4 140 addi %r4, %r4, 20 141 mtspr SPR_SRR0, %r4 --- 97 unchanged lines hidden (view full) --- 239/* AP Boot page */ 240/************************************************************************/ 241 .text 242 .globl __boot_page 243 .align 12 244__boot_page: 245 bl 1f 246 |
| 245 .globl bp_trace 246bp_trace: | 247 .globl bp_ntlb1s 248bp_ntlb1s: |
| 247 .long 0 248 | 249 .long 0 250 |
| 249 .globl bp_kernload 250bp_kernload: 251 .long 0 | 251 .globl bp_tlb1 252bp_tlb1: 253 .space 4 * 3 * 16 |
| 252 | 254 |
| 255 .globl bp_tlb1_end 256bp_tlb1_end: 257 |
|
| 253/* 254 * Initial configuration 255 */ | 258/* 259 * Initial configuration 260 */ |
| 2561: 257 mflr %r31 /* r31 hold the address of bp_trace */ | 2611: mflr %r31 /* r31 hold the address of bp_ntlb1s */ |
| 258 259 /* Set HIDs */ 260 lis %r3, HID0_E500_DEFAULT_SET@h 261 ori %r3, %r3, HID0_E500_DEFAULT_SET@l 262 mtspr SPR_HID0, %r3 263 isync 264 lis %r3, HID1_E500_DEFAULT_SET@h 265 ori %r3, %r3, HID1_E500_DEFAULT_SET@l --- 12 unchanged lines hidden (view full) --- 278/* 279 * Find TLB1 entry which is translating us now 280 */ 281 bl 2f 2822: mflr %r3 283 bl tlb1_find_current /* the entry number found is in r29 */ 284 285 bl tlb1_inval_all_but_current | 262 263 /* Set HIDs */ 264 lis %r3, HID0_E500_DEFAULT_SET@h 265 ori %r3, %r3, HID0_E500_DEFAULT_SET@l 266 mtspr SPR_HID0, %r3 267 isync 268 lis %r3, HID1_E500_DEFAULT_SET@h 269 ori %r3, %r3, HID1_E500_DEFAULT_SET@l --- 12 unchanged lines hidden (view full) --- 282/* 283 * Find TLB1 entry which is translating us now 284 */ 285 bl 2f 2862: mflr %r3 287 bl tlb1_find_current /* the entry number found is in r29 */ 288 289 bl tlb1_inval_all_but_current |
| 290 |
|
| 286/* 287 * Create temporary translation in AS=1 and switch to it 288 */ | 291/* 292 * Create temporary translation in AS=1 and switch to it 293 */ |
| 294 lwz %r3, 0(%r31) |
|
| 289 bl tlb1_temp_mapping_as1 290 291 mfmsr %r3 292 ori %r3, %r3, (PSL_IS | PSL_DS) 293 bl 3f 2943: mflr %r4 295 addi %r4, %r4, 20 296 mtspr SPR_SRR0, %r4 --- 4 unchanged lines hidden (view full) --- 301 * Invalidate initial entry 302 */ 303 mr %r3, %r29 304 bl tlb1_inval_entry 305 306/* 307 * Setup final mapping in TLB1[1] and switch to it 308 */ | 295 bl tlb1_temp_mapping_as1 296 297 mfmsr %r3 298 ori %r3, %r3, (PSL_IS | PSL_DS) 299 bl 3f 3003: mflr %r4 301 addi %r4, %r4, 20 302 mtspr SPR_SRR0, %r4 --- 4 unchanged lines hidden (view full) --- 307 * Invalidate initial entry 308 */ 309 mr %r3, %r29 310 bl tlb1_inval_entry 311 312/* 313 * Setup final mapping in TLB1[1] and switch to it 314 */ |
| 309 /* Final kernel mapping, map in 16 MB of RAM */ 310 lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */ 311 li %r4, 0 /* Entry 0 */ 312 rlwimi %r3, %r4, 16, 4, 15 | 315 lwz %r6, 0(%r31) 316 addi %r5, %r31, 4 317 li %r4, 0 318 3194: lis %r3, MAS0_TLBSEL1@h 320 rlwimi %r3, %r4, 16, 12, 15 |
| 313 mtspr SPR_MAS0, %r3 314 isync | 321 mtspr SPR_MAS0, %r3 322 isync |
| 315 316 li %r3, (TLB_SIZE_16M << MAS1_TSIZE_SHIFT)@l 317 oris %r3, %r3, (MAS1_VALID | MAS1_IPROT)@h 318 mtspr SPR_MAS1, %r3 /* note TS was not filled, so it's TS=0 */ | 323 lwz %r3, 0(%r5) 324 mtspr SPR_MAS1, %r3 |
| 319 isync | 325 isync |
| 320 321 lis %r3, KERNBASE@h 322 ori %r3, %r3, KERNBASE@l /* EPN = KERNBASE */ 323 ori %r3, %r3, MAS2_M@l /* WIMGE = 0b00100 */ | 326 lwz %r3, 4(%r5) |
| 324 mtspr SPR_MAS2, %r3 325 isync | 327 mtspr SPR_MAS2, %r3 328 isync |
| 326 327 /* Retrieve kernel load [physical] address from bp_kernload */ 328 bl 4f 3294: mflr %r3 330 rlwinm %r3, %r3, 0, 0, 19 331 lis %r4, bp_kernload@h 332 ori %r4, %r4, bp_kernload@l 333 lis %r5, __boot_page@h 334 ori %r5, %r5, __boot_page@l 335 sub %r4, %r4, %r5 /* offset of bp_kernload within __boot_page */ 336 lwzx %r3, %r4, %r3 337 338 /* Set RPN and protection */ 339 ori %r3, %r3, (MAS3_SX | MAS3_SW | MAS3_SR)@l | 329 lwz %r3, 8(%r5) |
| 340 mtspr SPR_MAS3, %r3 341 isync 342 tlbwe 343 isync 344 msync | 330 mtspr SPR_MAS3, %r3 331 isync 332 tlbwe 333 isync 334 msync |
| 335 addi %r5, %r5, 12 336 addi %r4, %r4, 1 337 cmpw %r4, %r6 338 blt 4b |
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| 345 346 /* Switch to the final mapping */ | 339 340 /* Switch to the final mapping */ |
| 341 lis %r5, __boot_page@ha 342 ori %r5, %r5, __boot_page@l |
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| 347 bl 5f 3485: mflr %r3 349 rlwinm %r3, %r3, 0, 0xfff /* Offset from boot page start */ 350 add %r3, %r3, %r5 /* Make this virtual address */ 351 addi %r3, %r3, 32 352 li %r4, 0 /* Note AS=0 */ 353 mtspr SPR_SRR0, %r3 354 mtspr SPR_SRR1, %r4 --- 100 unchanged lines hidden (view full) --- 455 mtspr SPR_MAS1, %r5 456 isync 457 tlbwe 458 isync 459 msync 460 blr 461 462/* | 343 bl 5f 3445: mflr %r3 345 rlwinm %r3, %r3, 0, 0xfff /* Offset from boot page start */ 346 add %r3, %r3, %r5 /* Make this virtual address */ 347 addi %r3, %r3, 32 348 li %r4, 0 /* Note AS=0 */ 349 mtspr SPR_SRR0, %r3 350 mtspr SPR_SRR1, %r4 --- 100 unchanged lines hidden (view full) --- 451 mtspr SPR_MAS1, %r5 452 isync 453 tlbwe 454 isync 455 msync 456 blr 457 458/* |
| 463 * r29 current entry number 464 * r28 returned temp entry 465 * r3-r5 scratched | 459 * r3 entry of temp translation 460 * r29 entry of current translation 461 * r28 returns temp entry passed in r3 462 * r4-r5 scratched |
| 466 */ 467tlb1_temp_mapping_as1: | 463 */ 464tlb1_temp_mapping_as1: |
| 465 mr %r28, %r3 466 |
|
| 468 /* Read our current translation */ 469 lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */ 470 rlwimi %r3, %r29, 16, 12, 15 /* Select our current entry */ 471 mtspr SPR_MAS0, %r3 472 isync 473 tlbre 474 | 467 /* Read our current translation */ 468 lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */ 469 rlwimi %r3, %r29, 16, 12, 15 /* Select our current entry */ 470 mtspr SPR_MAS0, %r3 471 isync 472 tlbre 473 |
| 475 /* 476 * Prepare and write temp entry 477 * 478 * FIXME this is not robust against overflow i.e. when the current 479 * entry is the last in TLB1 480 */ | 474 /* Prepare and write temp entry */ |
| 481 lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */ | 475 lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */ |
| 482 addi %r28, %r29, 1 /* Use next entry. */ | |
| 483 rlwimi %r3, %r28, 16, 12, 15 /* Select temp entry */ 484 mtspr SPR_MAS0, %r3 485 isync 486 mfspr %r5, SPR_MAS1 487 li %r4, 1 /* AS=1 */ 488 rlwimi %r5, %r4, 12, 19, 19 489 li %r4, 0 /* Global mapping, TID=0 */ 490 rlwimi %r5, %r4, 16, 8, 15 --- 301 unchanged lines hidden --- | 476 rlwimi %r3, %r28, 16, 12, 15 /* Select temp entry */ 477 mtspr SPR_MAS0, %r3 478 isync 479 mfspr %r5, SPR_MAS1 480 li %r4, 1 /* AS=1 */ 481 rlwimi %r5, %r4, 12, 19, 19 482 li %r4, 0 /* Global mapping, TID=0 */ 483 rlwimi %r5, %r4, 16, 8, 15 --- 301 unchanged lines hidden --- |