2/* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */
3
4/*-
5 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
6 * Copyright (C) 1995, 1996 TooLs GmbH.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by TooLs GmbH.
20 * 4. The name of TooLs GmbH may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/*
36 * NOTICE: This is not a standalone file. to use it, #include it in
37 * your port's locore.S, like so:
38 *
39 * #include <powerpc/aim/trap_subr.S>
40 */
41
42/*
43 * Save/restore segment registers
44 */
45
46/*
47 * Restore SRs for a pmap
48 *
49 * Requires that r28-r31 be scratch, with r28 initialized to the SLB cache
50 */
51
52/*
53 * User SRs are loaded through a pointer to the current pmap.
54 */
55restore_usersrs:
56 GET_CPUINFO(%r28);
57 ld %r28,PC_USERSLB(%r28);
58 li %r29, 0 /* Set the counter to zero */
59
60 slbia
61 slbmfee %r31,%r29
62 clrrdi %r31,%r31,28
63 slbie %r31
64instuserslb:
65 ld %r31, 0(%r28); /* Load SLB entry pointer */
66 cmpli 0, %r31, 0; /* If NULL, stop */
67 beqlr;
68
69 ld %r30, 0(%r31) /* Load SLBV */
70 ld %r31, 8(%r31) /* Load SLBE */
71 or %r31, %r31, %r29 /* Set SLBE slot */
72 slbmte %r30, %r31; /* Install SLB entry */
73
74 addi %r28, %r28, 8; /* Advance pointer */
75 addi %r29, %r29, 1;
76 cmpli 0, %r29, 64; /* Repeat if we are not at the end */
77 blt instuserslb;
78 blr;
79
80/*
81 * Kernel SRs are loaded directly from the PCPU fields
82 */
83restore_kernsrs:
84 GET_CPUINFO(%r28);
85 addi %r28,%r28,PC_KERNSLB;
86 li %r29, 0 /* Set the counter to zero */
87
88 slbia
89 slbmfee %r31,%r29
90 clrrdi %r31,%r31,28
91 slbie %r31
92instkernslb:
93 ld %r31, 8(%r28); /* Load SLBE */
94
95 cmpli 0, %r31, 0; /* If SLBE is not valid, stop */
96 beqlr;
97 ld %r30, 0(%r28) /* Load SLBV */
98 slbmte %r30, %r31; /* Install SLB entry */
99
100 addi %r28, %r28, 16; /* Advance pointer */
101 addi %r29, %r29, 1;
102 cmpli 0, %r29, USER_SLB_SLOT; /* Repeat if we are not at the end */
103 blt instkernslb;
104 blr;
105
106/*
107 * FRAME_SETUP assumes:
108 * SPRG1 SP (1)
109 * SPRG3 trap type
110 * savearea r27-r31,DAR,DSISR (DAR & DSISR only for DSI traps)
111 * r28 LR
112 * r29 CR
113 * r30 scratch
114 * r31 scratch
115 * r1 kernel stack
116 * SRR0/1 as at start of trap
117 */
118#define FRAME_SETUP(savearea) \
119/* Have to enable translation to allow access of kernel stack: */ \
120 GET_CPUINFO(%r31); \
121 mfsrr0 %r30; \
122 std %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \
123 mfsrr1 %r30; \
124 std %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \
125 mfmsr %r30; \
126 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \
127 mtmsr %r30; /* stack can now be accessed */ \
128 isync; \
129 mfsprg1 %r31; /* get saved SP */ \
130 stdu %r31,-(FRAMELEN+288)(%r1); /* save it in the callframe */ \
131 std %r0, FRAME_0+48(%r1); /* save r0 in the trapframe */ \
132 std %r31,FRAME_1+48(%r1); /* save SP " " */ \
133 std %r2, FRAME_2+48(%r1); /* save r2 " " */ \
134 std %r28,FRAME_LR+48(%r1); /* save LR " " */ \
135 std %r29,FRAME_CR+48(%r1); /* save CR " " */ \
136 GET_CPUINFO(%r2); \
137 ld %r27,(savearea+CPUSAVE_R27)(%r2); /* get saved r27 */ \
138 ld %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \
139 ld %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \
140 ld %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \
141 ld %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \
142 std %r3, FRAME_3+48(%r1); /* save r3-r31 */ \
143 std %r4, FRAME_4+48(%r1); \
144 std %r5, FRAME_5+48(%r1); \
145 std %r6, FRAME_6+48(%r1); \
146 std %r7, FRAME_7+48(%r1); \
147 std %r8, FRAME_8+48(%r1); \
148 std %r9, FRAME_9+48(%r1); \
149 std %r10, FRAME_10+48(%r1); \
150 std %r11, FRAME_11+48(%r1); \
151 std %r12, FRAME_12+48(%r1); \
152 std %r13, FRAME_13+48(%r1); \
153 std %r14, FRAME_14+48(%r1); \
154 std %r15, FRAME_15+48(%r1); \
155 std %r16, FRAME_16+48(%r1); \
156 std %r17, FRAME_17+48(%r1); \
157 std %r18, FRAME_18+48(%r1); \
158 std %r19, FRAME_19+48(%r1); \
159 std %r20, FRAME_20+48(%r1); \
160 std %r21, FRAME_21+48(%r1); \
161 std %r22, FRAME_22+48(%r1); \
162 std %r23, FRAME_23+48(%r1); \
163 std %r24, FRAME_24+48(%r1); \
164 std %r25, FRAME_25+48(%r1); \
165 std %r26, FRAME_26+48(%r1); \
166 std %r27, FRAME_27+48(%r1); \
167 std %r28, FRAME_28+48(%r1); \
168 std %r29, FRAME_29+48(%r1); \
169 std %r30, FRAME_30+48(%r1); \
170 std %r31, FRAME_31+48(%r1); \
171 ld %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \
172 ld %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\
173 ld %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \
174 ld %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \
175 mfxer %r3; \
176 mfctr %r4; \
177 mfsprg3 %r5; \
178 std %r3, FRAME_XER+48(1); /* save xer/ctr/exc */ \
179 std %r4, FRAME_CTR+48(1); \
180 std %r5, FRAME_EXC+48(1); \
181 std %r28,FRAME_AIM_DAR+48(1); \
182 std %r29,FRAME_AIM_DSISR+48(1); /* save dsisr/srr0/srr1 */ \
183 std %r30,FRAME_SRR0+48(1); \
184 std %r31,FRAME_SRR1+48(1)
185
186#define FRAME_LEAVE(savearea) \
187/* Now restore regs: */ \
188 ld %r2,FRAME_SRR0+48(%r1); \
189 ld %r3,FRAME_SRR1+48(%r1); \
190 ld %r4,FRAME_CTR+48(%r1); \
191 ld %r5,FRAME_XER+48(%r1); \
192 ld %r6,FRAME_LR+48(%r1); \
193 GET_CPUINFO(%r7); \
194 std %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \
195 std %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \
196 ld %r7,FRAME_CR+48(%r1); \
197 mtctr %r4; \
198 mtxer %r5; \
199 mtlr %r6; \
200 mtsprg1 %r7; /* save cr */ \
201 ld %r31,FRAME_31+48(%r1); /* restore r0-31 */ \
202 ld %r30,FRAME_30+48(%r1); \
203 ld %r29,FRAME_29+48(%r1); \
204 ld %r28,FRAME_28+48(%r1); \
205 ld %r27,FRAME_27+48(%r1); \
206 ld %r26,FRAME_26+48(%r1); \
207 ld %r25,FRAME_25+48(%r1); \
208 ld %r24,FRAME_24+48(%r1); \
209 ld %r23,FRAME_23+48(%r1); \
210 ld %r22,FRAME_22+48(%r1); \
211 ld %r21,FRAME_21+48(%r1); \
212 ld %r20,FRAME_20+48(%r1); \
213 ld %r19,FRAME_19+48(%r1); \
214 ld %r18,FRAME_18+48(%r1); \
215 ld %r17,FRAME_17+48(%r1); \
216 ld %r16,FRAME_16+48(%r1); \
217 ld %r15,FRAME_15+48(%r1); \
218 ld %r14,FRAME_14+48(%r1); \
219 ld %r13,FRAME_13+48(%r1); \
220 ld %r12,FRAME_12+48(%r1); \
221 ld %r11,FRAME_11+48(%r1); \
222 ld %r10,FRAME_10+48(%r1); \
223 ld %r9, FRAME_9+48(%r1); \
224 ld %r8, FRAME_8+48(%r1); \
225 ld %r7, FRAME_7+48(%r1); \
226 ld %r6, FRAME_6+48(%r1); \
227 ld %r5, FRAME_5+48(%r1); \
228 ld %r4, FRAME_4+48(%r1); \
229 ld %r3, FRAME_3+48(%r1); \
230 ld %r2, FRAME_2+48(%r1); \
231 ld %r0, FRAME_0+48(%r1); \
232 ld %r1, FRAME_1+48(%r1); \
233/* Can't touch %r1 from here on */ \
234 mtsprg2 %r2; /* save r2 & r3 */ \
235 mtsprg3 %r3; \
236/* Disable translation, machine check and recoverability: */ \
237 mfmsr %r2; \
238 andi. %r2,%r2,~(PSL_DR|PSL_IR|PSL_EE|PSL_ME|PSL_RI)@l; \
239 mtmsr %r2; \
240 isync; \
241/* Decide whether we return to user mode: */ \
242 GET_CPUINFO(%r2); \
243 ld %r3,(savearea+CPUSAVE_SRR1)(%r2); \
244 mtcr %r3; \
245 bf 17,1f; /* branch if PSL_PR is false */ \
246/* Restore user SRs */ \
247 GET_CPUINFO(%r3); \
248 std %r27,(savearea+CPUSAVE_R27)(%r3); \
249 std %r28,(savearea+CPUSAVE_R28)(%r3); \
250 std %r29,(savearea+CPUSAVE_R29)(%r3); \
251 std %r30,(savearea+CPUSAVE_R30)(%r3); \
252 std %r31,(savearea+CPUSAVE_R31)(%r3); \
253 mflr %r27; /* preserve LR */ \
254 bl restore_usersrs; /* uses r28-r31 */ \
255 mtlr %r27; \
256 ld %r31,(savearea+CPUSAVE_R31)(%r3); \
257 ld %r30,(savearea+CPUSAVE_R30)(%r3); \
258 ld %r29,(savearea+CPUSAVE_R29)(%r3); \
259 ld %r28,(savearea+CPUSAVE_R28)(%r3); \
260 ld %r27,(savearea+CPUSAVE_R27)(%r3); \
2611: mfsprg1 %r2; /* restore cr */ \
262 mtcr %r2; \
263 GET_CPUINFO(%r2); \
264 ld %r3,(savearea+CPUSAVE_SRR0)(%r2); /* restore srr0 */ \
265 mtsrr0 %r3; \
266 ld %r3,(savearea+CPUSAVE_SRR1)(%r2); /* restore srr1 */ \
267 mtsrr1 %r3; \
268 mfsprg2 %r2; /* restore r2 & r3 */ \
269 mfsprg3 %r3
270
271#ifdef SMP
272/*
273 * Processor reset exception handler. These are typically
274 * the first instructions the processor executes after a
275 * software reset. We do this in two bits so that we are
276 * not still hanging around in the trap handling region
277 * once the MMU is turned on.
278 */
279 .globl CNAME(rstcode), CNAME(rstsize)
280CNAME(rstcode):
281 /* Explicitly set MSR[SF] */
282 mfmsr %r9
283 li %r8,1
284 insrdi %r9,%r8,1,0
285 mtmsrd %r9
286 isync
287
288 ba cpu_reset
289CNAME(rstsize) = . - CNAME(rstcode)
290
291cpu_reset:
292 lis %r1,(tmpstk+TMPSTKSZ-48)@ha /* get new SP */
293 addi %r1,%r1,(tmpstk+TMPSTKSZ-48)@l
294
295 lis %r3,tocbase@ha
296 ld %r2,tocbase@l(%r3)
297 lis %r3,1@l
| 2/* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */
3
4/*-
5 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
6 * Copyright (C) 1995, 1996 TooLs GmbH.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by TooLs GmbH.
20 * 4. The name of TooLs GmbH may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/*
36 * NOTICE: This is not a standalone file. to use it, #include it in
37 * your port's locore.S, like so:
38 *
39 * #include <powerpc/aim/trap_subr.S>
40 */
41
42/*
43 * Save/restore segment registers
44 */
45
46/*
47 * Restore SRs for a pmap
48 *
49 * Requires that r28-r31 be scratch, with r28 initialized to the SLB cache
50 */
51
52/*
53 * User SRs are loaded through a pointer to the current pmap.
54 */
55restore_usersrs:
56 GET_CPUINFO(%r28);
57 ld %r28,PC_USERSLB(%r28);
58 li %r29, 0 /* Set the counter to zero */
59
60 slbia
61 slbmfee %r31,%r29
62 clrrdi %r31,%r31,28
63 slbie %r31
64instuserslb:
65 ld %r31, 0(%r28); /* Load SLB entry pointer */
66 cmpli 0, %r31, 0; /* If NULL, stop */
67 beqlr;
68
69 ld %r30, 0(%r31) /* Load SLBV */
70 ld %r31, 8(%r31) /* Load SLBE */
71 or %r31, %r31, %r29 /* Set SLBE slot */
72 slbmte %r30, %r31; /* Install SLB entry */
73
74 addi %r28, %r28, 8; /* Advance pointer */
75 addi %r29, %r29, 1;
76 cmpli 0, %r29, 64; /* Repeat if we are not at the end */
77 blt instuserslb;
78 blr;
79
80/*
81 * Kernel SRs are loaded directly from the PCPU fields
82 */
83restore_kernsrs:
84 GET_CPUINFO(%r28);
85 addi %r28,%r28,PC_KERNSLB;
86 li %r29, 0 /* Set the counter to zero */
87
88 slbia
89 slbmfee %r31,%r29
90 clrrdi %r31,%r31,28
91 slbie %r31
92instkernslb:
93 ld %r31, 8(%r28); /* Load SLBE */
94
95 cmpli 0, %r31, 0; /* If SLBE is not valid, stop */
96 beqlr;
97 ld %r30, 0(%r28) /* Load SLBV */
98 slbmte %r30, %r31; /* Install SLB entry */
99
100 addi %r28, %r28, 16; /* Advance pointer */
101 addi %r29, %r29, 1;
102 cmpli 0, %r29, USER_SLB_SLOT; /* Repeat if we are not at the end */
103 blt instkernslb;
104 blr;
105
106/*
107 * FRAME_SETUP assumes:
108 * SPRG1 SP (1)
109 * SPRG3 trap type
110 * savearea r27-r31,DAR,DSISR (DAR & DSISR only for DSI traps)
111 * r28 LR
112 * r29 CR
113 * r30 scratch
114 * r31 scratch
115 * r1 kernel stack
116 * SRR0/1 as at start of trap
117 */
118#define FRAME_SETUP(savearea) \
119/* Have to enable translation to allow access of kernel stack: */ \
120 GET_CPUINFO(%r31); \
121 mfsrr0 %r30; \
122 std %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \
123 mfsrr1 %r30; \
124 std %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \
125 mfmsr %r30; \
126 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \
127 mtmsr %r30; /* stack can now be accessed */ \
128 isync; \
129 mfsprg1 %r31; /* get saved SP */ \
130 stdu %r31,-(FRAMELEN+288)(%r1); /* save it in the callframe */ \
131 std %r0, FRAME_0+48(%r1); /* save r0 in the trapframe */ \
132 std %r31,FRAME_1+48(%r1); /* save SP " " */ \
133 std %r2, FRAME_2+48(%r1); /* save r2 " " */ \
134 std %r28,FRAME_LR+48(%r1); /* save LR " " */ \
135 std %r29,FRAME_CR+48(%r1); /* save CR " " */ \
136 GET_CPUINFO(%r2); \
137 ld %r27,(savearea+CPUSAVE_R27)(%r2); /* get saved r27 */ \
138 ld %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \
139 ld %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \
140 ld %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \
141 ld %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \
142 std %r3, FRAME_3+48(%r1); /* save r3-r31 */ \
143 std %r4, FRAME_4+48(%r1); \
144 std %r5, FRAME_5+48(%r1); \
145 std %r6, FRAME_6+48(%r1); \
146 std %r7, FRAME_7+48(%r1); \
147 std %r8, FRAME_8+48(%r1); \
148 std %r9, FRAME_9+48(%r1); \
149 std %r10, FRAME_10+48(%r1); \
150 std %r11, FRAME_11+48(%r1); \
151 std %r12, FRAME_12+48(%r1); \
152 std %r13, FRAME_13+48(%r1); \
153 std %r14, FRAME_14+48(%r1); \
154 std %r15, FRAME_15+48(%r1); \
155 std %r16, FRAME_16+48(%r1); \
156 std %r17, FRAME_17+48(%r1); \
157 std %r18, FRAME_18+48(%r1); \
158 std %r19, FRAME_19+48(%r1); \
159 std %r20, FRAME_20+48(%r1); \
160 std %r21, FRAME_21+48(%r1); \
161 std %r22, FRAME_22+48(%r1); \
162 std %r23, FRAME_23+48(%r1); \
163 std %r24, FRAME_24+48(%r1); \
164 std %r25, FRAME_25+48(%r1); \
165 std %r26, FRAME_26+48(%r1); \
166 std %r27, FRAME_27+48(%r1); \
167 std %r28, FRAME_28+48(%r1); \
168 std %r29, FRAME_29+48(%r1); \
169 std %r30, FRAME_30+48(%r1); \
170 std %r31, FRAME_31+48(%r1); \
171 ld %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \
172 ld %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\
173 ld %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \
174 ld %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \
175 mfxer %r3; \
176 mfctr %r4; \
177 mfsprg3 %r5; \
178 std %r3, FRAME_XER+48(1); /* save xer/ctr/exc */ \
179 std %r4, FRAME_CTR+48(1); \
180 std %r5, FRAME_EXC+48(1); \
181 std %r28,FRAME_AIM_DAR+48(1); \
182 std %r29,FRAME_AIM_DSISR+48(1); /* save dsisr/srr0/srr1 */ \
183 std %r30,FRAME_SRR0+48(1); \
184 std %r31,FRAME_SRR1+48(1)
185
186#define FRAME_LEAVE(savearea) \
187/* Now restore regs: */ \
188 ld %r2,FRAME_SRR0+48(%r1); \
189 ld %r3,FRAME_SRR1+48(%r1); \
190 ld %r4,FRAME_CTR+48(%r1); \
191 ld %r5,FRAME_XER+48(%r1); \
192 ld %r6,FRAME_LR+48(%r1); \
193 GET_CPUINFO(%r7); \
194 std %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \
195 std %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \
196 ld %r7,FRAME_CR+48(%r1); \
197 mtctr %r4; \
198 mtxer %r5; \
199 mtlr %r6; \
200 mtsprg1 %r7; /* save cr */ \
201 ld %r31,FRAME_31+48(%r1); /* restore r0-31 */ \
202 ld %r30,FRAME_30+48(%r1); \
203 ld %r29,FRAME_29+48(%r1); \
204 ld %r28,FRAME_28+48(%r1); \
205 ld %r27,FRAME_27+48(%r1); \
206 ld %r26,FRAME_26+48(%r1); \
207 ld %r25,FRAME_25+48(%r1); \
208 ld %r24,FRAME_24+48(%r1); \
209 ld %r23,FRAME_23+48(%r1); \
210 ld %r22,FRAME_22+48(%r1); \
211 ld %r21,FRAME_21+48(%r1); \
212 ld %r20,FRAME_20+48(%r1); \
213 ld %r19,FRAME_19+48(%r1); \
214 ld %r18,FRAME_18+48(%r1); \
215 ld %r17,FRAME_17+48(%r1); \
216 ld %r16,FRAME_16+48(%r1); \
217 ld %r15,FRAME_15+48(%r1); \
218 ld %r14,FRAME_14+48(%r1); \
219 ld %r13,FRAME_13+48(%r1); \
220 ld %r12,FRAME_12+48(%r1); \
221 ld %r11,FRAME_11+48(%r1); \
222 ld %r10,FRAME_10+48(%r1); \
223 ld %r9, FRAME_9+48(%r1); \
224 ld %r8, FRAME_8+48(%r1); \
225 ld %r7, FRAME_7+48(%r1); \
226 ld %r6, FRAME_6+48(%r1); \
227 ld %r5, FRAME_5+48(%r1); \
228 ld %r4, FRAME_4+48(%r1); \
229 ld %r3, FRAME_3+48(%r1); \
230 ld %r2, FRAME_2+48(%r1); \
231 ld %r0, FRAME_0+48(%r1); \
232 ld %r1, FRAME_1+48(%r1); \
233/* Can't touch %r1 from here on */ \
234 mtsprg2 %r2; /* save r2 & r3 */ \
235 mtsprg3 %r3; \
236/* Disable translation, machine check and recoverability: */ \
237 mfmsr %r2; \
238 andi. %r2,%r2,~(PSL_DR|PSL_IR|PSL_EE|PSL_ME|PSL_RI)@l; \
239 mtmsr %r2; \
240 isync; \
241/* Decide whether we return to user mode: */ \
242 GET_CPUINFO(%r2); \
243 ld %r3,(savearea+CPUSAVE_SRR1)(%r2); \
244 mtcr %r3; \
245 bf 17,1f; /* branch if PSL_PR is false */ \
246/* Restore user SRs */ \
247 GET_CPUINFO(%r3); \
248 std %r27,(savearea+CPUSAVE_R27)(%r3); \
249 std %r28,(savearea+CPUSAVE_R28)(%r3); \
250 std %r29,(savearea+CPUSAVE_R29)(%r3); \
251 std %r30,(savearea+CPUSAVE_R30)(%r3); \
252 std %r31,(savearea+CPUSAVE_R31)(%r3); \
253 mflr %r27; /* preserve LR */ \
254 bl restore_usersrs; /* uses r28-r31 */ \
255 mtlr %r27; \
256 ld %r31,(savearea+CPUSAVE_R31)(%r3); \
257 ld %r30,(savearea+CPUSAVE_R30)(%r3); \
258 ld %r29,(savearea+CPUSAVE_R29)(%r3); \
259 ld %r28,(savearea+CPUSAVE_R28)(%r3); \
260 ld %r27,(savearea+CPUSAVE_R27)(%r3); \
2611: mfsprg1 %r2; /* restore cr */ \
262 mtcr %r2; \
263 GET_CPUINFO(%r2); \
264 ld %r3,(savearea+CPUSAVE_SRR0)(%r2); /* restore srr0 */ \
265 mtsrr0 %r3; \
266 ld %r3,(savearea+CPUSAVE_SRR1)(%r2); /* restore srr1 */ \
267 mtsrr1 %r3; \
268 mfsprg2 %r2; /* restore r2 & r3 */ \
269 mfsprg3 %r3
270
271#ifdef SMP
272/*
273 * Processor reset exception handler. These are typically
274 * the first instructions the processor executes after a
275 * software reset. We do this in two bits so that we are
276 * not still hanging around in the trap handling region
277 * once the MMU is turned on.
278 */
279 .globl CNAME(rstcode), CNAME(rstsize)
280CNAME(rstcode):
281 /* Explicitly set MSR[SF] */
282 mfmsr %r9
283 li %r8,1
284 insrdi %r9,%r8,1,0
285 mtmsrd %r9
286 isync
287
288 ba cpu_reset
289CNAME(rstsize) = . - CNAME(rstcode)
290
291cpu_reset:
292 lis %r1,(tmpstk+TMPSTKSZ-48)@ha /* get new SP */
293 addi %r1,%r1,(tmpstk+TMPSTKSZ-48)@l
294
295 lis %r3,tocbase@ha
296 ld %r2,tocbase@l(%r3)
297 lis %r3,1@l
|
306 nop
307
308 /* Should not be reached */
3099:
310 b 9b
311#endif
312
313/*
314 * This code gets copied to all the trap vectors
315 * (except ISI/DSI, ALI, and the interrupts)
316 */
317
318 .globl CNAME(trapcode),CNAME(trapsize)
319CNAME(trapcode):
320 mtsprg1 %r1 /* save SP */
321 mflr %r1 /* Save the old LR in r1 */
322 mtsprg2 %r1 /* And then in SPRG2 */
323 li %r1, 0xA0 /* How to get the vector from LR */
324 bla generictrap /* LR & SPRG3 is exception # */
325CNAME(trapsize) = .-CNAME(trapcode)
326
327/*
328 * For ALI: has to save DSISR and DAR
329 */
330 .globl CNAME(alitrap),CNAME(alisize)
331CNAME(alitrap):
332 mtsprg1 %r1 /* save SP */
333 GET_CPUINFO(%r1)
334 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */
335 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
336 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
337 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
338 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
339 mfdar %r30
340 mfdsisr %r31
341 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
342 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
343 mfsprg1 %r1 /* restore SP, in case of branch */
344 mflr %r28 /* save LR */
345 mfcr %r29 /* save CR */
346
347 /* Put our exception vector in SPRG3 */
348 li %r31, EXC_ALI
349 mtsprg3 %r31
350
351 /* Test whether we already had PR set */
352 mfsrr1 %r31
353 mtcr %r31
354 bla s_trap
355CNAME(alisize) = .-CNAME(alitrap)
356
357/*
358 * Similar to the above for DSI
359 * Has to handle BAT spills
360 * and standard pagetable spills
361 */
362 .globl CNAME(dsitrap),CNAME(dsisize)
363CNAME(dsitrap):
364 mtsprg1 %r1 /* save SP */
365 GET_CPUINFO(%r1)
366 std %r27,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */
367 std %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1)
368 std %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1)
369 std %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
370 std %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
371 mfsprg1 %r1 /* restore SP */
372 mfcr %r29 /* save CR */
373 mfxer %r30 /* save XER */
374 mtsprg2 %r30 /* in SPRG2 */
375 mfsrr1 %r31 /* test kernel mode */
376 mtcr %r31
377 mflr %r28 /* save LR (SP already saved) */
378 bla disitrap
379CNAME(dsisize) = .-CNAME(dsitrap)
380
381/*
382 * Preamble code for DSI/ISI traps
383 */
384disitrap:
385 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */
386 mflr %r1
387 andi. %r1,%r1,0xff00
388 mtsprg3 %r1
389
390 GET_CPUINFO(%r1)
391 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1)
392 std %r31,(PC_TEMPSAVE+CPUSAVE_R27)(%r1)
393 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1)
394 std %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
395 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1)
396 std %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
397 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
398 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
399 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
400 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
401 mfdar %r30
402 mfdsisr %r31
403 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
404 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
405
406#ifdef KDB
407 /* Try and detect a kernel stack overflow */
408 mfsrr1 %r31
409 mtcr %r31
410 bt 17,realtrap /* branch is user mode */
411 mfsprg1 %r31 /* get old SP */
412 sub. %r30,%r31,%r30 /* SP - DAR */
413 bge 1f
414 neg %r30,%r30 /* modulo value */
4151: cmpldi %cr0,%r30,4096 /* is DAR within a page of SP? */
416 bge %cr0,realtrap /* no, too far away. */
417
418 /* Now convert this DSI into a DDB trap. */
419 GET_CPUINFO(%r1)
420 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */
421 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */
422 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */
423 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */
424 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* get r27 */
425 std %r31,(PC_DBSAVE +CPUSAVE_R27)(%r1) /* save r27 */
426 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */
427 std %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */
428 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */
429 std %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */
430 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */
431 std %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */
432 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */
433 std %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */
434 b dbtrap
435#endif
436
437 /* XXX need stack probe here */
438realtrap:
439/* Test whether we already had PR set */
440 mfsrr1 %r1
441 mtcr %r1
442 mfsprg1 %r1 /* restore SP (might have been
443 overwritten) */
444 bf 17,k_trap /* branch if PSL_PR is false */
445 GET_CPUINFO(%r1)
446 ld %r1,PC_CURPCB(%r1)
447 mr %r27,%r28 /* Save LR, r29 */
448 mtsprg2 %r29
449 bl restore_kernsrs /* enable kernel mapping */
450 mfsprg2 %r29
451 mr %r28,%r27
452 ba s_trap
453
454/*
455 * generictrap does some standard setup for trap handling to minimize
456 * the code that need be installed in the actual vectors. It expects
457 * the following conditions.
458 *
459 * R1 - Trap vector = LR & (0xff00 | R1)
460 * SPRG1 - Original R1 contents
461 * SPRG2 - Original LR
462 */
463
464generictrap:
465 /* Save R1 for computing the exception vector */
466 mtsprg3 %r1
467
468 /* Save interesting registers */
469 GET_CPUINFO(%r1)
470 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */
471 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
472 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
473 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
474 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
475 mfdar %r30
476 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
477 mfsprg1 %r1 /* restore SP, in case of branch */
478 mfsprg2 %r28 /* save LR */
479 mfcr %r29 /* save CR */
480
481 /* Compute the exception vector from the link register */
482 mfsprg3 %r31
483 ori %r31,%r31,0xff00
484 mflr %r30
485 and %r30,%r30,%r31
486 mtsprg3 %r30
487
488 /* Test whether we already had PR set */
489 mfsrr1 %r31
490 mtcr %r31
491
492s_trap:
493 bf 17,k_trap /* branch if PSL_PR is false */
494 GET_CPUINFO(%r1)
495u_trap:
496 ld %r1,PC_CURPCB(%r1)
497 mr %r27,%r28 /* Save LR, r29 */
498 mtsprg2 %r29
499 bl restore_kernsrs /* enable kernel mapping */
500 mfsprg2 %r29
501 mr %r28,%r27
502
503/*
504 * Now the common trap catching code.
505 */
506k_trap:
507 FRAME_SETUP(PC_TEMPSAVE)
508/* Call C interrupt dispatcher: */
509trapagain:
510 lis %r3,tocbase@ha
511 ld %r2,tocbase@l(%r3)
512 addi %r3,%r1,48
| 306 nop
307
308 /* Should not be reached */
3099:
310 b 9b
311#endif
312
313/*
314 * This code gets copied to all the trap vectors
315 * (except ISI/DSI, ALI, and the interrupts)
316 */
317
318 .globl CNAME(trapcode),CNAME(trapsize)
319CNAME(trapcode):
320 mtsprg1 %r1 /* save SP */
321 mflr %r1 /* Save the old LR in r1 */
322 mtsprg2 %r1 /* And then in SPRG2 */
323 li %r1, 0xA0 /* How to get the vector from LR */
324 bla generictrap /* LR & SPRG3 is exception # */
325CNAME(trapsize) = .-CNAME(trapcode)
326
327/*
328 * For ALI: has to save DSISR and DAR
329 */
330 .globl CNAME(alitrap),CNAME(alisize)
331CNAME(alitrap):
332 mtsprg1 %r1 /* save SP */
333 GET_CPUINFO(%r1)
334 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */
335 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
336 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
337 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
338 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
339 mfdar %r30
340 mfdsisr %r31
341 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
342 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
343 mfsprg1 %r1 /* restore SP, in case of branch */
344 mflr %r28 /* save LR */
345 mfcr %r29 /* save CR */
346
347 /* Put our exception vector in SPRG3 */
348 li %r31, EXC_ALI
349 mtsprg3 %r31
350
351 /* Test whether we already had PR set */
352 mfsrr1 %r31
353 mtcr %r31
354 bla s_trap
355CNAME(alisize) = .-CNAME(alitrap)
356
357/*
358 * Similar to the above for DSI
359 * Has to handle BAT spills
360 * and standard pagetable spills
361 */
362 .globl CNAME(dsitrap),CNAME(dsisize)
363CNAME(dsitrap):
364 mtsprg1 %r1 /* save SP */
365 GET_CPUINFO(%r1)
366 std %r27,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */
367 std %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1)
368 std %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1)
369 std %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
370 std %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
371 mfsprg1 %r1 /* restore SP */
372 mfcr %r29 /* save CR */
373 mfxer %r30 /* save XER */
374 mtsprg2 %r30 /* in SPRG2 */
375 mfsrr1 %r31 /* test kernel mode */
376 mtcr %r31
377 mflr %r28 /* save LR (SP already saved) */
378 bla disitrap
379CNAME(dsisize) = .-CNAME(dsitrap)
380
381/*
382 * Preamble code for DSI/ISI traps
383 */
384disitrap:
385 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */
386 mflr %r1
387 andi. %r1,%r1,0xff00
388 mtsprg3 %r1
389
390 GET_CPUINFO(%r1)
391 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1)
392 std %r31,(PC_TEMPSAVE+CPUSAVE_R27)(%r1)
393 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1)
394 std %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
395 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1)
396 std %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
397 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
398 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
399 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
400 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
401 mfdar %r30
402 mfdsisr %r31
403 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
404 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
405
406#ifdef KDB
407 /* Try and detect a kernel stack overflow */
408 mfsrr1 %r31
409 mtcr %r31
410 bt 17,realtrap /* branch is user mode */
411 mfsprg1 %r31 /* get old SP */
412 sub. %r30,%r31,%r30 /* SP - DAR */
413 bge 1f
414 neg %r30,%r30 /* modulo value */
4151: cmpldi %cr0,%r30,4096 /* is DAR within a page of SP? */
416 bge %cr0,realtrap /* no, too far away. */
417
418 /* Now convert this DSI into a DDB trap. */
419 GET_CPUINFO(%r1)
420 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */
421 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */
422 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */
423 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */
424 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* get r27 */
425 std %r31,(PC_DBSAVE +CPUSAVE_R27)(%r1) /* save r27 */
426 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */
427 std %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */
428 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */
429 std %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */
430 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */
431 std %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */
432 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */
433 std %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */
434 b dbtrap
435#endif
436
437 /* XXX need stack probe here */
438realtrap:
439/* Test whether we already had PR set */
440 mfsrr1 %r1
441 mtcr %r1
442 mfsprg1 %r1 /* restore SP (might have been
443 overwritten) */
444 bf 17,k_trap /* branch if PSL_PR is false */
445 GET_CPUINFO(%r1)
446 ld %r1,PC_CURPCB(%r1)
447 mr %r27,%r28 /* Save LR, r29 */
448 mtsprg2 %r29
449 bl restore_kernsrs /* enable kernel mapping */
450 mfsprg2 %r29
451 mr %r28,%r27
452 ba s_trap
453
454/*
455 * generictrap does some standard setup for trap handling to minimize
456 * the code that need be installed in the actual vectors. It expects
457 * the following conditions.
458 *
459 * R1 - Trap vector = LR & (0xff00 | R1)
460 * SPRG1 - Original R1 contents
461 * SPRG2 - Original LR
462 */
463
464generictrap:
465 /* Save R1 for computing the exception vector */
466 mtsprg3 %r1
467
468 /* Save interesting registers */
469 GET_CPUINFO(%r1)
470 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */
471 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
472 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
473 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
474 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
475 mfdar %r30
476 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
477 mfsprg1 %r1 /* restore SP, in case of branch */
478 mfsprg2 %r28 /* save LR */
479 mfcr %r29 /* save CR */
480
481 /* Compute the exception vector from the link register */
482 mfsprg3 %r31
483 ori %r31,%r31,0xff00
484 mflr %r30
485 and %r30,%r30,%r31
486 mtsprg3 %r30
487
488 /* Test whether we already had PR set */
489 mfsrr1 %r31
490 mtcr %r31
491
492s_trap:
493 bf 17,k_trap /* branch if PSL_PR is false */
494 GET_CPUINFO(%r1)
495u_trap:
496 ld %r1,PC_CURPCB(%r1)
497 mr %r27,%r28 /* Save LR, r29 */
498 mtsprg2 %r29
499 bl restore_kernsrs /* enable kernel mapping */
500 mfsprg2 %r29
501 mr %r28,%r27
502
503/*
504 * Now the common trap catching code.
505 */
506k_trap:
507 FRAME_SETUP(PC_TEMPSAVE)
508/* Call C interrupt dispatcher: */
509trapagain:
510 lis %r3,tocbase@ha
511 ld %r2,tocbase@l(%r3)
512 addi %r3,%r1,48
|