| machdep.c (222616) | machdep.c (222620) |
|---|---|
| 1/*- 2 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 3 * Copyright (C) 1995, 1996 TooLs GmbH. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 41 unchanged lines hidden (view full) --- 50 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 51 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 52 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 53 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $ 55 */ 56 57#include <sys/cdefs.h> | 1/*- 2 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 3 * Copyright (C) 1995, 1996 TooLs GmbH. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 41 unchanged lines hidden (view full) --- 50 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 51 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 52 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 53 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $ 55 */ 56 57#include <sys/cdefs.h> |
| 58__FBSDID("$FreeBSD: head/sys/powerpc/aim/machdep.c 222616 2011-06-02 14:21:20Z nwhitehorn $"); | 58__FBSDID("$FreeBSD: head/sys/powerpc/aim/machdep.c 222620 2011-06-02 14:25:52Z nwhitehorn $"); |
| 59 60#include "opt_compat.h" 61#include "opt_ddb.h" 62#include "opt_kstack_pages.h" 63 64#include <sys/param.h> 65#include <sys/proc.h> 66#include <sys/systm.h> --- 60 unchanged lines hidden (view full) --- 127#include <dev/ofw/openfirm.h> 128 129#ifdef DDB 130extern vm_offset_t ksym_start, ksym_end; 131#endif 132 133int cold = 1; 134#ifdef __powerpc64__ | 59 60#include "opt_compat.h" 61#include "opt_ddb.h" 62#include "opt_kstack_pages.h" 63 64#include <sys/param.h> 65#include <sys/proc.h> 66#include <sys/systm.h> --- 60 unchanged lines hidden (view full) --- 127#include <dev/ofw/openfirm.h> 128 129#ifdef DDB 130extern vm_offset_t ksym_start, ksym_end; 131#endif 132 133int cold = 1; 134#ifdef __powerpc64__ |
| 135extern int n_slbs; |
|
| 135int cacheline_size = 128; 136#else 137int cacheline_size = 32; 138#endif 139int hw_direct_map = 1; 140 141struct pcpu __pcpu[MAXCPU]; 142 --- 189 unchanged lines hidden (view full) --- 332 } 333 334 /* 335 * Init KDB 336 */ 337 338 kdb_init(); 339 | 136int cacheline_size = 128; 137#else 138int cacheline_size = 32; 139#endif 140int hw_direct_map = 1; 141 142struct pcpu __pcpu[MAXCPU]; 143 --- 189 unchanged lines hidden (view full) --- 333 } 334 335 /* 336 * Init KDB 337 */ 338 339 kdb_init(); 340 |
| 340 /* 341 * PowerPC 970 CPUs have a misfeature requested by Apple that makes 342 * them pretend they have a 32-byte cacheline. Turn this off 343 * before we measure the cacheline size. 344 */ 345 | 341 /* Various very early CPU fix ups */ |
| 346 switch (mfpvr() >> 16) { | 342 switch (mfpvr() >> 16) { |
| 343 /* 344 * PowerPC 970 CPUs have a misfeature requested by Apple that 345 * makes them pretend they have a 32-byte cacheline. Turn this 346 * off before we measure the cacheline size. 347 */ |
|
| 347 case IBM970: 348 case IBM970FX: 349 case IBM970MP: 350 case IBM970GX: 351 scratch = mfspr(SPR_HID5); 352 scratch &= ~HID5_970_DCBZ_SIZE_HI; 353 mtspr(SPR_HID5, scratch); 354 break; | 348 case IBM970: 349 case IBM970FX: 350 case IBM970MP: 351 case IBM970GX: 352 scratch = mfspr(SPR_HID5); 353 scratch &= ~HID5_970_DCBZ_SIZE_HI; 354 mtspr(SPR_HID5, scratch); 355 break; |
| 356 #ifdef __powerpc64__ 357 case IBMPOWER7: 358 /* XXX: get from ibm,slb-size in device tree */ 359 n_slbs = 32; 360 break; 361 #endif |
|
| 355 } 356 357 /* 358 * Initialize the interrupt tables and figure out our cache line 359 * size and whether or not we need the 64-bit bridge code. 360 */ 361 362 /* 363 * Disable translation in case the vector area hasn't been 364 * mapped (G5). Note that no OFW calls can be made until 365 * translation is re-enabled. 366 */ 367 368 msr = mfmsr(); 369 mtmsr((msr & ~(PSL_IR | PSL_DR)) | PSL_RI); | 362 } 363 364 /* 365 * Initialize the interrupt tables and figure out our cache line 366 * size and whether or not we need the 64-bit bridge code. 367 */ 368 369 /* 370 * Disable translation in case the vector area hasn't been 371 * mapped (G5). Note that no OFW calls can be made until 372 * translation is re-enabled. 373 */ 374 375 msr = mfmsr(); 376 mtmsr((msr & ~(PSL_IR | PSL_DR)) | PSL_RI); |
| 370 isync(); | |
| 371 372 /* 373 * Measure the cacheline size using dcbz 374 * 375 * Use EXC_PGM as a playground. We are about to overwrite it 376 * anyway, we know it exists, and we know it is cache-aligned. 377 */ 378 --- 118 unchanged lines hidden (view full) --- 497 bcopy(&dsmisstrap, (void *)EXC_DSMISS, (size_t)&dsmisssize); 498 #endif 499 __syncicache(EXC_RSVD, EXC_LAST - EXC_RSVD); 500 501 /* 502 * Restore MSR 503 */ 504 mtmsr(msr); | 377 378 /* 379 * Measure the cacheline size using dcbz 380 * 381 * Use EXC_PGM as a playground. We are about to overwrite it 382 * anyway, we know it exists, and we know it is cache-aligned. 383 */ 384 --- 118 unchanged lines hidden (view full) --- 503 bcopy(&dsmisstrap, (void *)EXC_DSMISS, (size_t)&dsmisssize); 504 #endif 505 __syncicache(EXC_RSVD, EXC_LAST - EXC_RSVD); 506 507 /* 508 * Restore MSR 509 */ 510 mtmsr(msr); |
| 505 isync(); | |
| 506 507 /* Warn if cachline size was not determined */ 508 if (cacheline_warn == 1) { 509 printf("WARNING: cacheline size undetermined, setting to 32\n"); 510 } 511 512 /* 513 * Choose a platform module so we can get the physical memory map. --- 8 unchanged lines hidden (view full) --- 522 */ 523 if (cpu_features & PPC_FEATURE_64) 524 pmap_mmu_install(MMU_TYPE_G5, BUS_PROBE_GENERIC); 525 else 526 pmap_mmu_install(MMU_TYPE_OEA, BUS_PROBE_GENERIC); 527 528 pmap_bootstrap(startkernel, endkernel); 529 mtmsr(PSL_KERNSET & ~PSL_EE); | 511 512 /* Warn if cachline size was not determined */ 513 if (cacheline_warn == 1) { 514 printf("WARNING: cacheline size undetermined, setting to 32\n"); 515 } 516 517 /* 518 * Choose a platform module so we can get the physical memory map. --- 8 unchanged lines hidden (view full) --- 527 */ 528 if (cpu_features & PPC_FEATURE_64) 529 pmap_mmu_install(MMU_TYPE_G5, BUS_PROBE_GENERIC); 530 else 531 pmap_mmu_install(MMU_TYPE_OEA, BUS_PROBE_GENERIC); 532 533 pmap_bootstrap(startkernel, endkernel); 534 mtmsr(PSL_KERNSET & ~PSL_EE); |
| 530 isync(); | |
| 531 532 /* 533 * Initialize params/tunables that are derived from memsize 534 */ 535 init_param2(physmem); 536 537 /* 538 * Grab booted kernel's name --- 248 unchanged lines hidden --- | 535 536 /* 537 * Initialize params/tunables that are derived from memsize 538 */ 539 init_param2(physmem); 540 541 /* 542 * Grab booted kernel's name --- 248 unchanged lines hidden --- |