| intpmreg.h (162289) | intpmreg.h (165951) |
|---|---|
| 1/*- 2 * Copyright (c) 1998, 1999 Takanori Watanabe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 1998, 1999 Takanori Watanabe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/pci/intpmreg.h 162289 2006-09-13 18:56:39Z jhb $ | 26 * $FreeBSD: head/sys/pci/intpmreg.h 165951 2007-01-11 19:56:24Z jhb $ |
| 27 */ 28 29#ifndef __INTPMREG_H__ 30#define __INTPMREG_H__ 31 32/* Register definitions for non-ICH Intel Chipset SMBUS controllers. */ 33 34/* PCI Config Registers. */ 35#define PCI_BASE_ADDR_SMB 0x90 /* IO BAR. */ 36#define PCI_BASE_ADDR_PM 0x40 | 27 */ 28 29#ifndef __INTPMREG_H__ 30#define __INTPMREG_H__ 31 32/* Register definitions for non-ICH Intel Chipset SMBUS controllers. */ 33 34/* PCI Config Registers. */ 35#define PCI_BASE_ADDR_SMB 0x90 /* IO BAR. */ 36#define PCI_BASE_ADDR_PM 0x40 |
| 37#define PCI_HST_CFG_SMB 0xd2 /*Host Configuration*/ | 37#define PCI_HST_CFG_SMB 0xd2 /* Host Configuration */ |
| 38#define PCI_INTR_SMB_SMI 0 39#define PCI_INTR_SMB_IRQ9 8 40#define PCI_INTR_SMB_ENABLE 1 41#define PCI_SLV_CMD_SMB 0xd3 /*SLAVE COMMAND*/ 42#define PCI_SLV_SDW_SMB_1 0xd4 /*SLAVE SHADOW PORT 1*/ 43#define PCI_SLV_SDW_SMB_2 0xd5 /*SLAVE SHADOW PORT 2*/ 44#define PCI_REVID_SMB 0xd6 45 --- 43 unchanged lines hidden --- | 38#define PCI_INTR_SMB_SMI 0 39#define PCI_INTR_SMB_IRQ9 8 40#define PCI_INTR_SMB_ENABLE 1 41#define PCI_SLV_CMD_SMB 0xd3 /*SLAVE COMMAND*/ 42#define PCI_SLV_SDW_SMB_1 0xd4 /*SLAVE SHADOW PORT 1*/ 43#define PCI_SLV_SDW_SMB_2 0xd5 /*SLAVE SHADOW PORT 2*/ 44#define PCI_REVID_SMB 0xd6 45 --- 43 unchanged lines hidden --- |