| if_rlreg.h (67931) | if_rlreg.h (72200) |
|---|---|
| 1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/pci/if_rlreg.h 67931 2000-10-30 07:54:38Z wpaul $ | 32 * $FreeBSD: head/sys/pci/if_rlreg.h 72200 2001-02-09 06:11:45Z bmilekic $ |
| 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 327 unchanged lines hidden (view full) --- 368 int rl_eecmd_read; 369 u_int8_t rl_stats_no_timeout; 370 int rl_txthresh; 371 struct rl_chain_data rl_cdata; 372 struct callout_handle rl_stat_ch; 373 struct mtx rl_mtx; 374}; 375 | 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 327 unchanged lines hidden (view full) --- 368 int rl_eecmd_read; 369 u_int8_t rl_stats_no_timeout; 370 int rl_txthresh; 371 struct rl_chain_data rl_cdata; 372 struct callout_handle rl_stat_ch; 373 struct mtx rl_mtx; 374}; 375 |
| 376#define RL_LOCK(_sc) mtx_enter(&(_sc)->rl_mtx, MTX_DEF) 377#define RL_UNLOCK(_sc) mtx_exit(&(_sc)->rl_mtx, MTX_DEF) | 376#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 377#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) |
| 378 379/* 380 * register space access macros 381 */ 382#define CSR_WRITE_4(sc, reg, val) \ 383 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 384#define CSR_WRITE_2(sc, reg, val) \ 385 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) --- 95 unchanged lines hidden --- | 378 379/* 380 * register space access macros 381 */ 382#define CSR_WRITE_4(sc, reg, val) \ 383 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 384#define CSR_WRITE_2(sc, reg, val) \ 385 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) --- 95 unchanged lines hidden --- |