if_rlreg.h (48028) | if_rlreg.h (48056) |
---|---|
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
32 * $Id: if_rlreg.h,v 1.19 1999/06/19 20:01:32 wpaul Exp wpaul $ | 32 * $Id: if_rlreg.h,v 1.8 1999/06/19 20:17:38 wpaul Exp $ |
33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 253 unchanged lines hidden (view full) --- 294 * For reception, there's just one large buffer where the chip stores 295 * all received packets. 296 */ 297 298#define RL_RX_BUF_SZ RL_RXBUF_64 299#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 300#define RL_TX_LIST_CNT 4 301#define RL_MIN_FRAMELEN 60 | 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 253 unchanged lines hidden (view full) --- 294 * For reception, there's just one large buffer where the chip stores 295 * all received packets. 296 */ 297 298#define RL_RX_BUF_SZ RL_RXBUF_64 299#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 300#define RL_TX_LIST_CNT 4 301#define RL_MIN_FRAMELEN 60 |
302#define RL_TX_EARLYTHRESH 0x00300000 /* 1536 << 11 */ 303#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 304#define RL_RX_MAXDMA RL_RXDMA_64BYTES 305#define RL_TX_MAXDMA RL_TXDMA_64BYTES | 302#define RL_TX_EARLYTHRESH (256 << 11) 303#define RL_RX_FIFOTHRESH RL_RXFIFO_256BYTES 304#define RL_RX_MAXDMA RL_RXDMA_256BYTES 305#define RL_TX_MAXDMA RL_TXDMA_256BYTES |
306 307#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 308#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 309 310#define RL_ETHER_ALIGN 2 311 312struct rl_chain_data { 313 u_int16_t cur_rx; --- 305 unchanged lines hidden --- | 306 307#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 308#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 309 310#define RL_ETHER_ALIGN 2 311 312struct rl_chain_data { 313 u_int16_t cur_rx; --- 305 unchanged lines hidden --- |