| if_rlreg.h (47632) | if_rlreg.h (48028) |
|---|---|
| 1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $Id: if_rlreg.h,v 1.18 1999/05/30 18:48:01 wpaul Exp $ | 32 * $Id: if_rlreg.h,v 1.19 1999/06/19 20:01:32 wpaul Exp wpaul $ |
| 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 261 unchanged lines hidden (view full) --- 302#define RL_TX_EARLYTHRESH 0x00300000 /* 1536 << 11 */ 303#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 304#define RL_RX_MAXDMA RL_RXDMA_64BYTES 305#define RL_TX_MAXDMA RL_TXDMA_64BYTES 306 307#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 308#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 309 | 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 261 unchanged lines hidden (view full) --- 302#define RL_TX_EARLYTHRESH 0x00300000 /* 1536 << 11 */ 303#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 304#define RL_RX_MAXDMA RL_RXDMA_64BYTES 305#define RL_TX_MAXDMA RL_TXDMA_64BYTES 306 307#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 308#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 309 |
| 310#define RL_ETHER_ALIGN 2 311 |
|
| 310struct rl_chain_data { 311 u_int16_t cur_rx; 312 caddr_t rl_rx_buf; | 312struct rl_chain_data { 313 u_int16_t cur_rx; 314 caddr_t rl_rx_buf; |
| 315 caddr_t rl_rx_buf_ptr; |
|
| 313 314 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 315 u_int8_t last_tx; 316 u_int8_t cur_tx; 317}; 318 319#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 320#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) --- 282 unchanged lines hidden (view full) --- 603#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ 604#define PHY_BMSR_MFPRESUP 0x0040 605#define PHY_BMSR_AUTONEGCOMP 0x0020 606#define PHY_BMSR_REMFAULT 0x0010 607#define PHY_BMSR_CANAUTONEG 0x0008 608#define PHY_BMSR_LINKSTAT 0x0004 609#define PHY_BMSR_JABBER 0x0002 610#define PHY_BMSR_EXTENDED 0x0001 | 316 317 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 318 u_int8_t last_tx; 319 u_int8_t cur_tx; 320}; 321 322#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 323#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) --- 282 unchanged lines hidden (view full) --- 606#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ 607#define PHY_BMSR_MFPRESUP 0x0040 608#define PHY_BMSR_AUTONEGCOMP 0x0020 609#define PHY_BMSR_REMFAULT 0x0010 610#define PHY_BMSR_CANAUTONEG 0x0008 611#define PHY_BMSR_LINKSTAT 0x0004 612#define PHY_BMSR_JABBER 0x0002 613#define PHY_BMSR_EXTENDED 0x0001 |
| 614#ifdef __alpha__ 615#undef vtophys 616#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 617#endif 618 |
|