| if_rlreg.h (257617) | if_rlreg.h (262389) |
|---|---|
| 1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: stable/10/sys/pci/if_rlreg.h 257617 2013-11-04 05:58:59Z yongari $ | 32 * $FreeBSD: stable/10/sys/pci/if_rlreg.h 262389 2014-02-23 21:03:30Z marius $ |
| 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 117 unchanged lines hidden (view full) --- 158#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 159#define RL_TXCFG_HWREV 0x7CC00000 160 161#define RL_LOOPTEST_OFF 0x00000000 162#define RL_LOOPTEST_ON 0x00020000 163#define RL_LOOPTEST_ON_CPLUS 0x00060000 164 165/* Known revision codes. */ | 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 117 unchanged lines hidden (view full) --- 158#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 159#define RL_TXCFG_HWREV 0x7CC00000 160 161#define RL_LOOPTEST_OFF 0x00000000 162#define RL_LOOPTEST_ON 0x00020000 163#define RL_LOOPTEST_ON_CPLUS 0x00060000 164 165/* Known revision codes. */ |
| 166 | |
| 167#define RL_HWREV_8169 0x00000000 168#define RL_HWREV_8169S 0x00800000 169#define RL_HWREV_8110S 0x04000000 170#define RL_HWREV_8169_8110SB 0x10000000 171#define RL_HWREV_8169_8110SC 0x18000000 172#define RL_HWREV_8401E 0x24000000 173#define RL_HWREV_8102EL 0x24800000 174#define RL_HWREV_8102EL_SPIN1 0x24C00000 --- 149 unchanged lines hidden (view full) --- 324#define RL_RXSTAT_CRCERR 0x00000004 325#define RL_RXSTAT_GIANT 0x00000008 326#define RL_RXSTAT_RUNT 0x00000010 327#define RL_RXSTAT_BADSYM 0x00000020 328#define RL_RXSTAT_BROAD 0x00002000 329#define RL_RXSTAT_INDIV 0x00004000 330#define RL_RXSTAT_MULTI 0x00008000 331#define RL_RXSTAT_LENMASK 0xFFFF0000 | 166#define RL_HWREV_8169 0x00000000 167#define RL_HWREV_8169S 0x00800000 168#define RL_HWREV_8110S 0x04000000 169#define RL_HWREV_8169_8110SB 0x10000000 170#define RL_HWREV_8169_8110SC 0x18000000 171#define RL_HWREV_8401E 0x24000000 172#define RL_HWREV_8102EL 0x24800000 173#define RL_HWREV_8102EL_SPIN1 0x24C00000 --- 149 unchanged lines hidden (view full) --- 323#define RL_RXSTAT_CRCERR 0x00000004 324#define RL_RXSTAT_GIANT 0x00000008 325#define RL_RXSTAT_RUNT 0x00000010 326#define RL_RXSTAT_BADSYM 0x00000020 327#define RL_RXSTAT_BROAD 0x00002000 328#define RL_RXSTAT_INDIV 0x00004000 329#define RL_RXSTAT_MULTI 0x00008000 330#define RL_RXSTAT_LENMASK 0xFFFF0000 |
| 331#define RL_RXSTAT_UNFINISHED 0x0000FFF0 /* DMA still in progress */ |
|
| 332 | 332 |
| 333#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ | |
| 334/* 335 * Command register. 336 */ 337#define RL_CMD_EMPTY_RXBUF 0x0001 338#define RL_CMD_TX_ENB 0x0004 339#define RL_CMD_RX_ENB 0x0008 340#define RL_CMD_RESET 0x0010 341#define RL_CMD_STOPREQ 0x0080 --- 14 unchanged lines hidden (view full) --- 356#define RL_NWAYTST_RESET 0 357#define RL_NWAYTST_CBL_TEST 0x20 358 359#define RL_PARA78 0x78 360#define RL_PARA78_DEF 0x78fa8388 361#define RL_PARA7C 0x7C 362#define RL_PARA7C_DEF 0xcb38de43 363#define RL_PARA7C_RETUNE 0xfb38de03 | 333/* 334 * Command register. 335 */ 336#define RL_CMD_EMPTY_RXBUF 0x0001 337#define RL_CMD_TX_ENB 0x0004 338#define RL_CMD_RX_ENB 0x0008 339#define RL_CMD_RESET 0x0010 340#define RL_CMD_STOPREQ 0x0080 --- 14 unchanged lines hidden (view full) --- 355#define RL_NWAYTST_RESET 0 356#define RL_NWAYTST_CBL_TEST 0x20 357 358#define RL_PARA78 0x78 359#define RL_PARA78_DEF 0x78fa8388 360#define RL_PARA7C 0x7C 361#define RL_PARA7C_DEF 0xcb38de43 362#define RL_PARA7C_RETUNE 0xfb38de03 |
| 363 |
|
| 364/* 365 * EEPROM control register 366 */ 367#define RL_EE_DATAOUT 0x01 /* Data out */ 368#define RL_EE_DATAIN 0x02 /* Data in */ 369#define RL_EE_CLK 0x04 /* clock */ 370#define RL_EE_SEL 0x08 /* chip select */ 371#define RL_EE_MODE (0x40|0x80) --- 96 unchanged lines hidden (view full) --- 468#define RL_CFG5_WOL_LANWAKE 0x02 469#define RL_CFG5_PME_STS 0x01 470 471/* 472 * 8139C+ register definitions 473 */ 474 475/* RL_DUMPSTATS_LO register */ | 364/* 365 * EEPROM control register 366 */ 367#define RL_EE_DATAOUT 0x01 /* Data out */ 368#define RL_EE_DATAIN 0x02 /* Data in */ 369#define RL_EE_CLK 0x04 /* clock */ 370#define RL_EE_SEL 0x08 /* chip select */ 371#define RL_EE_MODE (0x40|0x80) --- 96 unchanged lines hidden (view full) --- 468#define RL_CFG5_WOL_LANWAKE 0x02 469#define RL_CFG5_PME_STS 0x01 470 471/* 472 * 8139C+ register definitions 473 */ 474 475/* RL_DUMPSTATS_LO register */ |
| 476 | |
| 477#define RL_DUMPSTATS_START 0x00000008 478 479/* Transmit start register */ | 476#define RL_DUMPSTATS_START 0x00000008 477 478/* Transmit start register */ |
| 480 | |
| 481#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 482#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 483#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 484 485/* 486 * Config 2 register, 8139C+/8169/8169S/8110S only 487 */ 488#define RL_CFG2_BUSFREQ 0x07 489#define RL_CFG2_BUSWIDTH 0x08 490#define RL_CFG2_AUXPWRSTS 0x10 491 492#define RL_BUSFREQ_33MHZ 0x00 493#define RL_BUSFREQ_66MHZ 0x01 494 495#define RL_BUSWIDTH_32BITS 0x00 496#define RL_BUSWIDTH_64BITS 0x08 497 498/* C+ mode command register */ | 479#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 480#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 481#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 482 483/* 484 * Config 2 register, 8139C+/8169/8169S/8110S only 485 */ 486#define RL_CFG2_BUSFREQ 0x07 487#define RL_CFG2_BUSWIDTH 0x08 488#define RL_CFG2_AUXPWRSTS 0x10 489 490#define RL_BUSFREQ_33MHZ 0x00 491#define RL_BUSFREQ_66MHZ 0x01 492 493#define RL_BUSWIDTH_32BITS 0x00 494#define RL_BUSWIDTH_64BITS 0x08 495 496/* C+ mode command register */ |
| 499 | |
| 500#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 501#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 502#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 503#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 504#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 505#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 506#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 507#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 508#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 509#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 510#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 511#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 512#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 513#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 514#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 515 516/* C+ early transmit threshold */ | 497#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 498#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 499#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 500#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 501#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 502#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 503#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 504#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 505#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 506#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 507#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 508#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 509#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 510#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 511#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 512 513/* C+ early transmit threshold */ |
| 517 | |
| 518#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 519 520/* Timer interrupt register */ 521#define RL_TIMERINT_8169_VAL 0x00001FFF 522#define RL_TIMER_MIN 0 523#define RL_TIMER_MAX 65 /* 65.528us */ 524#define RL_TIMER_DEFAULT RL_TIMER_MAX 525#define RL_TIMER_PCIE_CLK 125 /* 125MHZ */ 526#define RL_USECS(x) ((x) * RL_TIMER_PCIE_CLK) 527 528/* 529 * Gigabit PHY access register (8169 only) 530 */ | 514#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 515 516/* Timer interrupt register */ 517#define RL_TIMERINT_8169_VAL 0x00001FFF 518#define RL_TIMER_MIN 0 519#define RL_TIMER_MAX 65 /* 65.528us */ 520#define RL_TIMER_DEFAULT RL_TIMER_MAX 521#define RL_TIMER_PCIE_CLK 125 /* 125MHZ */ 522#define RL_USECS(x) ((x) * RL_TIMER_PCIE_CLK) 523 524/* 525 * Gigabit PHY access register (8169 only) 526 */ |
| 531 | |
| 532#define RL_PHYAR_PHYDATA 0x0000FFFF 533#define RL_PHYAR_PHYREG 0x001F0000 534#define RL_PHYAR_BUSY 0x80000000 535 536/* 537 * Gigabit media status (8169 only) 538 */ 539#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ --- 14 unchanged lines hidden (view full) --- 554 * 555 * We can sort of kludge together the same kind of buffer management 556 * used in previous drivers, but we have to do buffer copies almost all 557 * the time, so it doesn't really buy us much. 558 * 559 * For reception, there's just one large buffer where the chip stores 560 * all received packets. 561 */ | 527#define RL_PHYAR_PHYDATA 0x0000FFFF 528#define RL_PHYAR_PHYREG 0x001F0000 529#define RL_PHYAR_BUSY 0x80000000 530 531/* 532 * Gigabit media status (8169 only) 533 */ 534#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ --- 14 unchanged lines hidden (view full) --- 549 * 550 * We can sort of kludge together the same kind of buffer management 551 * used in previous drivers, but we have to do buffer copies almost all 552 * the time, so it doesn't really buy us much. 553 * 554 * For reception, there's just one large buffer where the chip stores 555 * all received packets. 556 */ |
| 562 | |
| 563#define RL_RX_BUF_SZ RL_RXBUF_64 564#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 565#define RL_TX_LIST_CNT 4 566#define RL_MIN_FRAMELEN 60 567#define RL_TX_8139_BUF_ALIGN 4 568#define RL_RX_8139_BUF_ALIGN 8 569#define RL_RX_8139_BUF_RESERVE sizeof(int64_t) 570#define RL_RX_8139_BUF_GUARD_SZ \ --- 66 unchanged lines hidden (view full) --- 637 * The 8139C+ and 8160 gigE chips support descriptor-based TX 638 * and RX. In fact, they even support TCP large send. Descriptors 639 * must be allocated in contiguous blocks that are aligned on a 640 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 641 */ 642 643/* 644 * RX/TX descriptor definition. When large send mode is enabled, the | 557#define RL_RX_BUF_SZ RL_RXBUF_64 558#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 559#define RL_TX_LIST_CNT 4 560#define RL_MIN_FRAMELEN 60 561#define RL_TX_8139_BUF_ALIGN 4 562#define RL_RX_8139_BUF_ALIGN 8 563#define RL_RX_8139_BUF_RESERVE sizeof(int64_t) 564#define RL_RX_8139_BUF_GUARD_SZ \ --- 66 unchanged lines hidden (view full) --- 631 * The 8139C+ and 8160 gigE chips support descriptor-based TX 632 * and RX. In fact, they even support TCP large send. Descriptors 633 * must be allocated in contiguous blocks that are aligned on a 634 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 635 */ 636 637/* 638 * RX/TX descriptor definition. When large send mode is enabled, the |
| 645 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and | 639 * lower 11 bits of the TX rl_cmdstat word are used to hold the MSS, and |
| 646 * the checksum offload bits are disabled. The structure layout is 647 * the same for RX and TX descriptors 648 */ | 640 * the checksum offload bits are disabled. The structure layout is 641 * the same for RX and TX descriptors 642 */ |
| 649 | |
| 650struct rl_desc { 651 uint32_t rl_cmdstat; 652 uint32_t rl_vlanctl; 653 uint32_t rl_bufaddr_lo; 654 uint32_t rl_bufaddr_hi; 655}; 656 657#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF --- 16 unchanged lines hidden (view full) --- 674#define RL_TDESC_CMD_IPCSUMV2 0x20000000 675#define RL_TDESC_CMD_MSSVALV2 0x1FFC0000 676#define RL_TDESC_CMD_MSSVALV2_SHIFT 18 677 678/* 679 * Error bits are valid only on the last descriptor of a frame 680 * (i.e. RL_TDESC_CMD_EOF == 1) 681 */ | 643struct rl_desc { 644 uint32_t rl_cmdstat; 645 uint32_t rl_vlanctl; 646 uint32_t rl_bufaddr_lo; 647 uint32_t rl_bufaddr_hi; 648}; 649 650#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF --- 16 unchanged lines hidden (view full) --- 667#define RL_TDESC_CMD_IPCSUMV2 0x20000000 668#define RL_TDESC_CMD_MSSVALV2 0x1FFC0000 669#define RL_TDESC_CMD_MSSVALV2_SHIFT 18 670 671/* 672 * Error bits are valid only on the last descriptor of a frame 673 * (i.e. RL_TDESC_CMD_EOF == 1) 674 */ |
| 682 | |
| 683#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 684#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 685#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 686#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 687#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 688#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 689#define RL_TDESC_STAT_OWN 0x80000000 690 691/* 692 * RX descriptor cmd/vlan definitions 693 */ | 675#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 676#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 677#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 678#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 679#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 680#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 681#define RL_TDESC_STAT_OWN 0x80000000 682 683/* 684 * RX descriptor cmd/vlan definitions 685 */ |
| 694 | |
| 695#define RL_RDESC_CMD_EOR 0x40000000 696#define RL_RDESC_CMD_OWN 0x80000000 697#define RL_RDESC_CMD_BUFLEN 0x00001FFF 698 699#define RL_RDESC_STAT_OWN 0x80000000 700#define RL_RDESC_STAT_EOR 0x40000000 701#define RL_RDESC_STAT_SOF 0x20000000 702#define RL_RDESC_STAT_EOF 0x10000000 --- 461 unchanged lines hidden --- | 686#define RL_RDESC_CMD_EOR 0x40000000 687#define RL_RDESC_CMD_OWN 0x80000000 688#define RL_RDESC_CMD_BUFLEN 0x00001FFF 689 690#define RL_RDESC_STAT_OWN 0x80000000 691#define RL_RDESC_STAT_EOR 0x40000000 692#define RL_RDESC_STAT_SOF 0x20000000 693#define RL_RDESC_STAT_EOF 0x10000000 --- 461 unchanged lines hidden --- |