| if_rlreg.h (227639) | if_rlreg.h (227914) |
|---|---|
| 1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/pci/if_rlreg.h 227639 2011-11-17 22:07:50Z yongari $ | 32 * $FreeBSD: head/sys/pci/if_rlreg.h 227914 2011-11-23 22:07:13Z yongari $ |
| 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 97 unchanged lines hidden (view full) --- 138#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 139#define RL_INTRMOD 0x00E2 /* 16 bits */ 140 141/* 142 * TX config register bits 143 */ 144#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 145#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ | 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 97 unchanged lines hidden (view full) --- 138#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 139#define RL_INTRMOD 0x00E2 /* 16 bits */ 140 141/* 142 * TX config register bits 143 */ 144#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 145#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ |
| 146#define RL_TXCFG_QUEUE_EMPTY 0x00000800 /* 8168E-VL or higher */ |
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| 146#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 147#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 148#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 149#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 150#define RL_TXCFG_HWREV 0x7CC00000 151 152#define RL_LOOPTEST_OFF 0x00000000 153#define RL_LOOPTEST_ON 0x00020000 --- 738 unchanged lines hidden (view full) --- 892#endif 893 894 struct task rl_inttask; 895 896 int rl_txstart; 897 int rl_int_rx_act; 898 int rl_int_rx_mod; 899 uint32_t rl_flags; | 147#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 148#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 149#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 150#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 151#define RL_TXCFG_HWREV 0x7CC00000 152 153#define RL_LOOPTEST_OFF 0x00000000 154#define RL_LOOPTEST_ON 0x00020000 --- 738 unchanged lines hidden (view full) --- 893#endif 894 895 struct task rl_inttask; 896 897 int rl_txstart; 898 int rl_int_rx_act; 899 int rl_int_rx_mod; 900 uint32_t rl_flags; |
| 900#define RL_FLAG_MSI 0x0001 901#define RL_FLAG_AUTOPAD 0x0002 902#define RL_FLAG_PHYWAKE_PM 0x0004 903#define RL_FLAG_PHYWAKE 0x0008 904#define RL_FLAG_JUMBOV2 0x0010 905#define RL_FLAG_PAR 0x0020 906#define RL_FLAG_DESCV2 0x0040 907#define RL_FLAG_MACSTAT 0x0080 908#define RL_FLAG_FASTETHER 0x0100 909#define RL_FLAG_CMDSTOP 0x0200 910#define RL_FLAG_MACRESET 0x0400 911#define RL_FLAG_MSIX 0x0800 912#define RL_FLAG_WOLRXENB 0x1000 913#define RL_FLAG_MACSLEEP 0x2000 914#define RL_FLAG_PCIE 0x4000 915#define RL_FLAG_LINK 0x8000 | 901#define RL_FLAG_MSI 0x00000001 902#define RL_FLAG_AUTOPAD 0x00000002 903#define RL_FLAG_PHYWAKE_PM 0x00000004 904#define RL_FLAG_PHYWAKE 0x00000008 905#define RL_FLAG_JUMBOV2 0x00000010 906#define RL_FLAG_PAR 0x00000020 907#define RL_FLAG_DESCV2 0x00000040 908#define RL_FLAG_MACSTAT 0x00000080 909#define RL_FLAG_FASTETHER 0x00000100 910#define RL_FLAG_CMDSTOP 0x00000200 911#define RL_FLAG_MACRESET 0x00000400 912#define RL_FLAG_MSIX 0x00000800 913#define RL_FLAG_WOLRXENB 0x00001000 914#define RL_FLAG_MACSLEEP 0x00002000 915#define RL_FLAG_WAIT_TXPOLL 0x00004000 916#define RL_FLAG_CMDSTOP_WAIT_TXQ 0x00008000 917#define RL_FLAG_PCIE 0x40000000 918#define RL_FLAG_LINK 0x80000000 |
| 916}; 917 918#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 919#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 920#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 921 922/* 923 * register space access macros --- 211 unchanged lines hidden --- | 919}; 920 921#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 922#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 923#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 924 925/* 926 * register space access macros --- 211 unchanged lines hidden --- |