| if_rlreg.h (224506) | if_rlreg.h (226995) |
|---|---|
| 1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/pci/if_rlreg.h 224506 2011-07-30 01:06:12Z yongari $ | 32 * $FreeBSD: head/sys/pci/if_rlreg.h 226995 2011-11-01 16:13:59Z marius $ |
| 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 551 unchanged lines hidden (view full) --- 592#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 593#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 594#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 595 596struct rl_type { 597 uint16_t rl_vid; 598 uint16_t rl_did; 599 int rl_basetype; | 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 551 unchanged lines hidden (view full) --- 592#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 593#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 594#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 595 596struct rl_type { 597 uint16_t rl_vid; 598 uint16_t rl_did; 599 int rl_basetype; |
| 600 char *rl_name; | 600 const char *rl_name; |
| 601}; 602 603struct rl_hwrev { 604 uint32_t rl_rev; 605 int rl_type; | 601}; 602 603struct rl_hwrev { 604 uint32_t rl_rev; 605 int rl_type; |
| 606 char *rl_desc; | 606 const char *rl_desc; |
| 607 int rl_max_mtu; 608}; 609 | 607 int rl_max_mtu; 608}; 609 |
| 610struct rl_mii_frame { 611 uint8_t mii_stdelim; 612 uint8_t mii_opcode; 613 uint8_t mii_phyaddr; 614 uint8_t mii_regaddr; 615 uint8_t mii_turnaround; 616 uint16_t mii_data; 617}; 618 619/* 620 * MII constants 621 */ 622#define RL_MII_STARTDELIM 0x01 623#define RL_MII_READOP 0x02 624#define RL_MII_WRITEOP 0x01 625#define RL_MII_TURNAROUND 0x02 626 | |
| 627#define RL_8129 1 628#define RL_8139 2 629#define RL_8139CPLUS 3 630#define RL_8169 4 631 632#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 633 (x)->rl_type == RL_8169) 634 --- 240 unchanged lines hidden (view full) --- 875 int rl_res_id; 876 int rl_res_type; 877 struct resource *rl_res_pba; 878 struct resource *rl_irq[RL_MSI_MESSAGES]; 879 void *rl_intrhand[RL_MSI_MESSAGES]; 880 device_t rl_miibus; 881 bus_dma_tag_t rl_parent_tag; 882 uint8_t rl_type; | 610#define RL_8129 1 611#define RL_8139 2 612#define RL_8139CPLUS 3 613#define RL_8169 4 614 615#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 616 (x)->rl_type == RL_8169) 617 --- 240 unchanged lines hidden (view full) --- 858 int rl_res_id; 859 int rl_res_type; 860 struct resource *rl_res_pba; 861 struct resource *rl_irq[RL_MSI_MESSAGES]; 862 void *rl_intrhand[RL_MSI_MESSAGES]; 863 device_t rl_miibus; 864 bus_dma_tag_t rl_parent_tag; 865 uint8_t rl_type; |
| 883 struct rl_hwrev *rl_hwrev; | 866 const struct rl_hwrev *rl_hwrev; |
| 884 int rl_eecmd_read; 885 int rl_eewidth; 886 int rl_txthresh; 887 struct rl_chain_data rl_cdata; 888 struct rl_list_data rl_ldata; 889 struct callout rl_stat_callout; 890 int rl_watchdog_timer; 891 struct mtx rl_mtx; --- 53 unchanged lines hidden (view full) --- 945 946#define CSR_READ_4(sc, reg) \ 947 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 948#define CSR_READ_2(sc, reg) \ 949 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 950#define CSR_READ_1(sc, reg) \ 951 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 952 | 867 int rl_eecmd_read; 868 int rl_eewidth; 869 int rl_txthresh; 870 struct rl_chain_data rl_cdata; 871 struct rl_list_data rl_ldata; 872 struct callout rl_stat_callout; 873 int rl_watchdog_timer; 874 struct mtx rl_mtx; --- 53 unchanged lines hidden (view full) --- 928 929#define CSR_READ_4(sc, reg) \ 930 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 931#define CSR_READ_2(sc, reg) \ 932 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 933#define CSR_READ_1(sc, reg) \ 934 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 935 |
| 936#define CSR_BARRIER(sc, reg, length, flags) \ 937 bus_space_barrier(sc->rl_btag, sc->rl_bhandle, reg, length, flags) 938 |
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| 953#define CSR_SETBIT_1(sc, offset, val) \ 954 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 955 956#define CSR_CLRBIT_1(sc, offset, val) \ 957 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 958 959#define CSR_SETBIT_2(sc, offset, val) \ 960 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) --- 183 unchanged lines hidden --- | 939#define CSR_SETBIT_1(sc, offset, val) \ 940 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 941 942#define CSR_CLRBIT_1(sc, offset, val) \ 943 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 944 945#define CSR_SETBIT_2(sc, offset, val) \ 946 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) --- 183 unchanged lines hidden --- |