| if_rlreg.h (217902) | if_rlreg.h (217911) |
|---|---|
| 1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/pci/if_rlreg.h 217902 2011-01-26 20:25:40Z yongari $ | 32 * $FreeBSD: head/sys/pci/if_rlreg.h 217911 2011-01-26 21:14:20Z yongari $ |
| 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 130 unchanged lines hidden (view full) --- 171#define RL_HWREV_8101E 0x34000000 172#define RL_HWREV_8102E 0x34800000 173#define RL_HWREV_8103E 0x34C00000 174#define RL_HWREV_8168B_SPIN2 0x38000000 175#define RL_HWREV_8168B_SPIN3 0x38400000 176#define RL_HWREV_8168C 0x3C000000 177#define RL_HWREV_8168C_SPIN2 0x3C400000 178#define RL_HWREV_8168CP 0x3C800000 | 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 130 unchanged lines hidden (view full) --- 171#define RL_HWREV_8101E 0x34000000 172#define RL_HWREV_8102E 0x34800000 173#define RL_HWREV_8103E 0x34C00000 174#define RL_HWREV_8168B_SPIN2 0x38000000 175#define RL_HWREV_8168B_SPIN3 0x38400000 176#define RL_HWREV_8168C 0x3C000000 177#define RL_HWREV_8168C_SPIN2 0x3C400000 178#define RL_HWREV_8168CP 0x3C800000 |
| 179#define RL_HWREV_8105E 0x40800000 |
|
| 179#define RL_HWREV_8139 0x60000000 180#define RL_HWREV_8139A 0x70000000 181#define RL_HWREV_8139AG 0x70800000 182#define RL_HWREV_8139B 0x78000000 183#define RL_HWREV_8130 0x7C000000 184#define RL_HWREV_8139C 0x74000000 185#define RL_HWREV_8139D 0x74400000 186#define RL_HWREV_8139CPLUS 0x74800000 --- 954 unchanged lines hidden --- | 180#define RL_HWREV_8139 0x60000000 181#define RL_HWREV_8139A 0x70000000 182#define RL_HWREV_8139AG 0x70800000 183#define RL_HWREV_8139B 0x78000000 184#define RL_HWREV_8130 0x7C000000 185#define RL_HWREV_8139C 0x74000000 186#define RL_HWREV_8139D 0x74400000 187#define RL_HWREV_8139CPLUS 0x74800000 --- 954 unchanged lines hidden --- |