| if_rlreg.h (215018) | if_rlreg.h (215019) |
|---|---|
| 1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/pci/if_rlreg.h 215018 2010-11-08 22:03:40Z yongari $ | 32 * $FreeBSD: head/sys/pci/if_rlreg.h 215019 2010-11-08 22:05:11Z yongari $ |
| 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 355 unchanged lines hidden (view full) --- 396#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 397#define RL_CFG0_PCS 0x40 398#define RL_CFG0_SCR 0x80 399 400/* 401 * Config 1 register 402 */ 403#define RL_CFG1_PWRDWN 0x01 | 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 355 unchanged lines hidden (view full) --- 396#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 397#define RL_CFG0_PCS 0x40 398#define RL_CFG0_SCR 0x80 399 400/* 401 * Config 1 register 402 */ 403#define RL_CFG1_PWRDWN 0x01 |
| 404#define RL_CFG1_PME 0x01 | 404#define RL_CFG1_PME 0x01 |
| 405#define RL_CFG1_SLEEP 0x02 406#define RL_CFG1_VPDEN 0x02 407#define RL_CFG1_IOMAP 0x04 408#define RL_CFG1_MEMMAP 0x08 409#define RL_CFG1_RSVD 0x10 410#define RL_CFG1_LWACT 0x10 411#define RL_CFG1_DRVLOAD 0x20 412#define RL_CFG1_LED0 0x40 --- 50 unchanged lines hidden (view full) --- 463 * Config 2 register, 8139C+/8169/8169S/8110S only 464 */ 465#define RL_CFG2_BUSFREQ 0x07 466#define RL_CFG2_BUSWIDTH 0x08 467#define RL_CFG2_AUXPWRSTS 0x10 468 469#define RL_BUSFREQ_33MHZ 0x00 470#define RL_BUSFREQ_66MHZ 0x01 | 405#define RL_CFG1_SLEEP 0x02 406#define RL_CFG1_VPDEN 0x02 407#define RL_CFG1_IOMAP 0x04 408#define RL_CFG1_MEMMAP 0x08 409#define RL_CFG1_RSVD 0x10 410#define RL_CFG1_LWACT 0x10 411#define RL_CFG1_DRVLOAD 0x20 412#define RL_CFG1_LED0 0x40 --- 50 unchanged lines hidden (view full) --- 463 * Config 2 register, 8139C+/8169/8169S/8110S only 464 */ 465#define RL_CFG2_BUSFREQ 0x07 466#define RL_CFG2_BUSWIDTH 0x08 467#define RL_CFG2_AUXPWRSTS 0x10 468 469#define RL_BUSFREQ_33MHZ 0x00 470#define RL_BUSFREQ_66MHZ 0x01 |
| 471 | 471 |
| 472#define RL_BUSWIDTH_32BITS 0x00 473#define RL_BUSWIDTH_64BITS 0x08 474 475/* C+ mode command register */ 476 477#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 478#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 479#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ --- 7 unchanged lines hidden (view full) --- 487#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 488#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 489#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 490#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 491#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 492 493/* C+ early transmit threshold */ 494 | 472#define RL_BUSWIDTH_32BITS 0x00 473#define RL_BUSWIDTH_64BITS 0x08 474 475/* C+ mode command register */ 476 477#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 478#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 479#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ --- 7 unchanged lines hidden (view full) --- 487#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 488#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 489#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 490#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 491#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 492 493/* C+ early transmit threshold */ 494 |
| 495#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ | 495#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ |
| 496 497/* 498 * Gigabit PHY access register (8169 only) 499 */ 500 501#define RL_PHYAR_PHYDATA 0x0000FFFF 502#define RL_PHYAR_PHYREG 0x001F0000 503#define RL_PHYAR_BUSY 0x80000000 --- 28 unchanged lines hidden (view full) --- 532#define RL_RX_BUF_SZ RL_RXBUF_64 533#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 534#define RL_TX_LIST_CNT 4 535#define RL_MIN_FRAMELEN 60 536#define RL_TX_8139_BUF_ALIGN 4 537#define RL_RX_8139_BUF_ALIGN 8 538#define RL_RX_8139_BUF_RESERVE sizeof(int64_t) 539#define RL_RX_8139_BUF_GUARD_SZ \ | 496 497/* 498 * Gigabit PHY access register (8169 only) 499 */ 500 501#define RL_PHYAR_PHYDATA 0x0000FFFF 502#define RL_PHYAR_PHYREG 0x001F0000 503#define RL_PHYAR_BUSY 0x80000000 --- 28 unchanged lines hidden (view full) --- 532#define RL_RX_BUF_SZ RL_RXBUF_64 533#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 534#define RL_TX_LIST_CNT 4 535#define RL_MIN_FRAMELEN 60 536#define RL_TX_8139_BUF_ALIGN 4 537#define RL_RX_8139_BUF_ALIGN 8 538#define RL_RX_8139_BUF_RESERVE sizeof(int64_t) 539#define RL_RX_8139_BUF_GUARD_SZ \ |
| 540 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE) | 540 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE) |
| 541#define RL_TXTHRESH(x) ((x) << 11) 542#define RL_TX_THRESH_INIT 96 543#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 544#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 545#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 546 547#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 548#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) --- 101 unchanged lines hidden (view full) --- 650#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 651#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 652#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 653 654#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 655#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 656/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 657#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 | 541#define RL_TXTHRESH(x) ((x) << 11) 542#define RL_TX_THRESH_INIT 96 543#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 544#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 545#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 546 547#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 548#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) --- 101 unchanged lines hidden (view full) --- 650#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 651#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 652#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 653 654#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 655#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 656/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 657#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 |
| 658#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 659#define RL_TDESC_CMD_IPCSUMV2 0x20000000 | 658#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 659#define RL_TDESC_CMD_IPCSUMV2 0x20000000 |
| 660 661/* 662 * Error bits are valid only on the last descriptor of a frame 663 * (i.e. RL_TDESC_CMD_EOF == 1) 664 */ 665 666#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 667#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ --- 74 unchanged lines hidden (view full) --- 742/* 743 * Rx/Tx descriptor parameters (8139C+ and 8169 only) 744 * 745 * 8139C+ 746 * Number of descriptors supported : up to 64 747 * Descriptor alignment : 256 bytes 748 * Tx buffer : At least 4 bytes in length. 749 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. | 660 661/* 662 * Error bits are valid only on the last descriptor of a frame 663 * (i.e. RL_TDESC_CMD_EOF == 1) 664 */ 665 666#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 667#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ --- 74 unchanged lines hidden (view full) --- 742/* 743 * Rx/Tx descriptor parameters (8139C+ and 8169 only) 744 * 745 * 8139C+ 746 * Number of descriptors supported : up to 64 747 * Descriptor alignment : 256 bytes 748 * Tx buffer : At least 4 bytes in length. 749 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. |
| 750 * | 750 * |
| 751 * 8169 752 * Number of descriptors supported : up to 1024 753 * Descriptor alignment : 256 bytes 754 * Tx buffer : At least 4 bytes in length. 755 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 756 */ 757#ifndef __NO_STRICT_ALIGNMENT 758#define RE_FIXUP_RX 1 --- 392 unchanged lines hidden --- | 751 * 8169 752 * Number of descriptors supported : up to 1024 753 * Descriptor alignment : 256 bytes 754 * Tx buffer : At least 4 bytes in length. 755 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 756 */ 757#ifndef __NO_STRICT_ALIGNMENT 758#define RE_FIXUP_RX 1 --- 392 unchanged lines hidden --- |