| if_rlreg.h (180176) | if_rlreg.h (180177) |
|---|---|
| 1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/pci/if_rlreg.h 180176 2008-07-02 07:54:53Z yongari $ | 32 * $FreeBSD: head/sys/pci/if_rlreg.h 180177 2008-07-02 08:00:14Z yongari $ |
| 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 128 unchanged lines hidden (view full) --- 169#define RL_HWREV_8139AG 0x70800000 170#define RL_HWREV_8139B 0x78000000 171#define RL_HWREV_8130 0x7C000000 172#define RL_HWREV_8139C 0x74000000 173#define RL_HWREV_8139D 0x74400000 174#define RL_HWREV_8139CPLUS 0x74800000 175#define RL_HWREV_8101 0x74c00000 176#define RL_HWREV_8100 0x78800000 | 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 128 unchanged lines hidden (view full) --- 169#define RL_HWREV_8139AG 0x70800000 170#define RL_HWREV_8139B 0x78000000 171#define RL_HWREV_8130 0x7C000000 172#define RL_HWREV_8139C 0x74000000 173#define RL_HWREV_8139D 0x74400000 174#define RL_HWREV_8139CPLUS 0x74800000 175#define RL_HWREV_8101 0x74c00000 176#define RL_HWREV_8100 0x78800000 |
| 177#define RL_HWREV_8169_8110SBL 0x7CC00000 |
|
| 177 178#define RL_TXDMA_16BYTES 0x00000000 179#define RL_TXDMA_32BYTES 0x00000100 180#define RL_TXDMA_64BYTES 0x00000200 181#define RL_TXDMA_128BYTES 0x00000300 182#define RL_TXDMA_256BYTES 0x00000400 183#define RL_TXDMA_512BYTES 0x00000500 184#define RL_TXDMA_1024BYTES 0x00000600 --- 904 unchanged lines hidden --- | 178 179#define RL_TXDMA_16BYTES 0x00000000 180#define RL_TXDMA_32BYTES 0x00000100 181#define RL_TXDMA_64BYTES 0x00000200 182#define RL_TXDMA_128BYTES 0x00000300 183#define RL_TXDMA_256BYTES 0x00000400 184#define RL_TXDMA_512BYTES 0x00000500 185#define RL_TXDMA_1024BYTES 0x00000600 --- 904 unchanged lines hidden --- |