| if_rlreg.h (176756) | if_rlreg.h (177522) |
|---|---|
| 1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/pci/if_rlreg.h 176756 2008-03-03 03:41:06Z yongari $ | 32 * $FreeBSD: head/sys/pci/if_rlreg.h 177522 2008-03-23 05:31:35Z yongari $ |
| 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 336 unchanged lines hidden (view full) --- 377 378/* 379 * Config 2 register 380 */ 381#define RL_CFG2_PCI33MHZ 0x00 382#define RL_CFG2_PCI66MHZ 0x01 383#define RL_CFG2_PCI64BIT 0x08 384#define RL_CFG2_AUXPWR 0x10 | 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 336 unchanged lines hidden (view full) --- 377 378/* 379 * Config 2 register 380 */ 381#define RL_CFG2_PCI33MHZ 0x00 382#define RL_CFG2_PCI66MHZ 0x01 383#define RL_CFG2_PCI64BIT 0x08 384#define RL_CFG2_AUXPWR 0x10 |
| 385#define RL_CFG2_MSI 0x20 |
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| 385 386/* 387 * Config 3 register 388 */ 389#define RL_CFG3_GRANTSEL 0x80 390#define RL_CFG3_WOL_MAGIC 0x20 391#define RL_CFG3_WOL_LINK 0x10 392#define RL_CFG3_FAST_B2B 0x01 --- 658 unchanged lines hidden --- | 386 387/* 388 * Config 3 register 389 */ 390#define RL_CFG3_GRANTSEL 0x80 391#define RL_CFG3_WOL_MAGIC 0x20 392#define RL_CFG3_WOL_LINK 0x10 393#define RL_CFG3_FAST_B2B 0x01 --- 658 unchanged lines hidden --- |