| if_rlreg.h (168828) | if_rlreg.h (171263) |
|---|---|
| 1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/pci/if_rlreg.h 168828 2007-04-18 00:40:43Z yongari $ | 32 * $FreeBSD: head/sys/pci/if_rlreg.h 171263 2007-07-06 00:05:12Z yongari $ |
| 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 266 unchanged lines hidden (view full) --- 307#define RL_EE_MODE (0x40|0x80) 308 309#define RL_EEMODE_OFF 0x00 310#define RL_EEMODE_AUTOLOAD 0x40 311#define RL_EEMODE_PROGRAM 0x80 312#define RL_EEMODE_WRITECFG (0x80|0x40) 313 314/* 9346 EEPROM commands */ | 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 266 unchanged lines hidden (view full) --- 307#define RL_EE_MODE (0x40|0x80) 308 309#define RL_EEMODE_OFF 0x00 310#define RL_EEMODE_AUTOLOAD 0x40 311#define RL_EEMODE_PROGRAM 0x80 312#define RL_EEMODE_WRITECFG (0x80|0x40) 313 314/* 9346 EEPROM commands */ |
| 315#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 316#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ |
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| 315 316#define RL_9346_WRITE 0x5 317#define RL_9346_READ 0x6 318#define RL_9346_ERASE 0x7 319#define RL_9346_EWEN 0x4 320#define RL_9346_EWEN_ADDR 0x30 321#define RL_9456_EWDS 0x4 322#define RL_9346_EWDS_ADDR 0x00 --- 663 unchanged lines hidden --- | 317 318#define RL_9346_WRITE 0x5 319#define RL_9346_READ 0x6 320#define RL_9346_ERASE 0x7 321#define RL_9346_EWEN 0x4 322#define RL_9346_EWEN_ADDR 0x30 323#define RL_9456_EWDS 0x4 324#define RL_9346_EWDS_ADDR 0x00 --- 663 unchanged lines hidden --- |