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if_rlreg.h (158878) if_rlreg.h (159962)
1/*-
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 15 unchanged lines hidden (view full) ---

24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
1/*-
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 15 unchanged lines hidden (view full) ---

24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: head/sys/pci/if_rlreg.h 158878 2006-05-24 11:55:25Z glebius $
32 * $FreeBSD: head/sys/pci/if_rlreg.h 159962 2006-06-26 20:31:32Z wpaul $
33 */
34
35/*
36 * RealTek 8129/8139 register offsets
37 */
38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */
39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
40#define RL_IDR2 0x0002

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140#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */
141#define RL_TXCFG_IFG 0x03000000 /* interframe gap */
142#define RL_TXCFG_HWREV 0x7CC00000
143
144#define RL_LOOPTEST_OFF 0x00000000
145#define RL_LOOPTEST_ON 0x00020000
146#define RL_LOOPTEST_ON_CPLUS 0x00060000
147
33 */
34
35/*
36 * RealTek 8129/8139 register offsets
37 */
38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */
39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
40#define RL_IDR2 0x0002

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140#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */
141#define RL_TXCFG_IFG 0x03000000 /* interframe gap */
142#define RL_TXCFG_HWREV 0x7CC00000
143
144#define RL_LOOPTEST_OFF 0x00000000
145#define RL_LOOPTEST_ON 0x00020000
146#define RL_LOOPTEST_ON_CPLUS 0x00060000
147
148#define RL_HWREV_8169 0x00000000
149#define RL_HWREV_8169S 0x04000000
150#define RL_HWREV_8169SB 0x10000000
151#define RL_HWREV_8110S 0x00800000
152#define RL_HWREV_8139 0x60000000
153#define RL_HWREV_8139A 0x70000000
154#define RL_HWREV_8139AG 0x70800000
155#define RL_HWREV_8139B 0x78000000
156#define RL_HWREV_8130 0x7C000000
157#define RL_HWREV_8139C 0x74000000
158#define RL_HWREV_8139D 0x74400000
159#define RL_HWREV_8139CPLUS 0x74800000
160#define RL_HWREV_8101 0x74c00000
161#define RL_HWREV_8100 0x78800000
162#define RL_HWREV_8168 0x30000000
148/* Known revision codes. */
163
149
150#define RL_HWREV_8169 0x00000000
151#define RL_HWREV_8110S 0x00800000
152#define RL_HWREV_8169S 0x04000000
153#define RL_HWREV_8169_8110SB 0x10000000
154#define RL_HWREV_8169_8110SC 0x18000000
155#define RL_HWREV_8100E 0x30800000
156#define RL_HWREV_8101E 0x34000000
157#define RL_HWREV_8168 0x38000000
158#define RL_HWREV_8139 0x60000000
159#define RL_HWREV_8139A 0x70000000
160#define RL_HWREV_8139AG 0x70800000
161#define RL_HWREV_8139B 0x78000000
162#define RL_HWREV_8130 0x7C000000
163#define RL_HWREV_8139C 0x74000000
164#define RL_HWREV_8139D 0x74400000
165#define RL_HWREV_8139CPLUS 0x74800000
166#define RL_HWREV_8101 0x74c00000
167#define RL_HWREV_8100 0x78800000
168
164#define RL_TXDMA_16BYTES 0x00000000
165#define RL_TXDMA_32BYTES 0x00000100
166#define RL_TXDMA_64BYTES 0x00000200
167#define RL_TXDMA_128BYTES 0x00000300
168#define RL_TXDMA_256BYTES 0x00000400
169#define RL_TXDMA_512BYTES 0x00000500
170#define RL_TXDMA_1024BYTES 0x00000600
171#define RL_TXDMA_2048BYTES 0x00000700

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202#define RL_ISR_TIMEOUT_EXPIRED 0x4000
203#define RL_ISR_SYSTEM_ERR 0x8000
204
205#define RL_INTRS \
206 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
207 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
208 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
209
169#define RL_TXDMA_16BYTES 0x00000000
170#define RL_TXDMA_32BYTES 0x00000100
171#define RL_TXDMA_64BYTES 0x00000200
172#define RL_TXDMA_128BYTES 0x00000300
173#define RL_TXDMA_256BYTES 0x00000400
174#define RL_TXDMA_512BYTES 0x00000500
175#define RL_TXDMA_1024BYTES 0x00000600
176#define RL_TXDMA_2048BYTES 0x00000700

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207#define RL_ISR_TIMEOUT_EXPIRED 0x4000
208#define RL_ISR_SYSTEM_ERR 0x8000
209
210#define RL_INTRS \
211 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
212 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
213 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
214
215#ifdef RE_TX_MODERATION
210#define RL_INTRS_CPLUS \
211 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
212 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
213 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
216#define RL_INTRS_CPLUS \
217 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
218 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
219 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
220#else
221#define RL_INTRS_CPLUS \
222 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \
223 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
224 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
225#endif
214
215/*
216 * Media status register. (8139 only)
217 */
218#define RL_MEDIASTAT_RXPAUSE 0x01
219#define RL_MEDIASTAT_TXPAUSE 0x02
220#define RL_MEDIASTAT_LINK 0x04
221#define RL_MEDIASTAT_SPEED10 0x08

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294#define RL_EE_MODE (0x40|0x80)
295
296#define RL_EEMODE_OFF 0x00
297#define RL_EEMODE_AUTOLOAD 0x40
298#define RL_EEMODE_PROGRAM 0x80
299#define RL_EEMODE_WRITECFG (0x80|0x40)
300
301/* 9346 EEPROM commands */
226
227/*
228 * Media status register. (8139 only)
229 */
230#define RL_MEDIASTAT_RXPAUSE 0x01
231#define RL_MEDIASTAT_TXPAUSE 0x02
232#define RL_MEDIASTAT_LINK 0x04
233#define RL_MEDIASTAT_SPEED10 0x08

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306#define RL_EE_MODE (0x40|0x80)
307
308#define RL_EEMODE_OFF 0x00
309#define RL_EEMODE_AUTOLOAD 0x40
310#define RL_EEMODE_PROGRAM 0x80
311#define RL_EEMODE_WRITECFG (0x80|0x40)
312
313/* 9346 EEPROM commands */
314
315#define RL_9346_WRITE 0x5
316#define RL_9346_READ 0x6
317#define RL_9346_ERASE 0x7
318#define RL_9346_EWEN 0x4
319#define RL_9346_EWEN_ADDR 0x30
320#define RL_9456_EWDS 0x4
321#define RL_9346_EWDS_ADDR 0x00
322
302#define RL_EECMD_WRITE 0x140
303#define RL_EECMD_READ_6BIT 0x180
304#define RL_EECMD_READ_8BIT 0x600
305#define RL_EECMD_ERASE 0x1c0
306
307#define RL_EE_ID 0x00
308#define RL_EE_PCI_VID 0x01
309#define RL_EE_PCI_DID 0x02

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616 * structure and use that value instead.
617 */
618#if !defined(__i386__) && !defined(__amd64__)
619#define RE_FIXUP_RX 1
620#endif
621
622#define RL_TX_DESC_CNT 64
623#define RL_RX_DESC_CNT RL_TX_DESC_CNT
323#define RL_EECMD_WRITE 0x140
324#define RL_EECMD_READ_6BIT 0x180
325#define RL_EECMD_READ_8BIT 0x600
326#define RL_EECMD_ERASE 0x1c0
327
328#define RL_EE_ID 0x00
329#define RL_EE_PCI_VID 0x01
330#define RL_EE_PCI_DID 0x02

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637 * structure and use that value instead.
638 */
639#if !defined(__i386__) && !defined(__amd64__)
640#define RE_FIXUP_RX 1
641#endif
642
643#define RL_TX_DESC_CNT 64
644#define RL_RX_DESC_CNT RL_TX_DESC_CNT
645
624#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc))
625#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc))
626#define RL_RING_ALIGN 256
627#define RL_IFQ_MAXLEN 512
628#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT)
629#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
630#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask)
631#define RL_PKTSZ(x) ((x)/* >> 3*/)

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651 int rl_idx;
652 int rl_maxsegs;
653 uint32_t rl_flags;
654 struct rl_desc *rl_ring;
655};
656
657struct rl_list_data {
658 struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT];
646#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc))
647#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc))
648#define RL_RING_ALIGN 256
649#define RL_IFQ_MAXLEN 512
650#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT)
651#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
652#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask)
653#define RL_PKTSZ(x) ((x)/* >> 3*/)

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673 int rl_idx;
674 int rl_maxsegs;
675 uint32_t rl_flags;
676 struct rl_desc *rl_ring;
677};
678
679struct rl_list_data {
680 struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT];
659 struct mbuf *rl_rx_mbuf[RL_TX_DESC_CNT];
681 struct mbuf *rl_rx_mbuf[RL_RX_DESC_CNT];
660 int rl_tx_prodidx;
661 int rl_rx_prodidx;
662 int rl_tx_considx;
663 int rl_tx_free;
664 bus_dmamap_t rl_tx_dmamap[RL_TX_DESC_CNT];
665 bus_dmamap_t rl_rx_dmamap[RL_RX_DESC_CNT];
666 bus_dma_tag_t rl_mtag; /* mbuf mapping tag */
667 bus_dma_tag_t rl_stag; /* stats mapping tag */

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677 struct rl_desc *rl_tx_list;
678 bus_addr_t rl_tx_list_addr;
679};
680
681struct rl_softc {
682 struct ifnet *rl_ifp; /* interface info */
683 bus_space_handle_t rl_bhandle; /* bus space handle */
684 bus_space_tag_t rl_btag; /* bus space tag */
682 int rl_tx_prodidx;
683 int rl_rx_prodidx;
684 int rl_tx_considx;
685 int rl_tx_free;
686 bus_dmamap_t rl_tx_dmamap[RL_TX_DESC_CNT];
687 bus_dmamap_t rl_rx_dmamap[RL_RX_DESC_CNT];
688 bus_dma_tag_t rl_mtag; /* mbuf mapping tag */
689 bus_dma_tag_t rl_stag; /* stats mapping tag */

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699 struct rl_desc *rl_tx_list;
700 bus_addr_t rl_tx_list_addr;
701};
702
703struct rl_softc {
704 struct ifnet *rl_ifp; /* interface info */
705 bus_space_handle_t rl_bhandle; /* bus space handle */
706 bus_space_tag_t rl_btag; /* bus space tag */
707 device_t rl_dev;
685 struct resource *rl_res;
686 struct resource *rl_irq;
687 void *rl_intrhand;
688 device_t rl_miibus;
689 bus_dma_tag_t rl_parent_tag;
690 bus_dma_tag_t rl_tag;
691 uint8_t rl_type;
692 int rl_eecmd_read;
708 struct resource *rl_res;
709 struct resource *rl_irq;
710 void *rl_intrhand;
711 device_t rl_miibus;
712 bus_dma_tag_t rl_parent_tag;
713 bus_dma_tag_t rl_tag;
714 uint8_t rl_type;
715 int rl_eecmd_read;
716 int rl_eewidth;
693 uint8_t rl_stats_no_timeout;
694 int rl_txthresh;
695 struct rl_chain_data rl_cdata;
696 struct rl_list_data rl_ldata;
697 struct callout rl_stat_callout;
698 struct mtx rl_mtx;
699 struct mbuf *rl_head;
700 struct mbuf *rl_tail;
701 uint32_t rl_hwrev;
702 uint32_t rl_rxlenmask;
703 int rl_testmode;
704 int suspended; /* 0 = normal 1 = suspended */
705#ifdef DEVICE_POLLING
706 int rxcycles;
707#endif
717 uint8_t rl_stats_no_timeout;
718 int rl_txthresh;
719 struct rl_chain_data rl_cdata;
720 struct rl_list_data rl_ldata;
721 struct callout rl_stat_callout;
722 struct mtx rl_mtx;
723 struct mbuf *rl_head;
724 struct mbuf *rl_tail;
725 uint32_t rl_hwrev;
726 uint32_t rl_rxlenmask;
727 int rl_testmode;
728 int suspended; /* 0 = normal 1 = suspended */
729#ifdef DEVICE_POLLING
730 int rxcycles;
731#endif
732
733 struct task rl_txtask;
734 struct task rl_inttask;
735
736 struct mtx rl_intlock;
737 int rl_txstart;
738 int rl_link;
708};
709
710#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx)
711#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx)
712#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED)
713
714/*
715 * register space access macros

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725
726#define CSR_READ_4(sc, reg) \
727 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg)
728#define CSR_READ_2(sc, reg) \
729 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg)
730#define CSR_READ_1(sc, reg) \
731 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg)
732
739};
740
741#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx)
742#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx)
743#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED)
744
745/*
746 * register space access macros

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756
757#define CSR_READ_4(sc, reg) \
758 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg)
759#define CSR_READ_2(sc, reg) \
760 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg)
761#define CSR_READ_1(sc, reg) \
762 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg)
763
764#define CSR_SETBIT_1(sc, offset, val) \
765 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
766
767#define CSR_CLRBIT_1(sc, offset, val) \
768 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
769
770#define CSR_SETBIT_2(sc, offset, val) \
771 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
772
773#define CSR_CLRBIT_2(sc, offset, val) \
774 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
775
776#define CSR_SETBIT_4(sc, offset, val) \
777 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val))
778
779#define CSR_CLRBIT_4(sc, offset, val) \
780 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))
781
733#define RL_TIMEOUT 1000
734
735/*
736 * General constants that are fun to know.
737 *
738 * RealTek PCI vendor ID
739 */
740#define RT_VENDORID 0x10EC
741
742/*
743 * RealTek chip device IDs.
744 */
745#define RT_DEVICEID_8129 0x8129
782#define RL_TIMEOUT 1000
783
784/*
785 * General constants that are fun to know.
786 *
787 * RealTek PCI vendor ID
788 */
789#define RT_VENDORID 0x10EC
790
791/*
792 * RealTek chip device IDs.
793 */
794#define RT_DEVICEID_8129 0x8129
795#define RT_DEVICEID_8101E 0x8136
746#define RT_DEVICEID_8138 0x8138
747#define RT_DEVICEID_8139 0x8139
796#define RT_DEVICEID_8138 0x8138
797#define RT_DEVICEID_8139 0x8139
748#define RT_DEVICEID_8168 0x8168
798#define RT_DEVICEID_8169SC 0x8167
799#define RT_DEVICEID_8168 0x8168
749#define RT_DEVICEID_8169 0x8169
750#define RT_DEVICEID_8100 0x8100
751
752#define RT_REVID_8139CPLUS 0x20
753
754/*
755 * Accton PCI vendor ID
756 */

--- 166 unchanged lines hidden --- 		800#define RT_DEVICEID_8169 0x8169
801#define RT_DEVICEID_8100 0x8100
802
803#define RT_REVID_8139CPLUS 0x20
804
805/*
806 * Accton PCI vendor ID
807 */

--- 166 unchanged lines hidden ---