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if_rlreg.h (131253) if_rlreg.h (131605)
1/*
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
1/*
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: head/sys/pci/if_rlreg.h 131253 2004-06-28 20:07:03Z imp $
32 * $FreeBSD: head/sys/pci/if_rlreg.h 131605 2004-07-05 02:46:42Z bms $
33 */
34
35/*
36 * RealTek 8129/8139 register offsets
37 */
38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */
39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
40#define RL_IDR2 0x0002

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427#define RL_TX_MAXDMA RL_TXDMA_2048BYTES
428
429#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ)
430#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA)
431
432#define RL_ETHER_ALIGN 2
433
434struct rl_chain_data {
33 */
34
35/*
36 * RealTek 8129/8139 register offsets
37 */
38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */
39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
40#define RL_IDR2 0x0002

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427#define RL_TX_MAXDMA RL_TXDMA_2048BYTES
428
429#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ)
430#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA)
431
432#define RL_ETHER_ALIGN 2
433
434struct rl_chain_data {
435 u_int16_t cur_rx;
436 caddr_t rl_rx_buf;
437 caddr_t rl_rx_buf_ptr;
435 uint16_t cur_rx;
436 uint8_t *rl_rx_buf;
437 uint8_t *rl_rx_buf_ptr;
438 bus_dmamap_t rl_rx_dmamap;
439
440 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT];
441 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT];
438 bus_dmamap_t rl_rx_dmamap;
439
440 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT];
441 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT];
442 u_int8_t last_tx;
443 u_int8_t cur_tx;
442 uint8_t last_tx;
443 uint8_t cur_tx;
444};
445
446#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT)
447#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)
448#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)
449#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx])
450#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx])
451#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
452#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
453#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
454#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
455
456struct rl_type {
444};
445
446#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT)
447#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)
448#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)
449#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx])
450#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx])
451#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
452#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
453#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
454#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
455
456struct rl_type {
457 u_int16_t rl_vid;
458 u_int16_t rl_did;
457 uint16_t rl_vid;
458 uint16_t rl_did;
459 int rl_basetype;
460 char *rl_name;
461};
462
463struct rl_hwrev {
459 int rl_basetype;
460 char *rl_name;
461};
462
463struct rl_hwrev {
464 u_int32_t rl_rev;
464 uint32_t rl_rev;
465 int rl_type;
466 char *rl_desc;
467};
468
469struct rl_mii_frame {
465 int rl_type;
466 char *rl_desc;
467};
468
469struct rl_mii_frame {
470 u_int8_t mii_stdelim;
471 u_int8_t mii_opcode;
472 u_int8_t mii_phyaddr;
473 u_int8_t mii_regaddr;
474 u_int8_t mii_turnaround;
475 u_int16_t mii_data;
470 uint8_t mii_stdelim;
471 uint8_t mii_opcode;
472 uint8_t mii_phyaddr;
473 uint8_t mii_regaddr;
474 uint8_t mii_turnaround;
475 uint16_t mii_data;
476};
477
478/*
479 * MII constants
480 */
481#define RL_MII_STARTDELIM 0x01
482#define RL_MII_READOP 0x02
483#define RL_MII_WRITEOP 0x01

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501/*
502 * RX/TX descriptor definition. When large send mode is enabled, the
503 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and
504 * the checksum offload bits are disabled. The structure layout is
505 * the same for RX and TX descriptors
506 */
507
508struct rl_desc {
476};
477
478/*
479 * MII constants
480 */
481#define RL_MII_STARTDELIM 0x01
482#define RL_MII_READOP 0x02
483#define RL_MII_WRITEOP 0x01

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501/*
502 * RX/TX descriptor definition. When large send mode is enabled, the
503 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and
504 * the checksum offload bits are disabled. The structure layout is
505 * the same for RX and TX descriptors
506 */
507
508struct rl_desc {
509 u_int32_t rl_cmdstat;
510 u_int32_t rl_vlanctl;
511 u_int32_t rl_bufaddr_lo;
512 u_int32_t rl_bufaddr_hi;
509 uint32_t rl_cmdstat;
510 uint32_t rl_vlanctl;
511 uint32_t rl_bufaddr_lo;
512 uint32_t rl_bufaddr_hi;
513};
514
515#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF
516#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */
517#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */
518#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */
519#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */
520#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */

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580 RL_PROTOID_TCPIP)
581#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
582 RL_PROTOID_UDPIP)
583
584/*
585 * Statistics counter structure (8139C+ and 8169 only)
586 */
587struct rl_stats {
513};
514
515#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF
516#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */
517#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */
518#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */
519#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */
520#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */

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580 RL_PROTOID_TCPIP)
581#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
582 RL_PROTOID_UDPIP)
583
584/*
585 * Statistics counter structure (8139C+ and 8169 only)
586 */
587struct rl_stats {
588 u_int32_t rl_tx_pkts_lo;
589 u_int32_t rl_tx_pkts_hi;
590 u_int32_t rl_tx_errs_lo;
591 u_int32_t rl_tx_errs_hi;
592 u_int32_t rl_tx_errs;
593 u_int16_t rl_missed_pkts;
594 u_int16_t rl_rx_framealign_errs;
595 u_int32_t rl_tx_onecoll;
596 u_int32_t rl_tx_multicolls;
597 u_int32_t rl_rx_ucasts_hi;
598 u_int32_t rl_rx_ucasts_lo;
599 u_int32_t rl_rx_bcasts_lo;
600 u_int32_t rl_rx_bcasts_hi;
601 u_int32_t rl_rx_mcasts;
602 u_int16_t rl_tx_aborts;
603 u_int16_t rl_rx_underruns;
588 uint32_t rl_tx_pkts_lo;
589 uint32_t rl_tx_pkts_hi;
590 uint32_t rl_tx_errs_lo;
591 uint32_t rl_tx_errs_hi;
592 uint32_t rl_tx_errs;
593 uint16_t rl_missed_pkts;
594 uint16_t rl_rx_framealign_errs;
595 uint32_t rl_tx_onecoll;
596 uint32_t rl_tx_multicolls;
597 uint32_t rl_rx_ucasts_hi;
598 uint32_t rl_rx_ucasts_lo;
599 uint32_t rl_rx_bcasts_lo;
600 uint32_t rl_rx_bcasts_hi;
601 uint32_t rl_rx_mcasts;
602 uint16_t rl_tx_aborts;
603 uint16_t rl_rx_underruns;
604};
605
606#define RL_RX_DESC_CNT 64
607#define RL_TX_DESC_CNT 64
608#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc))
609#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc))
610#define RL_RING_ALIGN 256
611#define RL_IFQ_MAXLEN 512
612#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT)
613#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
614#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask)
615#define RL_PKTSZ(x) ((x)/* >> 3*/)
616
604};
605
606#define RL_RX_DESC_CNT 64
607#define RL_TX_DESC_CNT 64
608#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc))
609#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc))
610#define RL_RING_ALIGN 256
611#define RL_IFQ_MAXLEN 512
612#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT)
613#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
614#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask)
615#define RL_PKTSZ(x) ((x)/* >> 3*/)
616
617#define RL_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF)
618#define RL_ADDR_HI(y) ((u_int64_t) (y) >> 32)
617#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
618#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32)
619
620#define RL_JUMBO_FRAMELEN 9018
621#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
622
623struct rl_softc;
624
625struct rl_dmaload_arg {
626 struct rl_softc *sc;
627 int rl_idx;
628 int rl_maxsegs;
619
620#define RL_JUMBO_FRAMELEN 9018
621#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
622
623struct rl_softc;
624
625struct rl_dmaload_arg {
626 struct rl_softc *sc;
627 int rl_idx;
628 int rl_maxsegs;
629 u_int32_t rl_flags;
629 uint32_t rl_flags;
630 struct rl_desc *rl_ring;
631};
632
633struct rl_list_data {
634 struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT];
635 struct mbuf *rl_rx_mbuf[RL_TX_DESC_CNT];
636 int rl_tx_prodidx;
637 int rl_rx_prodidx;

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659 bus_space_handle_t rl_bhandle; /* bus space handle */
660 bus_space_tag_t rl_btag; /* bus space tag */
661 struct resource *rl_res;
662 struct resource *rl_irq;
663 void *rl_intrhand;
664 device_t rl_miibus;
665 bus_dma_tag_t rl_parent_tag;
666 bus_dma_tag_t rl_tag;
630 struct rl_desc *rl_ring;
631};
632
633struct rl_list_data {
634 struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT];
635 struct mbuf *rl_rx_mbuf[RL_TX_DESC_CNT];
636 int rl_tx_prodidx;
637 int rl_rx_prodidx;

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659 bus_space_handle_t rl_bhandle; /* bus space handle */
660 bus_space_tag_t rl_btag; /* bus space tag */
661 struct resource *rl_res;
662 struct resource *rl_irq;
663 void *rl_intrhand;
664 device_t rl_miibus;
665 bus_dma_tag_t rl_parent_tag;
666 bus_dma_tag_t rl_tag;
667 u_int8_t rl_unit; /* interface number */
668 u_int8_t rl_type;
667 uint8_t rl_unit; /* interface number */
668 uint8_t rl_type;
669 int rl_eecmd_read;
669 int rl_eecmd_read;
670 u_int8_t rl_stats_no_timeout;
670 uint8_t rl_stats_no_timeout;
671 int rl_txthresh;
672 struct rl_chain_data rl_cdata;
673 struct rl_list_data rl_ldata;
674 struct callout_handle rl_stat_ch;
675 struct mtx rl_mtx;
676 struct mbuf *rl_head;
677 struct mbuf *rl_tail;
671 int rl_txthresh;
672 struct rl_chain_data rl_cdata;
673 struct rl_list_data rl_ldata;
674 struct callout_handle rl_stat_ch;
675 struct mtx rl_mtx;
676 struct mbuf *rl_head;
677 struct mbuf *rl_tail;
678 u_int32_t rl_hwrev;
679 u_int32_t rl_rxlenmask;
678 uint32_t rl_hwrev;
679 uint32_t rl_rxlenmask;
680 int rl_testmode;
681 int suspended; /* 0 = normal 1 = suspended */
682#ifdef DEVICE_POLLING
683 int rxcycles;
684#endif
685};
686
687#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx)

--- 186 unchanged lines hidden --- 		680 int rl_testmode;
681 int suspended; /* 0 = normal 1 = suspended */
682#ifdef DEVICE_POLLING
683 int rxcycles;
684#endif
685};
686
687#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx)

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