| if_rlreg.h (119981) | if_rlreg.h (120043) |
|---|---|
| 1/* 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/* 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/pci/if_rlreg.h 119981 2003-09-11 06:56:46Z wpaul $ | 32 * $FreeBSD: head/sys/pci/if_rlreg.h 120043 2003-09-13 23:51:35Z wpaul $ |
| 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 30 unchanged lines hidden (view full) --- 71#define RL_ISR 0x003E /* interrupt status register */ 72#define RL_TXCFG 0x0040 /* transmit config */ 73#define RL_RXCFG 0x0044 /* receive config */ 74#define RL_TIMERCNT 0x0048 /* timer count register */ 75#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76#define RL_EECMD 0x0050 /* EEPROM command register */ 77#define RL_CFG0 0x0051 /* config register #0 */ 78#define RL_CFG1 0x0052 /* config register #1 */ | 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 30 unchanged lines hidden (view full) --- 71#define RL_ISR 0x003E /* interrupt status register */ 72#define RL_TXCFG 0x0040 /* transmit config */ 73#define RL_RXCFG 0x0044 /* receive config */ 74#define RL_TIMERCNT 0x0048 /* timer count register */ 75#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76#define RL_EECMD 0x0050 /* EEPROM command register */ 77#define RL_CFG0 0x0051 /* config register #0 */ 78#define RL_CFG1 0x0052 /* config register #1 */ |
| 79 /* 0053-0057 reserved */ | 79 /* 0053-0057 reserved */ |
| 80#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 81 /* 0059-005A reserved */ 82#define RL_MII 0x005A /* 8129 chip only */ 83#define RL_HALTCLK 0x005B 84#define RL_MULTIINTR 0x005C /* multiple interrupt */ 85#define RL_PCIREV 0x005E /* PCI revision value */ 86 /* 005F reserved */ 87#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ --- 17 unchanged lines hidden (view full) --- 105 * the 8169 gigE chip. 106 */ 107#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 108#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 109#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 110#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 111#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 112#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ | 80#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 81 /* 0059-005A reserved */ 82#define RL_MII 0x005A /* 8129 chip only */ 83#define RL_HALTCLK 0x005B 84#define RL_MULTIINTR 0x005C /* multiple interrupt */ 85#define RL_PCIREV 0x005E /* PCI revision value */ 86 /* 005F reserved */ 87#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ --- 17 unchanged lines hidden (view full) --- 105 * the 8169 gigE chip. 106 */ 107#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 108#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 109#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 110#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 111#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 112#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ |
| 113#define RL_CFG2 0x0053 |
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| 113#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 114#define RL_TXSTART 0x00D9 /* 8 bits */ 115#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 116#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 117#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 118#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 119 120/* --- 228 unchanged lines hidden (view full) --- 349#define RL_DUMPSTATS_START 0x00000008 350 351/* Transmit start register */ 352 353#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 354#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 355#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 356 | 114#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 115#define RL_TXSTART 0x00D9 /* 8 bits */ 116#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 117#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 118#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 119#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 120 121/* --- 228 unchanged lines hidden (view full) --- 350#define RL_DUMPSTATS_START 0x00000008 351 352/* Transmit start register */ 353 354#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 355#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 356#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 357 |
| 358/* 359 * Config 2 register, 8139C+/8169/8169S/8110S only 360 */ 361#define RL_CFG2_BUSFREQ 0x07 362#define RL_CFG2_BUSWIDTH 0x08 363#define RL_CFG2_AUXPWRSTS 0x10 364 365#define RL_BUSFREQ_33MHZ 0x00 366#define RL_BUSFREQ_66MHZ 0x01 367 368#define RL_BUSWIDTH_32BITS 0x00 369#define RL_BUSWIDTH_64BITS 0x08 370 |
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| 357/* C+ mode command register */ 358 359#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 360#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 361#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 362#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 363#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 364#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ --- 508 unchanged lines hidden --- | 371/* C+ mode command register */ 372 373#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 374#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 375#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 376#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 377#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 378#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ --- 508 unchanged lines hidden --- |