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if_rl.c (94400) if_rl.c (94883)
1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: head/sys/pci/if_rl.c 94400 2002-04-11 06:12:51Z wpaul $
32 * $FreeBSD: head/sys/pci/if_rl.c 94883 2002-04-16 22:03:14Z luigi $
33 */
34
35/*
36 * RealTek 8129/8139 PCI NIC driver
37 *
38 * Supports several extremely cheap PCI 10/100 adapters based on
39 * the RealTek chipset. Datasheets can be obtained from
40 * www.realtek.com.tw.

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126 * uniprocessor systems though.
127 */
128#define RL_USEIOSPACE
129
130#include <pci/if_rlreg.h>
131
132#ifndef lint
133static const char rcsid[] =
33 */
34
35/*
36 * RealTek 8129/8139 PCI NIC driver
37 *
38 * Supports several extremely cheap PCI 10/100 adapters based on
39 * the RealTek chipset. Datasheets can be obtained from
40 * www.realtek.com.tw.

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126 * uniprocessor systems though.
127 */
128#define RL_USEIOSPACE
129
130#include <pci/if_rlreg.h>
131
132#ifndef lint
133static const char rcsid[] =
134 "$FreeBSD: head/sys/pci/if_rl.c 94400 2002-04-11 06:12:51Z wpaul $";
134 "$FreeBSD: head/sys/pci/if_rl.c 94883 2002-04-16 22:03:14Z luigi $";
135#endif
136
137/*
138 * Various supported device vendors/types and their names.
139 */
140static struct rl_type rl_devs[] = {
141 { RT_VENDORID, RT_DEVICEID_8129,
142 "RealTek 8129 10/100BaseTX" },

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1178 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1179
1180 if (limit < cur_rx)
1181 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1182 else
1183 max_bytes = limit - cur_rx;
1184
1185 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
135#endif
136
137/*
138 * Various supported device vendors/types and their names.
139 */
140static struct rl_type rl_devs[] = {
141 { RT_VENDORID, RT_DEVICEID_8129,
142 "RealTek 8129 10/100BaseTX" },

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1178 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1179
1180 if (limit < cur_rx)
1181 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1182 else
1183 max_bytes = limit - cur_rx;
1184
1185 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1186#ifdef DEVICE_POLLING
1187 if (ifp->if_ipending & IFF_POLLING) {
1188 if (sc->rxcycles <= 0)
1189 break;
1190 sc->rxcycles--;
1191 }
1192#endif /* DEVICE_POLLING */
1186 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1187 rxstat = *(u_int32_t *)rxbufpos;
1188
1189 /*
1190 * Here's a totally undocumented fact for you. When the
1191 * RealTek chip is in the process of copying a packet into
1192 * RAM for you, the length will be 0xfff0. If you spot a
1193 * packet header with this value, you need to stop. The

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1343 mii_tick(mii);
1344
1345 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1346 RL_UNLOCK(sc);
1347
1348 return;
1349}
1350
1193 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1194 rxstat = *(u_int32_t *)rxbufpos;
1195
1196 /*
1197 * Here's a totally undocumented fact for you. When the
1198 * RealTek chip is in the process of copying a packet into
1199 * RAM for you, the length will be 0xfff0. If you spot a
1200 * packet header with this value, you need to stop. The

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1350 mii_tick(mii);
1351
1352 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1353 RL_UNLOCK(sc);
1354
1355 return;
1356}
1357
1358#ifdef DEVICE_POLLING
1359static void
1360rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count)
1361{
1362 struct rl_softc *sc = ifp->if_softc;
1363
1364 RL_LOCK(sc);
1365 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1366 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1367 goto done;
1368 }
1369
1370 sc->rxcycles = count;
1371 rl_rxeof(sc);
1372 rl_txeof(sc);
1373 if (ifp->if_snd.ifq_head != NULL)
1374 rl_start(ifp);
1375
1376 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1377 u_int16_t status;
1378
1379 status = CSR_READ_2(sc, RL_ISR);
1380 if (status)
1381 CSR_WRITE_2(sc, RL_ISR, status);
1382
1383 /*
1384 * XXX check behaviour on receiver stalls.
1385 */
1386
1387 if (status & RL_ISR_SYSTEM_ERR) {
1388 rl_reset(sc);
1389 rl_init(sc);
1390 }
1391 }
1392done:
1393 RL_UNLOCK(sc);
1394}
1395#endif /* DEVICE_POLLING */
1396
1351static void rl_intr(arg)
1352 void *arg;
1353{
1354 struct rl_softc *sc;
1355 struct ifnet *ifp;
1356 u_int16_t status;
1357
1358 sc = arg;
1359
1360 if (sc->suspended) {
1361 return;
1362 }
1363
1364 RL_LOCK(sc);
1365 ifp = &sc->arpcom.ac_if;
1366
1397static void rl_intr(arg)
1398 void *arg;
1399{
1400 struct rl_softc *sc;
1401 struct ifnet *ifp;
1402 u_int16_t status;
1403
1404 sc = arg;
1405
1406 if (sc->suspended) {
1407 return;
1408 }
1409
1410 RL_LOCK(sc);
1411 ifp = &sc->arpcom.ac_if;
1412
1367 /* Disable interrupts. */
1368 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1413#ifdef DEVICE_POLLING
1414 if (ifp->if_ipending & IFF_POLLING)
1415 goto done;
1416 if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */
1417 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1418 rl_poll(ifp, 0, 1);
1419 goto done;
1420 }
1421#endif /* DEVICE_POLLING */
1369
1370 for (;;) {
1371
1372 status = CSR_READ_2(sc, RL_ISR);
1373 if (status)
1374 CSR_WRITE_2(sc, RL_ISR, status);
1375
1376 if ((status & RL_INTRS) == 0)

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1387
1388 if (status & RL_ISR_SYSTEM_ERR) {
1389 rl_reset(sc);
1390 rl_init(sc);
1391 }
1392
1393 }
1394
1422
1423 for (;;) {
1424
1425 status = CSR_READ_2(sc, RL_ISR);
1426 if (status)
1427 CSR_WRITE_2(sc, RL_ISR, status);
1428
1429 if ((status & RL_INTRS) == 0)

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1440
1441 if (status & RL_ISR_SYSTEM_ERR) {
1442 rl_reset(sc);
1443 rl_init(sc);
1444 }
1445
1446 }
1447
1395 /* Re-enable interrupts. */
1396 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1397
1398 if (ifp->if_snd.ifq_head != NULL)
1399 rl_start(ifp);
1400
1448 if (ifp->if_snd.ifq_head != NULL)
1449 rl_start(ifp);
1450
1451#ifdef DEVICE_POLLING
1452done:
1453#endif
1401 RL_UNLOCK(sc);
1402
1403 return;
1404}
1405
1406/*
1407 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1408 * pointers to the fragment pointers.

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1584 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1585 }
1586
1587 /*
1588 * Program the multicast filter, if necessary.
1589 */
1590 rl_setmulti(sc);
1591
1454 RL_UNLOCK(sc);
1455
1456 return;
1457}
1458
1459/*
1460 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1461 * pointers to the fragment pointers.

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1637 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1638 }
1639
1640 /*
1641 * Program the multicast filter, if necessary.
1642 */
1643 rl_setmulti(sc);
1644
1645#ifdef DEVICE_POLLING
1592 /*
1646 /*
1647 * Disable interrupts if we are polling.
1648 */
1649 if (ifp->if_ipending & IFF_POLLING)
1650 CSR_WRITE_2(sc, RL_IMR, 0);
1651 else /* otherwise ... */
1652#endif /* DEVICE_POLLING */
1653 /*
1593 * Enable interrupts.
1594 */
1595 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1596
1597 /* Set initial TX threshold */
1598 sc->rl_txthresh = RL_TX_THRESH_INIT;
1599
1600 /* Start RX/TX process. */

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1727 register int i;
1728 struct ifnet *ifp;
1729
1730 RL_LOCK(sc);
1731 ifp = &sc->arpcom.ac_if;
1732 ifp->if_timer = 0;
1733
1734 untimeout(rl_tick, sc, sc->rl_stat_ch);
1654 * Enable interrupts.
1655 */
1656 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1657
1658 /* Set initial TX threshold */
1659 sc->rl_txthresh = RL_TX_THRESH_INIT;
1660
1661 /* Start RX/TX process. */

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1788 register int i;
1789 struct ifnet *ifp;
1790
1791 RL_LOCK(sc);
1792 ifp = &sc->arpcom.ac_if;
1793 ifp->if_timer = 0;
1794
1795 untimeout(rl_tick, sc, sc->rl_stat_ch);
1796 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1797#ifdef DEVICE_POLLING
1798 ether_poll_deregister(ifp);
1799#endif /* DEVICE_POLLING */
1735
1736 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1737 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1738 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1739
1740 /*
1741 * Free the TX list buffers.
1742 */

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1747 bus_dmamap_destroy(sc->rl_tag,
1748 sc->rl_cdata.rl_tx_dmamap[i]);
1749 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1750 sc->rl_cdata.rl_tx_chain[i] = NULL;
1751 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
1752 }
1753 }
1754
1800
1801 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1802 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1803 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1804
1805 /*
1806 * Free the TX list buffers.
1807 */

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1812 bus_dmamap_destroy(sc->rl_tag,
1813 sc->rl_cdata.rl_tx_dmamap[i]);
1814 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1815 sc->rl_cdata.rl_tx_chain[i] = NULL;
1816 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
1817 }
1818 }
1819
1755 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1756 RL_UNLOCK(sc);
1757 return;
1758}
1759
1760/*
1761 * Device suspend routine. Stop the interface and save some PCI
1762 * settings in case the BIOS doesn't restore them properly on
1763 * resume.

--- 74 unchanged lines hidden --- 		1820 RL_UNLOCK(sc);
1821 return;
1822}
1823
1824/*
1825 * Device suspend routine. Stop the interface and save some PCI
1826 * settings in case the BIOS doesn't restore them properly on
1827 * resume.

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