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if_rl.c (131455) if_rl.c (131605)
1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 17 unchanged lines hidden (view full) ---

26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 17 unchanged lines hidden (view full) ---

26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 131455 2004-07-02 12:16:02Z mlaier $");
34__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 131605 2004-07-05 02:46:42Z bms $");
35
36/*
37 * RealTek 8129/8139 PCI NIC driver
38 *
39 * Supports several extremely cheap PCI 10/100 adapters based on
40 * the RealTek chipset. Datasheets can be obtained from
41 * www.realtek.com.tw.
42 *

--- 126 unchanged lines hidden (view full) ---

169 "Compaq HNE-300" },
170 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
171 "LevelOne FPC-0106TX" },
172 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
173 "Edimax EP-4103DL CardBus" },
174 { 0, 0, 0, NULL }
175};
176
35
36/*
37 * RealTek 8129/8139 PCI NIC driver
38 *
39 * Supports several extremely cheap PCI 10/100 adapters based on
40 * the RealTek chipset. Datasheets can be obtained from
41 * www.realtek.com.tw.
42 *

--- 126 unchanged lines hidden (view full) ---

169 "Compaq HNE-300" },
170 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
171 "LevelOne FPC-0106TX" },
172 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
173 "Edimax EP-4103DL CardBus" },
174 { 0, 0, 0, NULL }
175};
176
177static int rl_probe (device_t);
178static int rl_attach (device_t);
179static int rl_detach (device_t);
177static int rl_attach (device_t);
178static int rl_detach (device_t);
180
179static void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int);
180static void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int);
181static void rl_eeprom_putbyte (struct rl_softc *, int);
182static void rl_eeprom_getword (struct rl_softc *, int, uint16_t *);
181static int rl_encap (struct rl_softc *, struct mbuf * );
183static int rl_encap (struct rl_softc *, struct mbuf * );
182
183static void rl_rxeof (struct rl_softc *);
184static void rl_txeof (struct rl_softc *);
185static void rl_intr (void *);
186static void rl_tick (void *);
187static void rl_start (struct ifnet *);
188static int rl_ioctl (struct ifnet *, u_long, caddr_t);
189static void rl_init (void *);
190static void rl_stop (struct rl_softc *);
191static void rl_watchdog (struct ifnet *);
192static int rl_suspend (device_t);
193static int rl_resume (device_t);
194static void rl_shutdown (device_t);
184static int rl_list_tx_init (struct rl_softc *);
195static int rl_ifmedia_upd (struct ifnet *);
196static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
185static int rl_ifmedia_upd (struct ifnet *);
186static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
197
198static void rl_eeprom_putbyte (struct rl_softc *, int);
199static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *);
200static void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int);
187static int rl_ioctl (struct ifnet *, u_long, caddr_t);
188static void rl_intr (void *);
189static void rl_init (void *);
190static void rl_mii_send (struct rl_softc *, uint32_t, int);
201static void rl_mii_sync (struct rl_softc *);
191static void rl_mii_sync (struct rl_softc *);
202static void rl_mii_send (struct rl_softc *, u_int32_t, int);
203static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *);
204static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *);
192static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *);
193static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *);
205
206static int rl_miibus_readreg (device_t, int, int);
194static int rl_miibus_readreg (device_t, int, int);
207static int rl_miibus_writereg (device_t, int, int, int);
208static void rl_miibus_statchg (device_t);
195static void rl_miibus_statchg (device_t);
209
210static void rl_setmulti (struct rl_softc *);
196static int rl_miibus_writereg (device_t, int, int, int);
197static int rl_probe (device_t);
198static void rl_read_eeprom (struct rl_softc *, uint8_t *, int, int, int);
211static void rl_reset (struct rl_softc *);
199static void rl_reset (struct rl_softc *);
212static int rl_list_tx_init (struct rl_softc *);
200static int rl_resume (device_t);
201static void rl_rxeof (struct rl_softc *);
202static void rl_setmulti (struct rl_softc *);
203static void rl_shutdown (device_t);
204static void rl_start (struct ifnet *);
205static void rl_stop (struct rl_softc *);
206static int rl_suspend (device_t);
207static void rl_tick (void *);
208static void rl_txeof (struct rl_softc *);
209static void rl_watchdog (struct ifnet *);
213
210
214static void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int);
215static void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int);
216
217#ifdef RL_USEIOSPACE
218#define RL_RES SYS_RES_IOPORT
219#define RL_RID RL_PCI_LOIO
220#else
221#define RL_RES SYS_RES_MEMORY
222#define RL_RID RL_PCI_LOMEM
223#endif
224

--- 34 unchanged lines hidden (view full) ---

259 CSR_WRITE_1(sc, RL_EECMD, \
260 CSR_READ_1(sc, RL_EECMD) | x)
261
262#define EE_CLR(x) \
263 CSR_WRITE_1(sc, RL_EECMD, \
264 CSR_READ_1(sc, RL_EECMD) & ~x)
265
266static void
211#ifdef RL_USEIOSPACE
212#define RL_RES SYS_RES_IOPORT
213#define RL_RID RL_PCI_LOIO
214#else
215#define RL_RES SYS_RES_MEMORY
216#define RL_RID RL_PCI_LOMEM
217#endif
218

--- 34 unchanged lines hidden (view full) ---

253 CSR_WRITE_1(sc, RL_EECMD, \
254 CSR_READ_1(sc, RL_EECMD) | x)
255
256#define EE_CLR(x) \
257 CSR_WRITE_1(sc, RL_EECMD, \
258 CSR_READ_1(sc, RL_EECMD) & ~x)
259
260static void
267rl_dma_map_rxbuf(arg, segs, nseg, error)
268 void *arg;
269 bus_dma_segment_t *segs;
270 int nseg, error;
261rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
271{
262{
272 struct rl_softc *sc;
263 struct rl_softc *sc = arg;
273
264
274 sc = arg;
275 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
265 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
276
277 return;
278}
279
280static void
266}
267
268static void
281rl_dma_map_txbuf(arg, segs, nseg, error)
282 void *arg;
283 bus_dma_segment_t *segs;
284 int nseg, error;
269rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
285{
270{
286 struct rl_softc *sc;
271 struct rl_softc *sc = arg;
287
272
288 sc = arg;
289 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
273 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
290
291 return;
292}
293
294/*
295 * Send a read command and address to the EEPROM, check for ACK.
296 */
297static void
274}
275
276/*
277 * Send a read command and address to the EEPROM, check for ACK.
278 */
279static void
298rl_eeprom_putbyte(sc, addr)
299 struct rl_softc *sc;
300 int addr;
280rl_eeprom_putbyte(struct rl_softc *sc, int addr)
301{
302 register int d, i;
303
304 d = addr | sc->rl_eecmd_read;
305
306 /*
307 * Feed in each bit and strobe the clock.
308 */

--- 4 unchanged lines hidden (view full) ---

313 EE_CLR(RL_EE_DATAIN);
314 }
315 DELAY(100);
316 EE_SET(RL_EE_CLK);
317 DELAY(150);
318 EE_CLR(RL_EE_CLK);
319 DELAY(100);
320 }
281{
282 register int d, i;
283
284 d = addr | sc->rl_eecmd_read;
285
286 /*
287 * Feed in each bit and strobe the clock.
288 */

--- 4 unchanged lines hidden (view full) ---

293 EE_CLR(RL_EE_DATAIN);
294 }
295 DELAY(100);
296 EE_SET(RL_EE_CLK);
297 DELAY(150);
298 EE_CLR(RL_EE_CLK);
299 DELAY(100);
300 }
321
322 return;
323}
324
325/*
326 * Read a word of data stored in the EEPROM at address 'addr.'
327 */
328static void
301}
302
303/*
304 * Read a word of data stored in the EEPROM at address 'addr.'
305 */
306static void
329rl_eeprom_getword(sc, addr, dest)
330 struct rl_softc *sc;
331 int addr;
332 u_int16_t *dest;
307rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
333{
334 register int i;
308{
309 register int i;
335 u_int16_t word = 0;
310 uint16_t word = 0;
336
337 /* Enter EEPROM access mode. */
338 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
339
340 /*
341 * Send address of word we want to read.
342 */
343 rl_eeprom_putbyte(sc, addr);

--- 11 unchanged lines hidden (view full) ---

355 EE_CLR(RL_EE_CLK);
356 DELAY(100);
357 }
358
359 /* Turn off EEPROM access mode. */
360 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
361
362 *dest = word;
311
312 /* Enter EEPROM access mode. */
313 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
314
315 /*
316 * Send address of word we want to read.
317 */
318 rl_eeprom_putbyte(sc, addr);

--- 11 unchanged lines hidden (view full) ---

330 EE_CLR(RL_EE_CLK);
331 DELAY(100);
332 }
333
334 /* Turn off EEPROM access mode. */
335 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
336
337 *dest = word;
363
364 return;
365}
366
367/*
368 * Read a sequence of words from the EEPROM.
369 */
370static void
338}
339
340/*
341 * Read a sequence of words from the EEPROM.
342 */
343static void
371rl_read_eeprom(sc, dest, off, cnt, swap)
372 struct rl_softc *sc;
373 caddr_t dest;
374 int off;
375 int cnt;
376 int swap;
344rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
377{
378 int i;
345{
346 int i;
379 u_int16_t word = 0, *ptr;
347 uint16_t word = 0, *ptr;
380
381 for (i = 0; i < cnt; i++) {
382 rl_eeprom_getword(sc, off + i, &word);
348
349 for (i = 0; i < cnt; i++) {
350 rl_eeprom_getword(sc, off + i, &word);
383 ptr = (u_int16_t *)(dest + (i * 2));
351 ptr = (uint16_t *)(dest + (i * 2));
384 if (swap)
385 *ptr = ntohs(word);
386 else
387 *ptr = word;
388 }
352 if (swap)
353 *ptr = ntohs(word);
354 else
355 *ptr = word;
356 }
389
390 return;
391}
392
357}
358
393
394/*
395 * MII access routines are provided for the 8129, which
396 * doesn't have a built-in PHY. For the 8139, we fake things
397 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
398 * direct access PHY registers.
399 */
400#define MII_SET(x) \
401 CSR_WRITE_1(sc, RL_MII, \
402 CSR_READ_1(sc, RL_MII) | (x))
403
404#define MII_CLR(x) \
405 CSR_WRITE_1(sc, RL_MII, \
406 CSR_READ_1(sc, RL_MII) & ~(x))
407
408/*
409 * Sync the PHYs by setting data bit and strobing the clock 32 times.
410 */
411static void
359/*
360 * MII access routines are provided for the 8129, which
361 * doesn't have a built-in PHY. For the 8139, we fake things
362 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
363 * direct access PHY registers.
364 */
365#define MII_SET(x) \
366 CSR_WRITE_1(sc, RL_MII, \
367 CSR_READ_1(sc, RL_MII) | (x))
368
369#define MII_CLR(x) \
370 CSR_WRITE_1(sc, RL_MII, \
371 CSR_READ_1(sc, RL_MII) & ~(x))
372
373/*
374 * Sync the PHYs by setting data bit and strobing the clock 32 times.
375 */
376static void
412rl_mii_sync(sc)
413 struct rl_softc *sc;
377rl_mii_sync(struct rl_softc *sc)
414{
415 register int i;
416
417 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
418
419 for (i = 0; i < 32; i++) {
420 MII_SET(RL_MII_CLK);
421 DELAY(1);
422 MII_CLR(RL_MII_CLK);
423 DELAY(1);
424 }
378{
379 register int i;
380
381 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
382
383 for (i = 0; i < 32; i++) {
384 MII_SET(RL_MII_CLK);
385 DELAY(1);
386 MII_CLR(RL_MII_CLK);
387 DELAY(1);
388 }
425
426 return;
427}
428
429/*
430 * Clock a series of bits through the MII.
431 */
432static void
389}
390
391/*
392 * Clock a series of bits through the MII.
393 */
394static void
433rl_mii_send(sc, bits, cnt)
434 struct rl_softc *sc;
435 u_int32_t bits;
436 int cnt;
395rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
437{
438 int i;
439
440 MII_CLR(RL_MII_CLK);
441
442 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
443 if (bits & i) {
444 MII_SET(RL_MII_DATAOUT);

--- 6 unchanged lines hidden (view full) ---

451 MII_SET(RL_MII_CLK);
452 }
453}
454
455/*
456 * Read an PHY register through the MII.
457 */
458static int
396{
397 int i;
398
399 MII_CLR(RL_MII_CLK);
400
401 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
402 if (bits & i) {
403 MII_SET(RL_MII_DATAOUT);

--- 6 unchanged lines hidden (view full) ---

410 MII_SET(RL_MII_CLK);
411 }
412}
413
414/*
415 * Read an PHY register through the MII.
416 */
417static int
459rl_mii_readreg(sc, frame)
460 struct rl_softc *sc;
461 struct rl_mii_frame *frame;
462
418rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
463{
464 int i, ack;
465
466 RL_LOCK(sc);
467
419{
420 int i, ack;
421
422 RL_LOCK(sc);
423
468 /*
469 * Set up frame for RX.
470 */
424 /* Set up frame for RX. */
471 frame->mii_stdelim = RL_MII_STARTDELIM;
472 frame->mii_opcode = RL_MII_READOP;
473 frame->mii_turnaround = 0;
474 frame->mii_data = 0;
475
476 CSR_WRITE_2(sc, RL_MII, 0);
477
425 frame->mii_stdelim = RL_MII_STARTDELIM;
426 frame->mii_opcode = RL_MII_READOP;
427 frame->mii_turnaround = 0;
428 frame->mii_data = 0;
429
430 CSR_WRITE_2(sc, RL_MII, 0);
431
478 /*
479 * Turn on data xmit.
480 */
432 /* Turn on data xmit. */
481 MII_SET(RL_MII_DIR);
482
483 rl_mii_sync(sc);
484
433 MII_SET(RL_MII_DIR);
434
435 rl_mii_sync(sc);
436
485 /*
486 * Send command/address info.
487 */
437 /* Send command/address info. */
488 rl_mii_send(sc, frame->mii_stdelim, 2);
489 rl_mii_send(sc, frame->mii_opcode, 2);
490 rl_mii_send(sc, frame->mii_phyaddr, 5);
491 rl_mii_send(sc, frame->mii_regaddr, 5);
492
493 /* Idle bit */
494 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
495 DELAY(1);

--- 32 unchanged lines hidden (view full) ---

528 frame->mii_data |= i;
529 DELAY(1);
530 }
531 MII_SET(RL_MII_CLK);
532 DELAY(1);
533 }
534
535fail:
438 rl_mii_send(sc, frame->mii_stdelim, 2);
439 rl_mii_send(sc, frame->mii_opcode, 2);
440 rl_mii_send(sc, frame->mii_phyaddr, 5);
441 rl_mii_send(sc, frame->mii_regaddr, 5);
442
443 /* Idle bit */
444 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
445 DELAY(1);

--- 32 unchanged lines hidden (view full) ---

478 frame->mii_data |= i;
479 DELAY(1);
480 }
481 MII_SET(RL_MII_CLK);
482 DELAY(1);
483 }
484
485fail:
536
537 MII_CLR(RL_MII_CLK);
538 DELAY(1);
539 MII_SET(RL_MII_CLK);
540 DELAY(1);
541
542 RL_UNLOCK(sc);
543
486 MII_CLR(RL_MII_CLK);
487 DELAY(1);
488 MII_SET(RL_MII_CLK);
489 DELAY(1);
490
491 RL_UNLOCK(sc);
492
544 if (ack)
545 return(1);
546 return(0);
493 return (ack ? 1 : 0);
547}
548
549/*
550 * Write to a PHY register through the MII.
551 */
552static int
494}
495
496/*
497 * Write to a PHY register through the MII.
498 */
499static int
553rl_mii_writereg(sc, frame)
554 struct rl_softc *sc;
555 struct rl_mii_frame *frame;
556
500rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
557{
501{
502
558 RL_LOCK(sc);
559
503 RL_LOCK(sc);
504
560 /*
561 * Set up frame for TX.
562 */
563
505 /* Set up frame for TX. */
564 frame->mii_stdelim = RL_MII_STARTDELIM;
565 frame->mii_opcode = RL_MII_WRITEOP;
566 frame->mii_turnaround = RL_MII_TURNAROUND;
567
506 frame->mii_stdelim = RL_MII_STARTDELIM;
507 frame->mii_opcode = RL_MII_WRITEOP;
508 frame->mii_turnaround = RL_MII_TURNAROUND;
509
568 /*
569 * Turn on data output.
570 */
510 /* Turn on data output. */
571 MII_SET(RL_MII_DIR);
572
573 rl_mii_sync(sc);
574
575 rl_mii_send(sc, frame->mii_stdelim, 2);
576 rl_mii_send(sc, frame->mii_opcode, 2);
577 rl_mii_send(sc, frame->mii_phyaddr, 5);
578 rl_mii_send(sc, frame->mii_regaddr, 5);
579 rl_mii_send(sc, frame->mii_turnaround, 2);
580 rl_mii_send(sc, frame->mii_data, 16);
581
582 /* Idle bit. */
583 MII_SET(RL_MII_CLK);
584 DELAY(1);
585 MII_CLR(RL_MII_CLK);
586 DELAY(1);
587
511 MII_SET(RL_MII_DIR);
512
513 rl_mii_sync(sc);
514
515 rl_mii_send(sc, frame->mii_stdelim, 2);
516 rl_mii_send(sc, frame->mii_opcode, 2);
517 rl_mii_send(sc, frame->mii_phyaddr, 5);
518 rl_mii_send(sc, frame->mii_regaddr, 5);
519 rl_mii_send(sc, frame->mii_turnaround, 2);
520 rl_mii_send(sc, frame->mii_data, 16);
521
522 /* Idle bit. */
523 MII_SET(RL_MII_CLK);
524 DELAY(1);
525 MII_CLR(RL_MII_CLK);
526 DELAY(1);
527
588 /*
589 * Turn off xmit.
590 */
528 /* Turn off xmit. */
591 MII_CLR(RL_MII_DIR);
592
593 RL_UNLOCK(sc);
594
529 MII_CLR(RL_MII_DIR);
530
531 RL_UNLOCK(sc);
532
595 return(0);
533 return (0);
596}
597
598static int
534}
535
536static int
599rl_miibus_readreg(dev, phy, reg)
600 device_t dev;
601 int phy, reg;
537rl_miibus_readreg(device_t dev, int phy, int reg)
602{
603 struct rl_softc *sc;
604 struct rl_mii_frame frame;
538{
539 struct rl_softc *sc;
540 struct rl_mii_frame frame;
605 u_int16_t rval = 0;
606 u_int16_t rl8139_reg = 0;
541 uint16_t rval = 0;
542 uint16_t rl8139_reg = 0;
607
608 sc = device_get_softc(dev);
609 RL_LOCK(sc);
610
611 if (sc->rl_type == RL_8139) {
612 /* Pretend the internal PHY is only at address 0 */
613 if (phy) {
614 RL_UNLOCK(sc);
543
544 sc = device_get_softc(dev);
545 RL_LOCK(sc);
546
547 if (sc->rl_type == RL_8139) {
548 /* Pretend the internal PHY is only at address 0 */
549 if (phy) {
550 RL_UNLOCK(sc);
615 return(0);
551 return (0);
616 }
552 }
617 switch(reg) {
553 switch (reg) {
618 case MII_BMCR:
619 rl8139_reg = RL_BMCR;
620 break;
621 case MII_BMSR:
622 rl8139_reg = RL_BMSR;
623 break;
624 case MII_ANAR:
625 rl8139_reg = RL_ANAR;
626 break;
627 case MII_ANER:
628 rl8139_reg = RL_ANER;
629 break;
630 case MII_ANLPAR:
631 rl8139_reg = RL_LPAR;
632 break;
633 case MII_PHYIDR1:
634 case MII_PHYIDR2:
635 RL_UNLOCK(sc);
554 case MII_BMCR:
555 rl8139_reg = RL_BMCR;
556 break;
557 case MII_BMSR:
558 rl8139_reg = RL_BMSR;
559 break;
560 case MII_ANAR:
561 rl8139_reg = RL_ANAR;
562 break;
563 case MII_ANER:
564 rl8139_reg = RL_ANER;
565 break;
566 case MII_ANLPAR:
567 rl8139_reg = RL_LPAR;
568 break;
569 case MII_PHYIDR1:
570 case MII_PHYIDR2:
571 RL_UNLOCK(sc);
636 return(0);
572 return (0);
637 /*
638 * Allow the rlphy driver to read the media status
639 * register. If we have a link partner which does not
640 * support NWAY, this is the register which will tell
641 * us the results of parallel detection.
642 */
643 case RL_MEDIASTAT:
644 rval = CSR_READ_1(sc, RL_MEDIASTAT);
645 RL_UNLOCK(sc);
573 /*
574 * Allow the rlphy driver to read the media status
575 * register. If we have a link partner which does not
576 * support NWAY, this is the register which will tell
577 * us the results of parallel detection.
578 */
579 case RL_MEDIASTAT:
580 rval = CSR_READ_1(sc, RL_MEDIASTAT);
581 RL_UNLOCK(sc);
646 return(rval);
582 return (rval);
647 default:
583 default:
648 printf("rl%d: bad phy register\n", sc->rl_unit);
584 if_printf(&sc->arpcom.ac_if, "bad phy register\n");
649 RL_UNLOCK(sc);
585 RL_UNLOCK(sc);
650 return(0);
586 return (0);
651 }
652 rval = CSR_READ_2(sc, rl8139_reg);
653 RL_UNLOCK(sc);
587 }
588 rval = CSR_READ_2(sc, rl8139_reg);
589 RL_UNLOCK(sc);
654 return(rval);
590 return (rval);
655 }
656
657 bzero((char *)&frame, sizeof(frame));
591 }
592
593 bzero((char *)&frame, sizeof(frame));
658
659 frame.mii_phyaddr = phy;
660 frame.mii_regaddr = reg;
661 rl_mii_readreg(sc, &frame);
594 frame.mii_phyaddr = phy;
595 frame.mii_regaddr = reg;
596 rl_mii_readreg(sc, &frame);
597
662 RL_UNLOCK(sc);
663
598 RL_UNLOCK(sc);
599
664 return(frame.mii_data);
600 return (frame.mii_data);
665}
666
667static int
601}
602
603static int
668rl_miibus_writereg(dev, phy, reg, data)
669 device_t dev;
670 int phy, reg, data;
604rl_miibus_writereg(device_t dev, int phy, int reg, int data)
671{
672 struct rl_softc *sc;
673 struct rl_mii_frame frame;
605{
606 struct rl_softc *sc;
607 struct rl_mii_frame frame;
674 u_int16_t rl8139_reg = 0;
608 uint16_t rl8139_reg = 0;
675
676 sc = device_get_softc(dev);
677 RL_LOCK(sc);
678
679 if (sc->rl_type == RL_8139) {
680 /* Pretend the internal PHY is only at address 0 */
681 if (phy) {
682 RL_UNLOCK(sc);
609
610 sc = device_get_softc(dev);
611 RL_LOCK(sc);
612
613 if (sc->rl_type == RL_8139) {
614 /* Pretend the internal PHY is only at address 0 */
615 if (phy) {
616 RL_UNLOCK(sc);
683 return(0);
617 return (0);
684 }
618 }
685 switch(reg) {
619 switch (reg) {
686 case MII_BMCR:
687 rl8139_reg = RL_BMCR;
688 break;
689 case MII_BMSR:
690 rl8139_reg = RL_BMSR;
691 break;
692 case MII_ANAR:
693 rl8139_reg = RL_ANAR;
694 break;
695 case MII_ANER:
696 rl8139_reg = RL_ANER;
697 break;
698 case MII_ANLPAR:
699 rl8139_reg = RL_LPAR;
700 break;
701 case MII_PHYIDR1:
702 case MII_PHYIDR2:
703 RL_UNLOCK(sc);
620 case MII_BMCR:
621 rl8139_reg = RL_BMCR;
622 break;
623 case MII_BMSR:
624 rl8139_reg = RL_BMSR;
625 break;
626 case MII_ANAR:
627 rl8139_reg = RL_ANAR;
628 break;
629 case MII_ANER:
630 rl8139_reg = RL_ANER;
631 break;
632 case MII_ANLPAR:
633 rl8139_reg = RL_LPAR;
634 break;
635 case MII_PHYIDR1:
636 case MII_PHYIDR2:
637 RL_UNLOCK(sc);
704 return(0);
638 return (0);
705 break;
706 default:
639 break;
640 default:
707 printf("rl%d: bad phy register\n", sc->rl_unit);
641 if_printf(&sc->arpcom.ac_if, "bad phy register\n");
708 RL_UNLOCK(sc);
642 RL_UNLOCK(sc);
709 return(0);
643 return (0);
710 }
711 CSR_WRITE_2(sc, rl8139_reg, data);
712 RL_UNLOCK(sc);
644 }
645 CSR_WRITE_2(sc, rl8139_reg, data);
646 RL_UNLOCK(sc);
713 return(0);
647 return (0);
714 }
715
716 bzero((char *)&frame, sizeof(frame));
648 }
649
650 bzero((char *)&frame, sizeof(frame));
717
718 frame.mii_phyaddr = phy;
719 frame.mii_regaddr = reg;
720 frame.mii_data = data;
651 frame.mii_phyaddr = phy;
652 frame.mii_regaddr = reg;
653 frame.mii_data = data;
721
722 rl_mii_writereg(sc, &frame);
723
724 RL_UNLOCK(sc);
654 rl_mii_writereg(sc, &frame);
655
656 RL_UNLOCK(sc);
725 return(0);
657
658 return (0);
726}
727
728static void
659}
660
661static void
729rl_miibus_statchg(dev)
730 device_t dev;
662rl_miibus_statchg(device_t dev)
731{
663{
732 return;
733}
734
735/*
736 * Program the 64-bit multicast hash filter.
737 */
738static void
664}
665
666/*
667 * Program the 64-bit multicast hash filter.
668 */
669static void
739rl_setmulti(sc)
740 struct rl_softc *sc;
670rl_setmulti(struct rl_softc *sc)
741{
671{
742 struct ifnet *ifp;
672 struct ifnet *ifp = &sc->arpcom.ac_if;
743 int h = 0;
673 int h = 0;
744 u_int32_t hashes[2] = { 0, 0 };
674 uint32_t hashes[2] = { 0, 0 };
745 struct ifmultiaddr *ifma;
675 struct ifmultiaddr *ifma;
746 u_int32_t rxfilt;
676 uint32_t rxfilt;
747 int mcnt = 0;
748
677 int mcnt = 0;
678
749 ifp = &sc->arpcom.ac_if;
750
751 rxfilt = CSR_READ_4(sc, RL_RXCFG);
752
753 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
754 rxfilt |= RL_RXCFG_RX_MULTI;
755 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
756 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
757 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
758 return;

--- 19 unchanged lines hidden (view full) ---

778 if (mcnt)
779 rxfilt |= RL_RXCFG_RX_MULTI;
780 else
781 rxfilt &= ~RL_RXCFG_RX_MULTI;
782
783 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
784 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
785 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
679 rxfilt = CSR_READ_4(sc, RL_RXCFG);
680
681 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
682 rxfilt |= RL_RXCFG_RX_MULTI;
683 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
684 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
685 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
686 return;

--- 19 unchanged lines hidden (view full) ---

706 if (mcnt)
707 rxfilt |= RL_RXCFG_RX_MULTI;
708 else
709 rxfilt &= ~RL_RXCFG_RX_MULTI;
710
711 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
712 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
713 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
786
787 return;
788}
789
790static void
714}
715
716static void
791rl_reset(sc)
792 struct rl_softc *sc;
717rl_reset(struct rl_softc *sc)
793{
794 register int i;
795
796 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
797
798 for (i = 0; i < RL_TIMEOUT; i++) {
799 DELAY(10);
800 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
801 break;
802 }
803 if (i == RL_TIMEOUT)
718{
719 register int i;
720
721 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
722
723 for (i = 0; i < RL_TIMEOUT; i++) {
724 DELAY(10);
725 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
726 break;
727 }
728 if (i == RL_TIMEOUT)
804 printf("rl%d: reset never completed!\n", sc->rl_unit);
805
806 return;
729 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
807}
808
809/*
810 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
811 * IDs against our list and return a device name if we find a match.
812 */
813static int
730}
731
732/*
733 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
734 * IDs against our list and return a device name if we find a match.
735 */
736static int
814rl_probe(dev)
815 device_t dev;
737rl_probe(device_t dev)
816{
738{
817 struct rl_type *t;
818 struct rl_softc *sc;
739 struct rl_softc *sc;
740 struct rl_type *t = rl_devs;
819 int rid;
741 int rid;
820 u_int32_t hwrev;
742 uint32_t hwrev;
821
743
822 t = rl_devs;
823 sc = device_get_softc(dev);
824
744 sc = device_get_softc(dev);
745
825 while(t->rl_name != NULL) {
746 while (t->rl_name != NULL) {
826 if ((pci_get_vendor(dev) == t->rl_vid) &&
827 (pci_get_device(dev) == t->rl_did)) {
747 if ((pci_get_vendor(dev) == t->rl_vid) &&
748 (pci_get_device(dev) == t->rl_did)) {
828
829 /*
830 * Temporarily map the I/O space
831 * so we can read the chip ID register.
832 */
833 rid = RL_RID;
834 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
835 RF_ACTIVE);
836 if (sc->rl_res == NULL) {
837 device_printf(dev,
838 "couldn't map ports/memory\n");
749 /*
750 * Temporarily map the I/O space
751 * so we can read the chip ID register.
752 */
753 rid = RL_RID;
754 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
755 RF_ACTIVE);
756 if (sc->rl_res == NULL) {
757 device_printf(dev,
758 "couldn't map ports/memory\n");
839 return(ENXIO);
759 return (ENXIO);
840 }
841 sc->rl_btag = rman_get_bustag(sc->rl_res);
842 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
760 }
761 sc->rl_btag = rman_get_bustag(sc->rl_res);
762 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
763
843 mtx_init(&sc->rl_mtx,
844 device_get_nameunit(dev),
845 MTX_NETWORK_LOCK, MTX_DEF);
764 mtx_init(&sc->rl_mtx,
765 device_get_nameunit(dev),
766 MTX_NETWORK_LOCK, MTX_DEF);
846 RL_LOCK(sc);
767 RL_LOCK(sc);
768
847 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
848 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
769 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
770 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
771
849 RL_UNLOCK(sc);
850 mtx_destroy(&sc->rl_mtx);
851
852 /* Don't attach to 8139C+ or 8169/8110 chips. */
853 if (hwrev == RL_HWREV_8139CPLUS ||
854 (hwrev == RL_HWREV_8169 &&
855 t->rl_did == RT_DEVICEID_8169) ||
856 hwrev == RL_HWREV_8169S ||
857 hwrev == RL_HWREV_8110S) {
858 t++;
859 continue;
860 }
861
862 device_set_desc(dev, t->rl_name);
772 RL_UNLOCK(sc);
773 mtx_destroy(&sc->rl_mtx);
774
775 /* Don't attach to 8139C+ or 8169/8110 chips. */
776 if (hwrev == RL_HWREV_8139CPLUS ||
777 (hwrev == RL_HWREV_8169 &&
778 t->rl_did == RT_DEVICEID_8169) ||
779 hwrev == RL_HWREV_8169S ||
780 hwrev == RL_HWREV_8110S) {
781 t++;
782 continue;
783 }
784
785 device_set_desc(dev, t->rl_name);
863 return(0);
786 return (0);
864 }
865 t++;
866 }
867
787 }
788 t++;
789 }
790
868 return(ENXIO);
791 return (ENXIO);
869}
870
871/*
872 * Attach the interface. Allocate softc structures, do ifmedia
873 * setup and ethernet/BPF attach.
874 */
875static int
792}
793
794/*
795 * Attach the interface. Allocate softc structures, do ifmedia
796 * setup and ethernet/BPF attach.
797 */
798static int
876rl_attach(dev)
877 device_t dev;
799rl_attach(device_t dev)
878{
800{
879 u_char eaddr[ETHER_ADDR_LEN];
880 u_int16_t as[3];
881 struct rl_softc *sc;
801 uint8_t eaddr[ETHER_ADDR_LEN];
802 uint16_t as[3];
882 struct ifnet *ifp;
803 struct ifnet *ifp;
883 u_int16_t rl_did = 0;
804 struct rl_softc *sc;
884 struct rl_type *t;
805 struct rl_type *t;
885 int unit, error = 0, rid, i;
806 int error = 0, i, rid;
807 int unit;
808 uint16_t rl_did = 0;
886
887 sc = device_get_softc(dev);
888 unit = device_get_unit(dev);
889
890 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
891 MTX_DEF | MTX_RECURSE);
809
810 sc = device_get_softc(dev);
811 unit = device_get_unit(dev);
812
813 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
814 MTX_DEF | MTX_RECURSE);
892 /*
893 * Map control/status registers.
894 */
815
895 pci_enable_busmaster(dev);
896
816 pci_enable_busmaster(dev);
817
818 /* Map control/status registers. */
897 rid = RL_RID;
898 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
899
900 if (sc->rl_res == NULL) {
819 rid = RL_RID;
820 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
821
822 if (sc->rl_res == NULL) {
901 printf ("rl%d: couldn't map ports/memory\n", unit);
823 device_printf(dev, "couldn't map ports/memory\n");
902 error = ENXIO;
903 goto fail;
904 }
905
906#ifdef notdef
824 error = ENXIO;
825 goto fail;
826 }
827
828#ifdef notdef
907 /* Detect the Realtek 8139B. For some reason, this chip is very
829 /*
830 * Detect the Realtek 8139B. For some reason, this chip is very
908 * unstable when left to autoselect the media
909 * The best workaround is to set the device to the required
910 * media type or to set it to the 10 Meg speed.
911 */
831 * unstable when left to autoselect the media
832 * The best workaround is to set the device to the required
833 * media type or to set it to the 10 Meg speed.
834 */
912
913 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) {
914 printf("rl%d: Realtek 8139B detected. Warning, "
915 "this may be unstable in autoselect mode\n", unit);
916 }
835 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
836 device_printf(dev,
837"Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
917#endif
918
919 sc->rl_btag = rman_get_bustag(sc->rl_res);
920 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
921
922 /* Allocate interrupt */
923 rid = 0;
924 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
925 RF_SHAREABLE | RF_ACTIVE);
926
927 if (sc->rl_irq == NULL) {
838#endif
839
840 sc->rl_btag = rman_get_bustag(sc->rl_res);
841 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
842
843 /* Allocate interrupt */
844 rid = 0;
845 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
846 RF_SHAREABLE | RF_ACTIVE);
847
848 if (sc->rl_irq == NULL) {
928 printf("rl%d: couldn't map interrupt\n", unit);
849 device_printf(dev, "couldn't map interrupt\n");
929 error = ENXIO;
930 goto fail;
931 }
932
933 /* Reset the adapter. */
934 rl_reset(sc);
935 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
850 error = ENXIO;
851 goto fail;
852 }
853
854 /* Reset the adapter. */
855 rl_reset(sc);
856 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
936 rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0);
857 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
937 if (rl_did != 0x8129)
938 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
939
940 /*
941 * Get station address from the EEPROM.
942 */
858 if (rl_did != 0x8129)
859 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
860
861 /*
862 * Get station address from the EEPROM.
863 */
943 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0);
864 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
944 for (i = 0; i < 3; i++) {
945 eaddr[(i * 2) + 0] = as[i] & 0xff;
946 eaddr[(i * 2) + 1] = as[i] >> 8;
947 }
948
949 sc->rl_unit = unit;
950 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
951
952 /*
953 * Now read the exact device type from the EEPROM to find
954 * out if it's an 8129 or 8139.
955 */
865 for (i = 0; i < 3; i++) {
866 eaddr[(i * 2) + 0] = as[i] & 0xff;
867 eaddr[(i * 2) + 1] = as[i] >> 8;
868 }
869
870 sc->rl_unit = unit;
871 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
872
873 /*
874 * Now read the exact device type from the EEPROM to find
875 * out if it's an 8129 or 8139.
876 */
956 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
877 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
957
958 t = rl_devs;
959 sc->rl_type = 0;
960 while(t->rl_name != NULL) {
961 if (rl_did == t->rl_did) {
962 sc->rl_type = t->rl_basetype;
963 break;
964 }
965 t++;
966 }
967
968 if (sc->rl_type == 0) {
878
879 t = rl_devs;
880 sc->rl_type = 0;
881 while(t->rl_name != NULL) {
882 if (rl_did == t->rl_did) {
883 sc->rl_type = t->rl_basetype;
884 break;
885 }
886 t++;
887 }
888
889 if (sc->rl_type == 0) {
969 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
890 device_printf(dev, "unknown device ID: %x\n", rl_did);
970 error = ENXIO;
971 goto fail;
972 }
973
974 /*
975 * Allocate the parent bus DMA tag appropriate for PCI.
976 */
977#define RL_NSEG_NEW 32

--- 30 unchanged lines hidden (view full) ---

1008
1009 /*
1010 * Now allocate a chunk of DMA-able memory based on the
1011 * tag we just created.
1012 */
1013 error = bus_dmamem_alloc(sc->rl_tag,
1014 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1015 &sc->rl_cdata.rl_rx_dmamap);
891 error = ENXIO;
892 goto fail;
893 }
894
895 /*
896 * Allocate the parent bus DMA tag appropriate for PCI.
897 */
898#define RL_NSEG_NEW 32

--- 30 unchanged lines hidden (view full) ---

929
930 /*
931 * Now allocate a chunk of DMA-able memory based on the
932 * tag we just created.
933 */
934 error = bus_dmamem_alloc(sc->rl_tag,
935 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
936 &sc->rl_cdata.rl_rx_dmamap);
1016
1017 if (error) {
937 if (error) {
1018 printf("rl%d: no memory for list buffers!\n", unit);
938 device_printf(dev, "no memory for list buffers!\n");
1019 bus_dma_tag_destroy(sc->rl_tag);
1020 sc->rl_tag = NULL;
1021 goto fail;
1022 }
1023
1024 /* Leave a few bytes before the start of the RX ring buffer. */
1025 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
939 bus_dma_tag_destroy(sc->rl_tag);
940 sc->rl_tag = NULL;
941 goto fail;
942 }
943
944 /* Leave a few bytes before the start of the RX ring buffer. */
945 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1026 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
946 sc->rl_cdata.rl_rx_buf += sizeof(uint64_t);
1027
1028 /* Do MII setup */
1029 if (mii_phy_probe(dev, &sc->rl_miibus,
1030 rl_ifmedia_upd, rl_ifmedia_sts)) {
947
948 /* Do MII setup */
949 if (mii_phy_probe(dev, &sc->rl_miibus,
950 rl_ifmedia_upd, rl_ifmedia_sts)) {
1031 printf("rl%d: MII without any phy!\n", sc->rl_unit);
951 device_printf(dev, "MII without any phy!\n");
1032 error = ENXIO;
1033 goto fail;
1034 }
1035
1036 ifp = &sc->arpcom.ac_if;
1037 ifp->if_softc = sc;
1038 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1039 ifp->if_mtu = ETHERMTU;

--- 6 unchanged lines hidden (view full) ---

1046 ifp->if_capabilities = IFCAP_VLAN_MTU;
1047#ifdef DEVICE_POLLING
1048 ifp->if_capabilities |= IFCAP_POLLING;
1049#endif
1050 ifp->if_capenable = ifp->if_capabilities;
1051 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
1052 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
1053 IFQ_SET_READY(&ifp->if_snd);
952 error = ENXIO;
953 goto fail;
954 }
955
956 ifp = &sc->arpcom.ac_if;
957 ifp->if_softc = sc;
958 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
959 ifp->if_mtu = ETHERMTU;

--- 6 unchanged lines hidden (view full) ---

966 ifp->if_capabilities = IFCAP_VLAN_MTU;
967#ifdef DEVICE_POLLING
968 ifp->if_capabilities |= IFCAP_POLLING;
969#endif
970 ifp->if_capenable = ifp->if_capabilities;
971 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
972 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
973 IFQ_SET_READY(&ifp->if_snd);
1054
974
1055 callout_handle_init(&sc->rl_stat_ch);
1056
1057 /*
1058 * Call MI attach routine.
1059 */
1060 ether_ifattach(ifp, eaddr);
1061
1062 /* Hook interrupt last to avoid having to lock softc */
1063 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET,
1064 rl_intr, sc, &sc->rl_intrhand);
1065
1066 if (error) {
975 callout_handle_init(&sc->rl_stat_ch);
976
977 /*
978 * Call MI attach routine.
979 */
980 ether_ifattach(ifp, eaddr);
981
982 /* Hook interrupt last to avoid having to lock softc */
983 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET,
984 rl_intr, sc, &sc->rl_intrhand);
985
986 if (error) {
1067 printf("rl%d: couldn't set up irq\n", unit);
987 if_printf(ifp, "couldn't set up irq\n");
1068 ether_ifdetach(ifp);
1069 goto fail;
1070 }
1071
1072fail:
1073 if (error)
1074 rl_detach(dev);
1075
1076 return (error);
1077}
1078
1079/*
1080 * Shutdown hardware and free up resources. This can be called any
1081 * time after the mutex has been initialized. It is called in both
1082 * the error case in attach and the normal detach case so it needs
1083 * to be careful about only freeing resources that have actually been
1084 * allocated.
1085 */
1086static int
988 ether_ifdetach(ifp);
989 goto fail;
990 }
991
992fail:
993 if (error)
994 rl_detach(dev);
995
996 return (error);
997}
998
999/*
1000 * Shutdown hardware and free up resources. This can be called any
1001 * time after the mutex has been initialized. It is called in both
1002 * the error case in attach and the normal detach case so it needs
1003 * to be careful about only freeing resources that have actually been
1004 * allocated.
1005 */
1006static int
1087rl_detach(dev)
1088 device_t dev;
1007rl_detach(device_t dev)
1089{
1090 struct rl_softc *sc;
1091 struct ifnet *ifp;
1092
1093 sc = device_get_softc(dev);
1008{
1009 struct rl_softc *sc;
1010 struct ifnet *ifp;
1011
1012 sc = device_get_softc(dev);
1013 ifp = &sc->arpcom.ac_if;
1014
1094 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
1095 RL_LOCK(sc);
1015 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
1016 RL_LOCK(sc);
1096 ifp = &sc->arpcom.ac_if;
1097
1098 /* These should only be active if attach succeeded */
1099 if (device_is_attached(dev)) {
1100 rl_stop(sc);
1101 ether_ifdetach(ifp);
1102 }
1103 if (sc->rl_miibus)
1104 device_delete_child(dev, sc->rl_miibus);

--- 13 unchanged lines hidden (view full) ---

1118 bus_dma_tag_destroy(sc->rl_tag);
1119 }
1120 if (sc->rl_parent_tag)
1121 bus_dma_tag_destroy(sc->rl_parent_tag);
1122
1123 RL_UNLOCK(sc);
1124 mtx_destroy(&sc->rl_mtx);
1125
1017
1018 /* These should only be active if attach succeeded */
1019 if (device_is_attached(dev)) {
1020 rl_stop(sc);
1021 ether_ifdetach(ifp);
1022 }
1023 if (sc->rl_miibus)
1024 device_delete_child(dev, sc->rl_miibus);

--- 13 unchanged lines hidden (view full) ---

1038 bus_dma_tag_destroy(sc->rl_tag);
1039 }
1040 if (sc->rl_parent_tag)
1041 bus_dma_tag_destroy(sc->rl_parent_tag);
1042
1043 RL_UNLOCK(sc);
1044 mtx_destroy(&sc->rl_mtx);
1045
1126 return(0);
1046 return (0);
1127}
1128
1129/*
1130 * Initialize the transmit descriptors.
1131 */
1132static int
1047}
1048
1049/*
1050 * Initialize the transmit descriptors.
1051 */
1052static int
1133rl_list_tx_init(sc)
1134 struct rl_softc *sc;
1053rl_list_tx_init(struct rl_softc *sc)
1135{
1136 struct rl_chain_data *cd;
1137 int i;
1138
1139 cd = &sc->rl_cdata;
1140 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1141 cd->rl_tx_chain[i] = NULL;
1142 CSR_WRITE_4(sc,
1054{
1055 struct rl_chain_data *cd;
1056 int i;
1057
1058 cd = &sc->rl_cdata;
1059 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1060 cd->rl_tx_chain[i] = NULL;
1061 CSR_WRITE_4(sc,
1143 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000);
1062 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1144 }
1145
1146 sc->rl_cdata.cur_tx = 0;
1147 sc->rl_cdata.last_tx = 0;
1148
1063 }
1064
1065 sc->rl_cdata.cur_tx = 0;
1066 sc->rl_cdata.last_tx = 0;
1067
1149 return(0);
1068 return (0);
1150}
1151
1152/*
1153 * A frame has been uploaded: pass the resulting mbuf chain up to
1154 * the higher level protocols.
1155 *
1156 * You know there's something wrong with a PCI bus-master chip design
1157 * when you have to use m_devget().

--- 8 unchanged lines hidden (view full) ---

1166 * first 16 bits of the status word; the lower 15 bits correspond with
1167 * the 'rx status register' mentioned in the datasheet.
1168 *
1169 * Note: to make the Alpha happy, the frame payload needs to be aligned
1170 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1171 * as the offset argument to m_devget().
1172 */
1173static void
1069}
1070
1071/*
1072 * A frame has been uploaded: pass the resulting mbuf chain up to
1073 * the higher level protocols.
1074 *
1075 * You know there's something wrong with a PCI bus-master chip design
1076 * when you have to use m_devget().

--- 8 unchanged lines hidden (view full) ---

1085 * first 16 bits of the status word; the lower 15 bits correspond with
1086 * the 'rx status register' mentioned in the datasheet.
1087 *
1088 * Note: to make the Alpha happy, the frame payload needs to be aligned
1089 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1090 * as the offset argument to m_devget().
1091 */
1092static void
1174rl_rxeof(sc)
1175 struct rl_softc *sc;
1093rl_rxeof(struct rl_softc *sc)
1176{
1177 struct mbuf *m;
1094{
1095 struct mbuf *m;
1178 struct ifnet *ifp;
1096 struct ifnet *ifp = &sc->arpcom.ac_if;
1097 uint8_t *rxbufpos;
1179 int total_len = 0;
1098 int total_len = 0;
1180 u_int32_t rxstat;
1181 caddr_t rxbufpos;
1182 int wrap = 0;
1099 int wrap = 0;
1183 u_int16_t cur_rx;
1184 u_int16_t limit;
1185 u_int16_t rx_bytes = 0, max_bytes;
1100 uint32_t rxstat;
1101 uint16_t cur_rx;
1102 uint16_t limit;
1103 uint16_t max_bytes, rx_bytes = 0;
1186
1187 RL_LOCK_ASSERT(sc);
1188
1104
1105 RL_LOCK_ASSERT(sc);
1106
1189 ifp = &sc->arpcom.ac_if;
1190
1191 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1192 BUS_DMASYNC_POSTREAD);
1193
1194 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1195
1196 /* Do not try to read past this point. */
1197 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1198

--- 6 unchanged lines hidden (view full) ---

1205#ifdef DEVICE_POLLING
1206 if (ifp->if_flags & IFF_POLLING) {
1207 if (sc->rxcycles <= 0)
1208 break;
1209 sc->rxcycles--;
1210 }
1211#endif /* DEVICE_POLLING */
1212 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1107 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1108 BUS_DMASYNC_POSTREAD);
1109
1110 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1111
1112 /* Do not try to read past this point. */
1113 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1114

--- 6 unchanged lines hidden (view full) ---

1121#ifdef DEVICE_POLLING
1122 if (ifp->if_flags & IFF_POLLING) {
1123 if (sc->rxcycles <= 0)
1124 break;
1125 sc->rxcycles--;
1126 }
1127#endif /* DEVICE_POLLING */
1128 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1213 rxstat = le32toh(*(u_int32_t *)rxbufpos);
1129 rxstat = le32toh(*(uint32_t *)rxbufpos);
1214
1215 /*
1216 * Here's a totally undocumented fact for you. When the
1217 * RealTek chip is in the process of copying a packet into
1218 * RAM for you, the length will be 0xfff0. If you spot a
1219 * packet header with this value, you need to stop. The
1220 * datasheet makes absolutely no mention of this and
1221 * RealTek should be shot for this.
1222 */
1130
1131 /*
1132 * Here's a totally undocumented fact for you. When the
1133 * RealTek chip is in the process of copying a packet into
1134 * RAM for you, the length will be 0xfff0. If you spot a
1135 * packet header with this value, you need to stop. The
1136 * datasheet makes absolutely no mention of this and
1137 * RealTek should be shot for this.
1138 */
1223 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1139 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1224 break;
1225
1226 if (!(rxstat & RL_RXSTAT_RXOK)) {
1227 ifp->if_ierrors++;
1228 rl_init(sc);
1229 return;
1230 }
1231

--- 13 unchanged lines hidden (view full) ---

1245 /*
1246 * Avoid trying to read more bytes than we know
1247 * the chip has prepared for us.
1248 */
1249 if (rx_bytes > max_bytes)
1250 break;
1251
1252 rxbufpos = sc->rl_cdata.rl_rx_buf +
1140 break;
1141
1142 if (!(rxstat & RL_RXSTAT_RXOK)) {
1143 ifp->if_ierrors++;
1144 rl_init(sc);
1145 return;
1146 }
1147

--- 13 unchanged lines hidden (view full) ---

1161 /*
1162 * Avoid trying to read more bytes than we know
1163 * the chip has prepared for us.
1164 */
1165 if (rx_bytes > max_bytes)
1166 break;
1167
1168 rxbufpos = sc->rl_cdata.rl_rx_buf +
1253 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
1254
1169 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1255 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1256 rxbufpos = sc->rl_cdata.rl_rx_buf;
1257
1258 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1170 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1171 rxbufpos = sc->rl_cdata.rl_rx_buf;
1172
1173 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1259
1260 if (total_len > wrap) {
1261 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1262 NULL);
1263 if (m == NULL) {
1264 ifp->if_ierrors++;
1265 } else {
1266 m_copyback(m, wrap, total_len - wrap,
1267 sc->rl_cdata.rl_rx_buf);
1268 }
1269 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1270 } else {
1271 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1272 NULL);
1174 if (total_len > wrap) {
1175 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1176 NULL);
1177 if (m == NULL) {
1178 ifp->if_ierrors++;
1179 } else {
1180 m_copyback(m, wrap, total_len - wrap,
1181 sc->rl_cdata.rl_rx_buf);
1182 }
1183 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1184 } else {
1185 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1186 NULL);
1273 if (m == NULL) {
1187 if (m == NULL)
1274 ifp->if_ierrors++;
1188 ifp->if_ierrors++;
1275 }
1276 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1277 }
1278
1189 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1190 }
1191
1279 /*
1280 * Round up to 32-bit boundary.
1281 */
1192 /* Round up to 32-bit boundary. */
1282 cur_rx = (cur_rx + 3) & ~3;
1283 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1284
1285 if (m == NULL)
1286 continue;
1287
1288 ifp->if_ipackets++;
1289 RL_UNLOCK(sc);
1290 (*ifp->if_input)(ifp, m);
1291 RL_LOCK(sc);
1292 }
1193 cur_rx = (cur_rx + 3) & ~3;
1194 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1195
1196 if (m == NULL)
1197 continue;
1198
1199 ifp->if_ipackets++;
1200 RL_UNLOCK(sc);
1201 (*ifp->if_input)(ifp, m);
1202 RL_LOCK(sc);
1203 }
1293
1294 return;
1295}
1296
1297/*
1298 * A frame was downloaded to the chip. It's safe for us to clean up
1299 * the list buffers.
1300 */
1301static void
1204}
1205
1206/*
1207 * A frame was downloaded to the chip. It's safe for us to clean up
1208 * the list buffers.
1209 */
1210static void
1302rl_txeof(sc)
1303 struct rl_softc *sc;
1211rl_txeof(struct rl_softc *sc)
1304{
1212{
1305 struct ifnet *ifp;
1306 u_int32_t txstat;
1213 struct ifnet *ifp = &sc->arpcom.ac_if;
1214 uint32_t txstat;
1307
1215
1308 ifp = &sc->arpcom.ac_if;
1309
1310 /*
1311 * Go through our tx list and free mbufs for those
1312 * frames that have been uploaded.
1313 */
1314 do {
1315 if (RL_LAST_TXMBUF(sc) == NULL)
1316 break;
1317 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));

--- 30 unchanged lines hidden (view full) ---

1348 RL_INC(sc->rl_cdata.last_tx);
1349 ifp->if_flags &= ~IFF_OACTIVE;
1350 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1351
1352 if (RL_LAST_TXMBUF(sc) == NULL)
1353 ifp->if_timer = 0;
1354 else if (ifp->if_timer == 0)
1355 ifp->if_timer = 5;
1216 /*
1217 * Go through our tx list and free mbufs for those
1218 * frames that have been uploaded.
1219 */
1220 do {
1221 if (RL_LAST_TXMBUF(sc) == NULL)
1222 break;
1223 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));

--- 30 unchanged lines hidden (view full) ---

1254 RL_INC(sc->rl_cdata.last_tx);
1255 ifp->if_flags &= ~IFF_OACTIVE;
1256 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1257
1258 if (RL_LAST_TXMBUF(sc) == NULL)
1259 ifp->if_timer = 0;
1260 else if (ifp->if_timer == 0)
1261 ifp->if_timer = 5;
1356
1357 return;
1358}
1359
1360static void
1262}
1263
1264static void
1361rl_tick(xsc)
1362 void *xsc;
1265rl_tick(void *xsc)
1363{
1266{
1364 struct rl_softc *sc;
1267 struct rl_softc *sc = xsc;
1365 struct mii_data *mii;
1366
1268 struct mii_data *mii;
1269
1367 sc = xsc;
1368 RL_LOCK(sc);
1369 mii = device_get_softc(sc->rl_miibus);
1270 RL_LOCK(sc);
1271 mii = device_get_softc(sc->rl_miibus);
1370
1371 mii_tick(mii);
1372
1373 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1374 RL_UNLOCK(sc);
1272 mii_tick(mii);
1273
1274 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1275 RL_UNLOCK(sc);
1375
1376 return;
1377}
1378
1379#ifdef DEVICE_POLLING
1380static void
1381rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count)
1382{
1383 struct rl_softc *sc = ifp->if_softc;
1384
1385 RL_LOCK(sc);
1276}
1277
1278#ifdef DEVICE_POLLING
1279static void
1280rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count)
1281{
1282 struct rl_softc *sc = ifp->if_softc;
1283
1284 RL_LOCK(sc);
1285
1386 if (!(ifp->if_capenable & IFCAP_POLLING)) {
1387 ether_poll_deregister(ifp);
1388 cmd = POLL_DEREGISTER;
1389 }
1286 if (!(ifp->if_capenable & IFCAP_POLLING)) {
1287 ether_poll_deregister(ifp);
1288 cmd = POLL_DEREGISTER;
1289 }
1390 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1290
1291 if (cmd == POLL_DEREGISTER) {
1292 /* Final call; enable interrupts. */
1391 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1392 goto done;
1393 }
1394
1395 sc->rxcycles = count;
1396 rl_rxeof(sc);
1397 rl_txeof(sc);
1293 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1294 goto done;
1295 }
1296
1297 sc->rxcycles = count;
1298 rl_rxeof(sc);
1299 rl_txeof(sc);
1300
1398 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1399 rl_start(ifp);
1400
1301 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1302 rl_start(ifp);
1303
1401 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1402 u_int16_t status;
1304 if (cmd == POLL_AND_CHECK_STATUS) {
1305 uint16_t status;
1403
1306
1307 /* We should also check the status register. */
1404 status = CSR_READ_2(sc, RL_ISR);
1405 if (status == 0xffff)
1406 goto done;
1308 status = CSR_READ_2(sc, RL_ISR);
1309 if (status == 0xffff)
1310 goto done;
1407 if (status)
1311 if (status != 0)
1408 CSR_WRITE_2(sc, RL_ISR, status);
1409
1312 CSR_WRITE_2(sc, RL_ISR, status);
1313
1410 /*
1411 * XXX check behaviour on receiver stalls.
1412 */
1314 /* XXX We should check behaviour on receiver stalls. */
1413
1414 if (status & RL_ISR_SYSTEM_ERR) {
1415 rl_reset(sc);
1416 rl_init(sc);
1417 }
1418 }
1419done:
1420 RL_UNLOCK(sc);
1421}
1422#endif /* DEVICE_POLLING */
1423
1424static void
1315
1316 if (status & RL_ISR_SYSTEM_ERR) {
1317 rl_reset(sc);
1318 rl_init(sc);
1319 }
1320 }
1321done:
1322 RL_UNLOCK(sc);
1323}
1324#endif /* DEVICE_POLLING */
1325
1326static void
1425rl_intr(arg)
1426 void *arg;
1327rl_intr(void *arg)
1427{
1328{
1428 struct rl_softc *sc;
1329 struct rl_softc *sc = arg;
1429 struct ifnet *ifp;
1330 struct ifnet *ifp;
1430 u_int16_t status;
1331 uint16_t status;
1431
1332
1432 sc = arg;
1433
1434 if (sc->suspended) {
1333 if (sc->suspended)
1435 return;
1334 return;
1436 }
1437
1438 RL_LOCK(sc);
1439 ifp = &sc->arpcom.ac_if;
1440
1441#ifdef DEVICE_POLLING
1442 if (ifp->if_flags & IFF_POLLING)
1443 goto done;
1444 if ((ifp->if_capenable & IFCAP_POLLING) &&
1335
1336 RL_LOCK(sc);
1337 ifp = &sc->arpcom.ac_if;
1338
1339#ifdef DEVICE_POLLING
1340 if (ifp->if_flags & IFF_POLLING)
1341 goto done;
1342 if ((ifp->if_capenable & IFCAP_POLLING) &&
1445 ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */
1343 ether_poll_register(rl_poll, ifp)) {
1344 /* Disable interrupts. */
1446 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1447 rl_poll(ifp, 0, 1);
1448 goto done;
1449 }
1450#endif /* DEVICE_POLLING */
1451
1452 for (;;) {
1345 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1346 rl_poll(ifp, 0, 1);
1347 goto done;
1348 }
1349#endif /* DEVICE_POLLING */
1350
1351 for (;;) {
1453
1454 status = CSR_READ_2(sc, RL_ISR);
1352 status = CSR_READ_2(sc, RL_ISR);
1455 /* If the card has gone away the read returns 0xffff. */
1353 /* If the card has gone away, the read returns 0xffff. */
1456 if (status == 0xffff)
1457 break;
1354 if (status == 0xffff)
1355 break;
1458 if (status)
1356 if (status != 0)
1459 CSR_WRITE_2(sc, RL_ISR, status);
1357 CSR_WRITE_2(sc, RL_ISR, status);
1460
1461 if ((status & RL_INTRS) == 0)
1462 break;
1358 if ((status & RL_INTRS) == 0)
1359 break;
1463
1464 if (status & RL_ISR_RX_OK)
1465 rl_rxeof(sc);
1360 if (status & RL_ISR_RX_OK)
1361 rl_rxeof(sc);
1466
1467 if (status & RL_ISR_RX_ERR)
1468 rl_rxeof(sc);
1362 if (status & RL_ISR_RX_ERR)
1363 rl_rxeof(sc);
1469
1470 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1471 rl_txeof(sc);
1364 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1365 rl_txeof(sc);
1472
1473 if (status & RL_ISR_SYSTEM_ERR) {
1474 rl_reset(sc);
1475 rl_init(sc);
1476 }
1366 if (status & RL_ISR_SYSTEM_ERR) {
1367 rl_reset(sc);
1368 rl_init(sc);
1369 }
1477
1478 }
1479
1480 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1481 rl_start(ifp);
1482
1483#ifdef DEVICE_POLLING
1484done:
1485#endif
1486 RL_UNLOCK(sc);
1370 }
1371
1372 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1373 rl_start(ifp);
1374
1375#ifdef DEVICE_POLLING
1376done:
1377#endif
1378 RL_UNLOCK(sc);
1487
1488 return;
1489}
1490
1491/*
1492 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1493 * pointers to the fragment pointers.
1494 */
1495static int
1379}
1380
1381/*
1382 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1383 * pointers to the fragment pointers.
1384 */
1385static int
1496rl_encap(sc, m_head)
1497 struct rl_softc *sc;
1498 struct mbuf *m_head;
1386rl_encap(struct rl_softc *sc, struct mbuf *m_head)
1499{
1500 struct mbuf *m_new = NULL;
1501
1502 /*
1503 * The RealTek is brain damaged and wants longword-aligned
1504 * TX buffers, plus we can only have one fragment buffer
1505 * per packet. We have to copy pretty much all the time.
1506 */
1507 m_new = m_defrag(m_head, M_DONTWAIT);
1508
1509 if (m_new == NULL) {
1510 m_freem(m_head);
1387{
1388 struct mbuf *m_new = NULL;
1389
1390 /*
1391 * The RealTek is brain damaged and wants longword-aligned
1392 * TX buffers, plus we can only have one fragment buffer
1393 * per packet. We have to copy pretty much all the time.
1394 */
1395 m_new = m_defrag(m_head, M_DONTWAIT);
1396
1397 if (m_new == NULL) {
1398 m_freem(m_head);
1511 return(1);
1399 return (1);
1512 }
1513 m_head = m_new;
1514
1515 /* Pad frames to at least 60 bytes. */
1516 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1517 /*
1518 * Make security concious people happy: zero out the
1519 * bytes in the pad area, since we don't know what

--- 4 unchanged lines hidden (view full) ---

1524 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1525 m_head->m_pkthdr.len +=
1526 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1527 m_head->m_len = m_head->m_pkthdr.len;
1528 }
1529
1530 RL_CUR_TXMBUF(sc) = m_head;
1531
1400 }
1401 m_head = m_new;
1402
1403 /* Pad frames to at least 60 bytes. */
1404 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1405 /*
1406 * Make security concious people happy: zero out the
1407 * bytes in the pad area, since we don't know what

--- 4 unchanged lines hidden (view full) ---

1412 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1413 m_head->m_pkthdr.len +=
1414 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1415 m_head->m_len = m_head->m_pkthdr.len;
1416 }
1417
1418 RL_CUR_TXMBUF(sc) = m_head;
1419
1532 return(0);
1420 return (0);
1533}
1534
1535/*
1536 * Main transmit routine.
1537 */
1538
1539static void
1421}
1422
1423/*
1424 * Main transmit routine.
1425 */
1426
1427static void
1540rl_start(ifp)
1541 struct ifnet *ifp;
1428rl_start(struct ifnet *ifp)
1542{
1429{
1543 struct rl_softc *sc;
1430 struct rl_softc *sc = ifp->if_softc;
1544 struct mbuf *m_head = NULL;
1545
1431 struct mbuf *m_head = NULL;
1432
1546 sc = ifp->if_softc;
1547 RL_LOCK(sc);
1548
1433 RL_LOCK(sc);
1434
1549 while(RL_CUR_TXMBUF(sc) == NULL) {
1435 while (RL_CUR_TXMBUF(sc) == NULL) {
1550 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1551 if (m_head == NULL)
1552 break;
1553
1554 if (rl_encap(sc, m_head)) {
1555 break;
1556 }
1557
1436 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1437 if (m_head == NULL)
1438 break;
1439
1440 if (rl_encap(sc, m_head)) {
1441 break;
1442 }
1443
1558 /*
1559 * If there's a BPF listener, bounce a copy of this frame
1560 * to him.
1561 */
1444 /* Pass a copy of this mbuf chain to the bpf subsystem. */
1562 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1563
1445 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1446
1564 /*
1565 * Transmit the frame.
1566 */
1447 /* Transmit the frame. */
1567 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1568 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1569 mtod(RL_CUR_TXMBUF(sc), void *),
1570 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0);
1571 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1572 BUS_DMASYNC_PREREAD);
1573 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1574 RL_TXTHRESH(sc->rl_txthresh) |
1575 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1576
1577 RL_INC(sc->rl_cdata.cur_tx);
1578
1448 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1449 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1450 mtod(RL_CUR_TXMBUF(sc), void *),
1451 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0);
1452 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1453 BUS_DMASYNC_PREREAD);
1454 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1455 RL_TXTHRESH(sc->rl_txthresh) |
1456 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1457
1458 RL_INC(sc->rl_cdata.cur_tx);
1459
1579 /*
1580 * Set a timeout in case the chip goes out to lunch.
1581 */
1460 /* Set a timeout in case the chip goes out to lunch. */
1582 ifp->if_timer = 5;
1583 }
1584
1585 /*
1586 * We broke out of the loop because all our TX slots are
1587 * full. Mark the NIC as busy until it drains some of the
1588 * packets from the queue.
1589 */
1590 if (RL_CUR_TXMBUF(sc) != NULL)
1591 ifp->if_flags |= IFF_OACTIVE;
1592
1593 RL_UNLOCK(sc);
1461 ifp->if_timer = 5;
1462 }
1463
1464 /*
1465 * We broke out of the loop because all our TX slots are
1466 * full. Mark the NIC as busy until it drains some of the
1467 * packets from the queue.
1468 */
1469 if (RL_CUR_TXMBUF(sc) != NULL)
1470 ifp->if_flags |= IFF_OACTIVE;
1471
1472 RL_UNLOCK(sc);
1594
1595 return;
1596}
1597
1598static void
1473}
1474
1475static void
1599rl_init(xsc)
1600 void *xsc;
1476rl_init(void *xsc)
1601{
1602 struct rl_softc *sc = xsc;
1603 struct ifnet *ifp = &sc->arpcom.ac_if;
1604 struct mii_data *mii;
1477{
1478 struct rl_softc *sc = xsc;
1479 struct ifnet *ifp = &sc->arpcom.ac_if;
1480 struct mii_data *mii;
1605 u_int32_t rxcfg = 0;
1481 uint32_t rxcfg = 0;
1606
1607 RL_LOCK(sc);
1608 mii = device_get_softc(sc->rl_miibus);
1609
1610 /*
1611 * Cancel pending I/O and free all RX/TX buffers.
1612 */
1613 rl_stop(sc);
1614
1615 /*
1616 * Init our MAC address. Even though the chipset
1617 * documentation doesn't mention it, we need to enter "Config
1618 * register write enable" mode to modify the ID registers.
1619 */
1620 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1621 CSR_WRITE_STREAM_4(sc, RL_IDR0,
1482
1483 RL_LOCK(sc);
1484 mii = device_get_softc(sc->rl_miibus);
1485
1486 /*
1487 * Cancel pending I/O and free all RX/TX buffers.
1488 */
1489 rl_stop(sc);
1490
1491 /*
1492 * Init our MAC address. Even though the chipset
1493 * documentation doesn't mention it, we need to enter "Config
1494 * register write enable" mode to modify the ID registers.
1495 */
1496 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1497 CSR_WRITE_STREAM_4(sc, RL_IDR0,
1622 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1498 *(uint32_t *)(&sc->arpcom.ac_enaddr[0]));
1623 CSR_WRITE_STREAM_4(sc, RL_IDR4,
1499 CSR_WRITE_STREAM_4(sc, RL_IDR4,
1624 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1500 *(uint32_t *)(&sc->arpcom.ac_enaddr[4]));
1625 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1626
1627 /* Init the RX buffer pointer register. */
1628 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1629 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0);
1630 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1631 BUS_DMASYNC_PREWRITE);
1632

--- 19 unchanged lines hidden (view full) ---

1652 if (ifp->if_flags & IFF_PROMISC) {
1653 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1654 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1655 } else {
1656 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1657 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1658 }
1659
1501 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1502
1503 /* Init the RX buffer pointer register. */
1504 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1505 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0);
1506 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1507 BUS_DMASYNC_PREWRITE);
1508

--- 19 unchanged lines hidden (view full) ---

1528 if (ifp->if_flags & IFF_PROMISC) {
1529 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1530 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1531 } else {
1532 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1533 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1534 }
1535
1660 /*
1661 * Set capture broadcast bit to capture broadcast frames.
1662 */
1536 /* Set capture broadcast bit to capture broadcast frames. */
1663 if (ifp->if_flags & IFF_BROADCAST) {
1664 rxcfg |= RL_RXCFG_RX_BROAD;
1665 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1666 } else {
1667 rxcfg &= ~RL_RXCFG_RX_BROAD;
1668 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1669 }
1670
1537 if (ifp->if_flags & IFF_BROADCAST) {
1538 rxcfg |= RL_RXCFG_RX_BROAD;
1539 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1540 } else {
1541 rxcfg &= ~RL_RXCFG_RX_BROAD;
1542 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1543 }
1544
1671 /*
1672 * Program the multicast filter, if necessary.
1673 */
1545 /* Program the multicast filter, if necessary. */
1674 rl_setmulti(sc);
1675
1676#ifdef DEVICE_POLLING
1546 rl_setmulti(sc);
1547
1548#ifdef DEVICE_POLLING
1677 /*
1678 * Disable interrupts if we are polling.
1679 */
1549 /* Disable interrupts if we are polling. */
1680 if (ifp->if_flags & IFF_POLLING)
1681 CSR_WRITE_2(sc, RL_IMR, 0);
1550 if (ifp->if_flags & IFF_POLLING)
1551 CSR_WRITE_2(sc, RL_IMR, 0);
1682 else /* otherwise ... */
1552 else
1683#endif /* DEVICE_POLLING */
1553#endif /* DEVICE_POLLING */
1684 /*
1685 * Enable interrupts.
1686 */
1554 /* Enable interrupts. */
1687 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1688
1689 /* Set initial TX threshold */
1690 sc->rl_txthresh = RL_TX_THRESH_INIT;
1691
1692 /* Start RX/TX process. */
1693 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1694
1695 /* Enable receiver and transmitter. */
1696 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1697
1698 mii_mediachg(mii);
1699
1700 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1701
1702 ifp->if_flags |= IFF_RUNNING;
1703 ifp->if_flags &= ~IFF_OACTIVE;
1704
1705 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1555 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1556
1557 /* Set initial TX threshold */
1558 sc->rl_txthresh = RL_TX_THRESH_INIT;
1559
1560 /* Start RX/TX process. */
1561 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1562
1563 /* Enable receiver and transmitter. */
1564 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1565
1566 mii_mediachg(mii);
1567
1568 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1569
1570 ifp->if_flags |= IFF_RUNNING;
1571 ifp->if_flags &= ~IFF_OACTIVE;
1572
1573 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1706 RL_UNLOCK(sc);
1707
1574
1708 return;
1575 RL_UNLOCK(sc);
1709}
1710
1711/*
1712 * Set media options.
1713 */
1714static int
1576}
1577
1578/*
1579 * Set media options.
1580 */
1581static int
1715rl_ifmedia_upd(ifp)
1716 struct ifnet *ifp;
1582rl_ifmedia_upd(struct ifnet *ifp)
1717{
1583{
1718 struct rl_softc *sc;
1584 struct rl_softc *sc = ifp->if_softc;
1719 struct mii_data *mii;
1720
1585 struct mii_data *mii;
1586
1721 sc = ifp->if_softc;
1722 mii = device_get_softc(sc->rl_miibus);
1587 mii = device_get_softc(sc->rl_miibus);
1588
1723 mii_mediachg(mii);
1724
1589 mii_mediachg(mii);
1590
1725 return(0);
1591 return (0);
1726}
1727
1728/*
1729 * Report current media status.
1730 */
1731static void
1592}
1593
1594/*
1595 * Report current media status.
1596 */
1597static void
1732rl_ifmedia_sts(ifp, ifmr)
1733 struct ifnet *ifp;
1734 struct ifmediareq *ifmr;
1598rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1735{
1599{
1736 struct rl_softc *sc;
1600 struct rl_softc *sc = ifp->if_softc;
1737 struct mii_data *mii;
1738
1601 struct mii_data *mii;
1602
1739 sc = ifp->if_softc;
1740 mii = device_get_softc(sc->rl_miibus);
1741
1742 mii_pollstat(mii);
1743 ifmr->ifm_active = mii->mii_media_active;
1744 ifmr->ifm_status = mii->mii_media_status;
1603 mii = device_get_softc(sc->rl_miibus);
1604
1605 mii_pollstat(mii);
1606 ifmr->ifm_active = mii->mii_media_active;
1607 ifmr->ifm_status = mii->mii_media_status;
1745
1746 return;
1747}
1748
1749static int
1608}
1609
1610static int
1750rl_ioctl(ifp, command, data)
1751 struct ifnet *ifp;
1752 u_long command;
1753 caddr_t data;
1611rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1754{
1612{
1755 struct rl_softc *sc = ifp->if_softc;
1756 struct ifreq *ifr = (struct ifreq *) data;
1613 struct ifreq *ifr = (struct ifreq *)data;
1757 struct mii_data *mii;
1614 struct mii_data *mii;
1615 struct rl_softc *sc = ifp->if_softc;
1758 int error = 0;
1759
1760 RL_LOCK(sc);
1761
1616 int error = 0;
1617
1618 RL_LOCK(sc);
1619
1762 switch(command) {
1620 switch (command) {
1763 case SIOCSIFFLAGS:
1764 if (ifp->if_flags & IFF_UP) {
1765 rl_init(sc);
1766 } else {
1767 if (ifp->if_flags & IFF_RUNNING)
1768 rl_stop(sc);
1769 }
1770 error = 0;

--- 14 unchanged lines hidden (view full) ---

1785 break;
1786 default:
1787 error = ether_ioctl(ifp, command, data);
1788 break;
1789 }
1790
1791 RL_UNLOCK(sc);
1792
1621 case SIOCSIFFLAGS:
1622 if (ifp->if_flags & IFF_UP) {
1623 rl_init(sc);
1624 } else {
1625 if (ifp->if_flags & IFF_RUNNING)
1626 rl_stop(sc);
1627 }
1628 error = 0;

--- 14 unchanged lines hidden (view full) ---

1643 break;
1644 default:
1645 error = ether_ioctl(ifp, command, data);
1646 break;
1647 }
1648
1649 RL_UNLOCK(sc);
1650
1793 return(error);
1651 return (error);
1794}
1795
1796static void
1652}
1653
1654static void
1797rl_watchdog(ifp)
1798 struct ifnet *ifp;
1655rl_watchdog(struct ifnet *ifp)
1799{
1656{
1800 struct rl_softc *sc;
1657 struct rl_softc *sc = ifp->if_softc;
1801
1658
1802 sc = ifp->if_softc;
1803 RL_LOCK(sc);
1659 RL_LOCK(sc);
1804 printf("rl%d: watchdog timeout\n", sc->rl_unit);
1660
1661 if_printf(ifp, "watchdog timeout\n");
1805 ifp->if_oerrors++;
1806
1807 rl_txeof(sc);
1808 rl_rxeof(sc);
1809 rl_init(sc);
1662 ifp->if_oerrors++;
1663
1664 rl_txeof(sc);
1665 rl_rxeof(sc);
1666 rl_init(sc);
1810 RL_UNLOCK(sc);
1811
1667
1812 return;
1668 RL_UNLOCK(sc);
1813}
1814
1815/*
1816 * Stop the adapter and free any mbufs allocated to the
1817 * RX and TX lists.
1818 */
1819static void
1669}
1670
1671/*
1672 * Stop the adapter and free any mbufs allocated to the
1673 * RX and TX lists.
1674 */
1675static void
1820rl_stop(sc)
1821 struct rl_softc *sc;
1676rl_stop(struct rl_softc *sc)
1822{
1823 register int i;
1677{
1678 register int i;
1824 struct ifnet *ifp;
1679 struct ifnet *ifp = &sc->arpcom.ac_if;
1825
1680
1826 RL_LOCK(sc);
1827 ifp = &sc->arpcom.ac_if;
1828 ifp->if_timer = 0;
1829
1681 ifp->if_timer = 0;
1682
1683 RL_LOCK(sc);
1684
1830 untimeout(rl_tick, sc, sc->rl_stat_ch);
1831 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1832#ifdef DEVICE_POLLING
1833 ether_poll_deregister(ifp);
1834#endif /* DEVICE_POLLING */
1835
1836 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1837 CSR_WRITE_2(sc, RL_IMR, 0x0000);

--- 5 unchanged lines hidden (view full) ---

1843 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1844 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1845 bus_dmamap_unload(sc->rl_tag,
1846 sc->rl_cdata.rl_tx_dmamap[i]);
1847 bus_dmamap_destroy(sc->rl_tag,
1848 sc->rl_cdata.rl_tx_dmamap[i]);
1849 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1850 sc->rl_cdata.rl_tx_chain[i] = NULL;
1685 untimeout(rl_tick, sc, sc->rl_stat_ch);
1686 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1687#ifdef DEVICE_POLLING
1688 ether_poll_deregister(ifp);
1689#endif /* DEVICE_POLLING */
1690
1691 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1692 CSR_WRITE_2(sc, RL_IMR, 0x0000);

--- 5 unchanged lines hidden (view full) ---

1698 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1699 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1700 bus_dmamap_unload(sc->rl_tag,
1701 sc->rl_cdata.rl_tx_dmamap[i]);
1702 bus_dmamap_destroy(sc->rl_tag,
1703 sc->rl_cdata.rl_tx_dmamap[i]);
1704 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1705 sc->rl_cdata.rl_tx_chain[i] = NULL;
1851 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(u_int32_t)),
1706 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1852 0x0000000);
1853 }
1854 }
1855
1856 RL_UNLOCK(sc);
1707 0x0000000);
1708 }
1709 }
1710
1711 RL_UNLOCK(sc);
1857 return;
1858}
1859
1860/*
1861 * Device suspend routine. Stop the interface and save some PCI
1862 * settings in case the BIOS doesn't restore them properly on
1863 * resume.
1864 */
1865static int
1712}
1713
1714/*
1715 * Device suspend routine. Stop the interface and save some PCI
1716 * settings in case the BIOS doesn't restore them properly on
1717 * resume.
1718 */
1719static int
1866rl_suspend(dev)
1867 device_t dev;
1720rl_suspend(device_t dev)
1868{
1869 struct rl_softc *sc;
1870
1871 sc = device_get_softc(dev);
1872 rl_stop(sc);
1873 sc->suspended = 1;
1874
1875 return (0);
1876}
1877
1878/*
1879 * Device resume routine. Restore some PCI settings in case the BIOS
1880 * doesn't, re-enable busmastering, and restart the interface if
1881 * appropriate.
1882 */
1883static int
1721{
1722 struct rl_softc *sc;
1723
1724 sc = device_get_softc(dev);
1725 rl_stop(sc);
1726 sc->suspended = 1;
1727
1728 return (0);
1729}
1730
1731/*
1732 * Device resume routine. Restore some PCI settings in case the BIOS
1733 * doesn't, re-enable busmastering, and restart the interface if
1734 * appropriate.
1735 */
1736static int
1884rl_resume(dev)
1885 device_t dev;
1737rl_resume(device_t dev)
1886{
1887 struct rl_softc *sc;
1888 struct ifnet *ifp;
1889
1890 sc = device_get_softc(dev);
1891 ifp = &sc->arpcom.ac_if;
1892
1893 /* reinitialize interface if necessary */

--- 5 unchanged lines hidden (view full) ---

1899 return (0);
1900}
1901
1902/*
1903 * Stop all chip I/O so that the kernel's probe routines don't
1904 * get confused by errant DMAs when rebooting.
1905 */
1906static void
1738{
1739 struct rl_softc *sc;
1740 struct ifnet *ifp;
1741
1742 sc = device_get_softc(dev);
1743 ifp = &sc->arpcom.ac_if;
1744
1745 /* reinitialize interface if necessary */

--- 5 unchanged lines hidden (view full) ---

1751 return (0);
1752}
1753
1754/*
1755 * Stop all chip I/O so that the kernel's probe routines don't
1756 * get confused by errant DMAs when rebooting.
1757 */
1758static void
1907rl_shutdown(dev)
1908 device_t dev;
1759rl_shutdown(device_t dev)
1909{
1910 struct rl_softc *sc;
1911
1912 sc = device_get_softc(dev);
1760{
1761 struct rl_softc *sc;
1762
1763 sc = device_get_softc(dev);
1913
1914 rl_stop(sc);
1764 rl_stop(sc);
1915
1916 return;
1917}
1765}