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if_rl.c (119738) if_rl.c (119868)
1/*
1/*
2 * Copyright (c) 1997, 1998-2003
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright

--- 15 unchanged lines hidden (view full) ---

26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/*
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright

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26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/*
34 * RealTek 8129/8139/8139C+/8169 PCI NIC driver
34 * RealTek 8129/8139 PCI NIC driver
35 *
35 *
36 * Supports several extremely cheap PCI 10/100 and 10/100/1000 adapters
37 * based on RealTek chipsets. Datasheets can be obtained from
36 * Supports several extremely cheap PCI 10/100 adapters based on
37 * the RealTek chipset. Datasheets can be obtained from
38 * www.realtek.com.tw.
39 *
38 * www.realtek.com.tw.
39 *
40 * Written by Bill Paul <wpaul@windriver.com>
41 * Senior Networking Software Engineer
42 * Wind River Systems
40 * Written by Bill Paul <wpaul@ctr.columbia.edu>
41 * Electrical Engineering Department
42 * Columbia University, New York City
43 */
44
45/*
46 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
47 * probably the worst PCI ethernet controller ever made, with the possible
48 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
49 * DMA, but it has a terrible interface that nullifies any performance
50 * gains that bus-master DMA usually offers.

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74 * PHY registers are directly accessible through the 8139's register
75 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
76 * filter.
77 *
78 * The 8129 chip is an older version of the 8139 that uses an external PHY
79 * chip. The 8129 has a serial MDIO interface for accessing the MII where
80 * the 8139 lets you directly access the on-board PHY registers. We need
81 * to select which interface to use depending on the chip type.
43 */
44
45/*
46 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
47 * probably the worst PCI ethernet controller ever made, with the possible
48 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
49 * DMA, but it has a terrible interface that nullifies any performance
50 * gains that bus-master DMA usually offers.

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74 * PHY registers are directly accessible through the 8139's register
75 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
76 * filter.
77 *
78 * The 8129 chip is an older version of the 8139 that uses an external PHY
79 * chip. The 8129 has a serial MDIO interface for accessing the MII where
80 * the 8139 lets you directly access the on-board PHY registers. We need
81 * to select which interface to use depending on the chip type.
82 *
83 * Fast forward a few years. RealTek now has a new chip called the
84 * 8139C+ which at long last implements descriptor-based DMA. Not
85 * only that, it supports RX and TX TCP/IP checksum offload, VLAN
86 * tagging and insertion, TCP large send and 64-bit addressing.
87 * Better still, it allows arbitrary byte alignments for RX and
88 * TX buffers, meaning no copying is necessary on any architecture.
89 * There are a few limitations however: the RX and TX descriptor
90 * rings must be aligned on 256 byte boundaries, they must be in
91 * contiguous RAM, and each ring can have a maximum of 64 descriptors.
92 * There are two TX descriptor queues: one normal priority and one
93 * high. Descriptor ring addresses and DMA buffer addresses are
94 * 64 bits wide. The 8139C+ is also backwards compatible with the
95 * 8139, so the chip will still function with older drivers: C+
96 * mode has to be enabled by setting the appropriate bits in the C+
97 * command register. The PHY access mechanism appears to be unchanged.
98 *
99 * The 8169 is a 10/100/1000 ethernet MAC. It has almost the same
100 * programming API as the C+ mode of the 8139C+, with a couple of
101 * minor changes and additions: TX start register and timer interrupt
102 * register are located at different offsets, and there are additional
103 * registers for GMII PHY status and control, as well as TBI-mode
104 * status and control. There is also a maximum RX packet size
105 * register to allow the chip to receive jumbo frames. The 8169
106 * can only be programmed in C+ mode: the old 8139 programming
107 * method isn't supported with this chip. Also, RealTek has a LOM
108 * (LAN On Motherboard) gigabit MAC chip called the RTL8110S which
109 * I believe to be register compatible with the 8169. Unlike the
110 * 8139C+, the 8169 can have up to 1024 descriptors per DMA ring.
111 * The reference 8169 board design uses a Marvell 88E1000 'Alaska'
112 * copper PHY.
113 *
114 * The 8169S and 8110S are newer versions of the 8169. Available
115 * in both 32-bit and 64-bit forms, these devices have built-in
116 * copper 10/100/1000 PHYs. The 8110S is a lan-on-motherboard chip
117 * that is pin-for-pin compatible with the 8100. Unfortunately,
118 * RealTek has not released programming manuals for the 8169S and
119 * 8110S yet. The datasheet for the original 8169 provides most
120 * of the information, but you must refer to RealTek's 8169 Linux
121 * driver to fill in the gaps. Mostly, it appears that the built-in
122 * PHY requires some special initialization. The original 8169
123 * datasheet and the 8139C+ datasheet can be obtained from
124 * http://www.freebsd.org/~wpaul/RealTek.
125 *
126 * This driver now supports both the old 8139 and new 8139C+
127 * programming models. We detect the 8139C+ by looking for the
128 * corresponding hardware rev bits, and we detect the 8169 by its
129 * PCI ID. Two new NIC type codes, RL_8139CPLUS and RL_8169 have
130 * been added to distinguish the chips at runtime. Separate RX and
131 * TX handling routines have been added to handle C+ mode, which
132 * are selected via function pointers that are initialized during
133 * the driver attach phase.
134 */
135
136#include <sys/cdefs.h>
82 */
83
84#include <sys/cdefs.h>
137__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 119738 2003-09-04 15:39:44Z tmm $");
85__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 119868 2003-09-08 02:11:25Z wpaul $");
138
139#include <sys/param.h>
140#include <sys/endian.h>
141#include <sys/systm.h>
142#include <sys/sockio.h>
143#include <sys/mbuf.h>
144#include <sys/malloc.h>
145#include <sys/kernel.h>
146#include <sys/socket.h>
147
148#include <net/if.h>
149#include <net/if_arp.h>
150#include <net/ethernet.h>
151#include <net/if_dl.h>
152#include <net/if_media.h>
86
87#include <sys/param.h>
88#include <sys/endian.h>
89#include <sys/systm.h>
90#include <sys/sockio.h>
91#include <sys/mbuf.h>
92#include <sys/malloc.h>
93#include <sys/kernel.h>
94#include <sys/socket.h>
95
96#include <net/if.h>
97#include <net/if_arp.h>
98#include <net/ethernet.h>
99#include <net/if_dl.h>
100#include <net/if_media.h>
153#include <net/if_vlan_var.h>
154
155#include <net/bpf.h>
156
157#include <machine/bus_pio.h>
158#include <machine/bus_memio.h>
159#include <machine/bus.h>
160#include <machine/resource.h>
161#include <sys/bus.h>
162#include <sys/rman.h>
163
164#include <dev/mii/mii.h>
165#include <dev/mii/miivar.h>
166
101
102#include <net/bpf.h>
103
104#include <machine/bus_pio.h>
105#include <machine/bus_memio.h>
106#include <machine/bus.h>
107#include <machine/resource.h>
108#include <sys/bus.h>
109#include <sys/rman.h>
110
111#include <dev/mii/mii.h>
112#include <dev/mii/miivar.h>
113
167#include <dev/pci/pcireg.h>
168#include <dev/pci/pcivar.h>
114#include
115#include
169
170MODULE_DEPEND(rl, pci, 1, 1, 1);
171MODULE_DEPEND(rl, ether, 1, 1, 1);
172MODULE_DEPEND(rl, miibus, 1, 1, 1);
173
174/* "controller miibus0" required. See GENERIC if you get errors here. */
175#include "miibus_if.h"
176

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181 * can hang the bus. I'm inclined to blame this on crummy design/construction
182 * on the part of RealTek. Memory mapped mode does appear to work on
183 * uniprocessor systems though.
184 */
185#define RL_USEIOSPACE
186
187#include <pci/if_rlreg.h>
188
116
117MODULE_DEPEND(rl, pci, 1, 1, 1);
118MODULE_DEPEND(rl, ether, 1, 1, 1);
119MODULE_DEPEND(rl, miibus, 1, 1, 1);
120
121/* "controller miibus0" required. See GENERIC if you get errors here. */
122#include "miibus_if.h"
123

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128 * can hang the bus. I'm inclined to blame this on crummy design/construction
129 * on the part of RealTek. Memory mapped mode does appear to work on
130 * uniprocessor systems though.
131 */
132#define RL_USEIOSPACE
133
134#include <pci/if_rlreg.h>
135
189#define RL_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
190
191/*
192 * Various supported device vendors/types and their names.
193 */
194static struct rl_type rl_devs[] = {
195 { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
196 "RealTek 8129 10/100BaseTX" },
197 { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
198 "RealTek 8139 10/100BaseTX" },
136/*
137 * Various supported device vendors/types and their names.
138 */
139static struct rl_type rl_devs[] = {
140 { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
141 "RealTek 8129 10/100BaseTX" },
142 { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
143 "RealTek 8139 10/100BaseTX" },
199 { RT_VENDORID, RT_DEVICEID_8169, RL_8169,
200 "RealTek 8169 10/100/1000BaseTX" },
201 { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
202 "RealTek 8139 10/100BaseTX CardBus" },
203 { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
204 "RealTek 8100 10/100BaseTX" },
205 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
206 "Accton MPX 5030/5038 10/100BaseTX" },
207 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
208 "Delta Electronics 8139 10/100BaseTX" },

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213 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
214 "D-Link DFE-690TXD 10/100BaseTX" },
215 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
216 "Nortel Networks 10/100BaseTX" },
217 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
218 "Corega FEther CB-TXD" },
219 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
220 "Corega FEtherII CB-TXD" },
144 { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
145 "RealTek 8139 10/100BaseTX CardBus" },
146 { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
147 "RealTek 8100 10/100BaseTX" },
148 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
149 "Accton MPX 5030/5038 10/100BaseTX" },
150 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
151 "Delta Electronics 8139 10/100BaseTX" },

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156 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
157 "D-Link DFE-690TXD 10/100BaseTX" },
158 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
159 "Nortel Networks 10/100BaseTX" },
160 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
161 "Corega FEther CB-TXD" },
162 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
163 "Corega FEtherII CB-TXD" },
221 /* XXX what type of realtek is PEPPERCON_DEVICEID_ROLF ? */
222 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
223 "Peppercon AG ROL-F" },
224 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
225 "Planex FNW-3800-TX" },
226 { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
227 "Compaq HNE-300" },
228 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
229 "LevelOne FPC-0106TX" },
230 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
231 "Edimax EP-4103DL CardBus" },
164 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
165 "Peppercon AG ROL-F" },
166 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
167 "Planex FNW-3800-TX" },
168 { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
169 "Compaq HNE-300" },
170 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
171 "LevelOne FPC-0106TX" },
172 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
173 "Edimax EP-4103DL CardBus" },
232 { 0, 0, 0, NULL }
233};
234
235static struct rl_hwrev rl_hwrevs[] = {
236 { RL_HWREV_8139, RL_8139, "" },
237 { RL_HWREV_8139A, RL_8139, "A" },
238 { RL_HWREV_8139AG, RL_8139, "A-G" },
239 { RL_HWREV_8139B, RL_8139, "B" },
240 { RL_HWREV_8130, RL_8139, "8130" },
241 { RL_HWREV_8139C, RL_8139, "C" },
242 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" },
243 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"},
244 { RL_HWREV_8169, RL_8169, "8169"},
245 { RL_HWREV_8110, RL_8169, "8169S/8110S"},
246 { RL_HWREV_8100, RL_8139, "8100"},
247 { RL_HWREV_8101, RL_8139, "8101"},
248 { 0, 0, NULL }
249};
250
251static int rl_probe (device_t);
252static int rl_attach (device_t);
253static int rl_detach (device_t);
254
174 { 0, 0, NULL }
175};
176
177static int rl_probe (device_t);
178static int rl_attach (device_t);
179static int rl_detach (device_t);
180
255static int rl_encap (struct rl_softc *, struct mbuf *);
256static int rl_encapcplus (struct rl_softc *, struct mbuf *, int *);
181static int rl_encap (struct rl_softc *, struct mbuf * );
257
182
258static void rl_dma_map_addr (void *, bus_dma_segment_t *, int, int);
259static void rl_dma_map_desc (void *, bus_dma_segment_t *, int,
260 bus_size_t, int);
261static int rl_allocmem (device_t, struct rl_softc *);
262static int rl_allocmemcplus (device_t, struct rl_softc *);
263static int rl_newbuf (struct rl_softc *, int, struct mbuf *);
264static int rl_rx_list_init (struct rl_softc *);
265static int rl_tx_list_init (struct rl_softc *);
266static void rl_rxeof (struct rl_softc *);
183static void rl_rxeof (struct rl_softc *);
267static void rl_rxeofcplus (struct rl_softc *);
268static void rl_txeof (struct rl_softc *);
184static void rl_txeof (struct rl_softc *);
269static void rl_txeofcplus (struct rl_softc *);
270static void rl_intr (void *);
185static void rl_intr (void *);
271static void rl_intrcplus (void *);
272static void rl_tick (void *);
273static void rl_start (struct ifnet *);
186static void rl_tick (void *);
187static void rl_start (struct ifnet *);
274static void rl_startcplus (struct ifnet *);
275static int rl_ioctl (struct ifnet *, u_long, caddr_t);
276static void rl_init (void *);
277static void rl_stop (struct rl_softc *);
278static void rl_watchdog (struct ifnet *);
279static int rl_suspend (device_t);
280static int rl_resume (device_t);
281static void rl_shutdown (device_t);
282static int rl_ifmedia_upd (struct ifnet *);
283static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
284
285static void rl_eeprom_putbyte (struct rl_softc *, int);
286static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *);
287static void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int);
288static void rl_mii_sync (struct rl_softc *);
289static void rl_mii_send (struct rl_softc *, u_int32_t, int);
290static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *);
291static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *);
188static int rl_ioctl (struct ifnet *, u_long, caddr_t);
189static void rl_init (void *);
190static void rl_stop (struct rl_softc *);
191static void rl_watchdog (struct ifnet *);
192static int rl_suspend (device_t);
193static int rl_resume (device_t);
194static void rl_shutdown (device_t);
195static int rl_ifmedia_upd (struct ifnet *);
196static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
197
198static void rl_eeprom_putbyte (struct rl_softc *, int);
199static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *);
200static void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int);
201static void rl_mii_sync (struct rl_softc *);
202static void rl_mii_send (struct rl_softc *, u_int32_t, int);
203static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *);
204static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *);
292static int rl_gmii_readreg (device_t, int, int);
293static int rl_gmii_writereg (device_t, int, int, int);
294
295static int rl_miibus_readreg (device_t, int, int);
296static int rl_miibus_writereg (device_t, int, int, int);
297static void rl_miibus_statchg (device_t);
298
299static u_int8_t rl_calchash (caddr_t);
300static void rl_setmulti (struct rl_softc *);
301static void rl_reset (struct rl_softc *);

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681 MII_CLR(RL_MII_DIR);
682
683 RL_UNLOCK(sc);
684
685 return(0);
686}
687
688static int
205
206static int rl_miibus_readreg (device_t, int, int);
207static int rl_miibus_writereg (device_t, int, int, int);
208static void rl_miibus_statchg (device_t);
209
210static u_int8_t rl_calchash (caddr_t);
211static void rl_setmulti (struct rl_softc *);
212static void rl_reset (struct rl_softc *);

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592 MII_CLR(RL_MII_DIR);
593
594 RL_UNLOCK(sc);
595
596 return(0);
597}
598
599static int
689rl_gmii_readreg(dev, phy, reg)
690 device_t dev;
691 int phy, reg;
692{
693 struct rl_softc *sc;
694 u_int32_t rval;
695 int i;
696
697 if (phy != 1)
698 return(0);
699
700 sc = device_get_softc(dev);
701
702 CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
703 DELAY(1000);
704
705 for (i = 0; i < RL_TIMEOUT; i++) {
706 rval = CSR_READ_4(sc, RL_PHYAR);
707 if (rval & RL_PHYAR_BUSY)
708 break;
709 DELAY(100);
710 }
711
712 if (i == RL_TIMEOUT) {
713 printf ("rl%d: PHY read failed\n", sc->rl_unit);
714 return (0);
715 }
716
717 return (rval & RL_PHYAR_PHYDATA);
718}
719
720static int
721rl_gmii_writereg(dev, phy, reg, data)
722 device_t dev;
723 int phy, reg, data;
724{
725 struct rl_softc *sc;
726 u_int32_t rval;
727 int i;
728
729 if (phy > 0)
730 return(0);
731
732 sc = device_get_softc(dev);
733
734 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
735 (data | RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
736 DELAY(1000);
737
738 for (i = 0; i < RL_TIMEOUT; i++) {
739 rval = CSR_READ_4(sc, RL_PHYAR);
740 if (!(rval & RL_PHYAR_BUSY))
741 break;
742 DELAY(100);
743 }
744
745 if (i == RL_TIMEOUT) {
746 printf ("rl%d: PHY write failed\n", sc->rl_unit);
747 return (0);
748 }
749
750 return (0);
751}
752
753static int
754rl_miibus_readreg(dev, phy, reg)
755 device_t dev;
756 int phy, reg;
757{
758 struct rl_softc *sc;
759 struct rl_mii_frame frame;
760 u_int16_t rval = 0;
761 u_int16_t rl8139_reg = 0;
762
763 sc = device_get_softc(dev);
764 RL_LOCK(sc);
765
600rl_miibus_readreg(dev, phy, reg)
601 device_t dev;
602 int phy, reg;
603{
604 struct rl_softc *sc;
605 struct rl_mii_frame frame;
606 u_int16_t rval = 0;
607 u_int16_t rl8139_reg = 0;
608
609 sc = device_get_softc(dev);
610 RL_LOCK(sc);
611
766 if (sc->rl_type == RL_8169) {
767 rval = rl_gmii_readreg(dev, phy, reg);
768 RL_UNLOCK(sc);
769 return (rval);
770 }
771
772 if (sc->rl_type == RL_8139 || sc->rl_type == RL_8139CPLUS) {
612 if (sc->rl_type == RL_8139) {
773 /* Pretend the internal PHY is only at address 0 */
774 if (phy) {
775 RL_UNLOCK(sc);
776 return(0);
777 }
778 switch(reg) {
779 case MII_BMCR:
780 rl8139_reg = RL_BMCR;

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828static int
829rl_miibus_writereg(dev, phy, reg, data)
830 device_t dev;
831 int phy, reg, data;
832{
833 struct rl_softc *sc;
834 struct rl_mii_frame frame;
835 u_int16_t rl8139_reg = 0;
613 /* Pretend the internal PHY is only at address 0 */
614 if (phy) {
615 RL_UNLOCK(sc);
616 return(0);
617 }
618 switch(reg) {
619 case MII_BMCR:
620 rl8139_reg = RL_BMCR;

--- 47 unchanged lines hidden (view full) ---

668static int
669rl_miibus_writereg(dev, phy, reg, data)
670 device_t dev;
671 int phy, reg, data;
672{
673 struct rl_softc *sc;
674 struct rl_mii_frame frame;
675 u_int16_t rl8139_reg = 0;
836 int rval = 0;
837
838 sc = device_get_softc(dev);
839 RL_LOCK(sc);
840
676
677 sc = device_get_softc(dev);
678 RL_LOCK(sc);
679
841 if (sc->rl_type == RL_8169) {
842 rval = rl_gmii_writereg(dev, phy, reg, data);
843 RL_UNLOCK(sc);
844 return (rval);
845 }
846
847 if (sc->rl_type == RL_8139 || sc->rl_type == RL_8139CPLUS) {
680 if (sc->rl_type == RL_8139) {
848 /* Pretend the internal PHY is only at address 0 */
849 if (phy) {
850 RL_UNLOCK(sc);
851 return(0);
852 }
853 switch(reg) {
854 case MII_BMCR:
855 rl8139_reg = RL_BMCR;

--- 138 unchanged lines hidden (view full) ---

994 for (i = 0; i < RL_TIMEOUT; i++) {
995 DELAY(10);
996 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
997 break;
998 }
999 if (i == RL_TIMEOUT)
1000 printf("rl%d: reset never completed!\n", sc->rl_unit);
1001
681 /* Pretend the internal PHY is only at address 0 */
682 if (phy) {
683 RL_UNLOCK(sc);
684 return(0);
685 }
686 switch(reg) {
687 case MII_BMCR:
688 rl8139_reg = RL_BMCR;

--- 138 unchanged lines hidden (view full) ---

827 for (i = 0; i < RL_TIMEOUT; i++) {
828 DELAY(10);
829 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
830 break;
831 }
832 if (i == RL_TIMEOUT)
833 printf("rl%d: reset never completed!\n", sc->rl_unit);
834
1002 CSR_WRITE_1(sc, 0x82, 1);
1003
1004 return;
1005}
1006
1007/*
1008 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
1009 * IDs against our list and return a device name if we find a match.
1010 */
1011static int
1012rl_probe(dev)
1013 device_t dev;
1014{
1015 struct rl_type *t;
835 return;
836}
837
838/*
839 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
840 * IDs against our list and return a device name if we find a match.
841 */
842static int
843rl_probe(dev)
844 device_t dev;
845{
846 struct rl_type *t;
1016 struct rl_softc *sc;
1017 struct rl_hwrev *hw_rev;
847 struct rl_softc *sc;
1018 int rid;
1019 u_int32_t hwrev;
848 int rid;
849 u_int32_t hwrev;
1020 char desc[64];
1021
1022 t = rl_devs;
1023 sc = device_get_softc(dev);
1024
1025 while(t->rl_name != NULL) {
1026 if ((pci_get_vendor(dev) == t->rl_vid) &&
1027 (pci_get_device(dev) == t->rl_did)) {
1028

--- 9 unchanged lines hidden (view full) ---

1038 "couldn't map ports/memory\n");
1039 return(ENXIO);
1040 }
1041 sc->rl_btag = rman_get_bustag(sc->rl_res);
1042 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1043 mtx_init(&sc->rl_mtx,
1044 device_get_nameunit(dev),
1045 MTX_NETWORK_LOCK, MTX_DEF);
850
851 t = rl_devs;
852 sc = device_get_softc(dev);
853
854 while(t->rl_name != NULL) {
855 if ((pci_get_vendor(dev) == t->rl_vid) &&
856 (pci_get_device(dev) == t->rl_did)) {
857

--- 9 unchanged lines hidden (view full) ---

867 "couldn't map ports/memory\n");
868 return(ENXIO);
869 }
870 sc->rl_btag = rman_get_bustag(sc->rl_res);
871 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
872 mtx_init(&sc->rl_mtx,
873 device_get_nameunit(dev),
874 MTX_NETWORK_LOCK, MTX_DEF);
1046 RL_LOCK(sc);
1047 if (t->rl_basetype == RL_8139) {
1048 hwrev = CSR_READ_4(sc, RL_TXCFG) &
1049 RL_TXCFG_HWREV;
1050 hw_rev = rl_hwrevs;
1051 while (hw_rev->rl_desc != NULL) {
1052 if (hw_rev->rl_rev == hwrev) {
1053 sprintf(desc, "%s, rev. %s",
1054 t->rl_name,
1055 hw_rev->rl_desc);
1056 sc->rl_type = hw_rev->rl_type;
1057 break;
1058 }
1059 hw_rev++;
1060 }
1061 if (hw_rev->rl_desc == NULL)
1062 sprintf(desc, "%s, rev. %s",
1063 t->rl_name, "unknown");
1064 } else
1065 sprintf(desc, "%s", t->rl_name);
1066 bus_release_resource(dev, RL_RES,
1067 RL_RID, sc->rl_res);
875 RL_LOCK(sc);
876 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
877 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1068 RL_UNLOCK(sc);
1069 mtx_destroy(&sc->rl_mtx);
878 RL_UNLOCK(sc);
879 mtx_destroy(&sc->rl_mtx);
1070 device_set_desc_copy(dev, desc);
880
881 /* Don't attach to 8139C+ or 8169/8110 chips. */
882 if (hwrev == RL_HWREV_8139CPLUS ||
883 hwrev == RL_HWREV_8169 ||
884 hwrev == RL_HWREV_8110) {
885 t++;
886 continue;
887 }
888
889 device_set_desc(dev, t->rl_name);
1071 return(0);
1072 }
1073 t++;
1074 }
1075
1076 return(ENXIO);
1077}
1078
1079/*
890 return(0);
891 }
892 t++;
893 }
894
895 return(ENXIO);
896}
897
898/*
1080 * This routine takes the segment list provided as the result of
1081 * a bus_dma_map_load() operation and assigns the addresses/lengths
1082 * to RealTek DMA descriptors. This can be called either by the RX
1083 * code or the TX code. In the RX case, we'll probably wind up mapping
1084 * at most one segment. For the TX case, there could be any number of
1085 * segments since TX packets may span multiple mbufs. In either case,
1086 * if the number of segments is larger than the rl_maxsegs limit
1087 * specified by the caller, we abort the mapping operation. Sadly,
1088 * whoever designed the buffer mapping API did not provide a way to
1089 * return an error from here, so we have to fake it a bit.
1090 */
1091
1092static void
1093rl_dma_map_desc(arg, segs, nseg, mapsize, error)
1094 void *arg;
1095 bus_dma_segment_t *segs;
1096 int nseg;
1097 bus_size_t mapsize;
1098 int error;
1099{
1100 struct rl_dmaload_arg *ctx;
1101 struct rl_desc *d = NULL;
1102 int i = 0, idx;
1103
1104 if (error)
1105 return;
1106
1107 ctx = arg;
1108
1109 /* Signal error to caller if there's too many segments */
1110 if (nseg > ctx->rl_maxsegs) {
1111 ctx->rl_maxsegs = 0;
1112 return;
1113 }
1114
1115 /*
1116 * Map the segment array into descriptors. Note that we set the
1117 * start-of-frame and end-of-frame markers for either TX or RX, but
1118 * they really only have meaning in the TX case. (In the RX case,
1119 * it's the chip that tells us where packets begin and end.)
1120 * We also keep track of the end of the ring and set the
1121 * end-of-ring bits as needed, and we set the ownership bits
1122 * in all except the very first descriptor. (The caller will
1123 * set this descriptor later when it start transmission or
1124 * reception.)
1125 */
1126 idx = ctx->rl_idx;
1127 while(1) {
1128 u_int32_t cmdstat;
1129 d = &ctx->rl_ring[idx];
1130 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) {
1131 ctx->rl_maxsegs = 0;
1132 return;
1133 }
1134 cmdstat = segs[i].ds_len;
1135 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
1136 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
1137 if (i == 0)
1138 cmdstat |= RL_TDESC_CMD_SOF;
1139 else
1140 cmdstat |= RL_TDESC_CMD_OWN;
1141 if (idx == (RL_RX_DESC_CNT - 1))
1142 cmdstat |= RL_TDESC_CMD_EOR;
1143 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags);
1144 i++;
1145 if (i == nseg)
1146 break;
1147 RL_DESC_INC(idx);
1148 }
1149
1150 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
1151 ctx->rl_maxsegs = nseg;
1152 ctx->rl_idx = idx;
1153
1154 return;
1155}
1156
1157/*
1158 * Map a single buffer address.
1159 */
1160
1161static void
1162rl_dma_map_addr(arg, segs, nseg, error)
1163 void *arg;
1164 bus_dma_segment_t *segs;
1165 int nseg;
1166 int error;
1167{
1168 u_int32_t *addr;
1169
1170 if (error)
1171 return;
1172
1173 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
1174 addr = arg;
1175 *addr = segs->ds_addr;
1176
1177 return;
1178}
1179
1180static int
1181rl_allocmem(dev, sc)
1182 device_t dev;
1183 struct rl_softc *sc;
1184{
1185 int error;
1186
1187 /*
1188 * Now allocate a tag for the DMA descriptor lists.
1189 * All of our lists are allocated as a contiguous block
1190 * of memory.
1191 */
1192 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
1193 1, 0, /* alignment, boundary */
1194 BUS_SPACE_MAXADDR, /* lowaddr */
1195 BUS_SPACE_MAXADDR, /* highaddr */
1196 NULL, NULL, /* filter, filterarg */
1197 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */
1198 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1199 0, /* flags */
1200 NULL, NULL, /* lockfunc, lockarg */
1201 &sc->rl_tag);
1202 if (error)
1203 return(error);
1204
1205 /*
1206 * Now allocate a chunk of DMA-able memory based on the
1207 * tag we just created.
1208 */
1209 error = bus_dmamem_alloc(sc->rl_tag,
1210 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT,
1211 &sc->rl_cdata.rl_rx_dmamap);
1212
1213 if (error) {
1214 printf("rl%d: no memory for list buffers!\n", sc->rl_unit);
1215 bus_dma_tag_destroy(sc->rl_tag);
1216 sc->rl_tag = NULL;
1217 return(error);
1218 }
1219
1220 /* Leave a few bytes before the start of the RX ring buffer. */
1221 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1222 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
1223
1224 return(0);
1225}
1226
1227static int
1228rl_allocmemcplus(dev, sc)
1229 device_t dev;
1230 struct rl_softc *sc;
1231{
1232 int error;
1233 int nseg;
1234 int i;
1235
1236 /*
1237 * Allocate map for RX mbufs.
1238 */
1239 nseg = 32;
1240 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0,
1241 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1242 NULL, MCLBYTES * nseg, nseg, MCLBYTES, 0, NULL, NULL,
1243 &sc->rl_ldata.rl_mtag);
1244 if (error) {
1245 device_printf(dev, "could not allocate dma tag\n");
1246 return (ENOMEM);
1247 }
1248
1249 /*
1250 * Allocate map for TX descriptor list.
1251 */
1252 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1253 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1254 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, 0, NULL, NULL,
1255 &sc->rl_ldata.rl_tx_list_tag);
1256 if (error) {
1257 device_printf(dev, "could not allocate dma tag\n");
1258 return (ENOMEM);
1259 }
1260
1261 /* Allocate DMA'able memory for the TX ring */
1262
1263 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
1264 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1265 &sc->rl_ldata.rl_tx_list_map);
1266 if (error)
1267 return (ENOMEM);
1268
1269 /* Load the map for the TX ring. */
1270
1271 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
1272 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
1273 RL_TX_LIST_SZ, rl_dma_map_addr,
1274 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1275
1276 /* Create DMA maps for TX buffers */
1277
1278 for (i = 0; i < RL_TX_DESC_CNT; i++) {
1279 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1280 &sc->rl_ldata.rl_tx_dmamap[i]);
1281 if (error) {
1282 device_printf(dev, "can't create DMA map for TX\n");
1283 return(ENOMEM);
1284 }
1285 }
1286
1287 /*
1288 * Allocate map for RX descriptor list.
1289 */
1290 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1291 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1292 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, 0, NULL, NULL,
1293 &sc->rl_ldata.rl_rx_list_tag);
1294 if (error) {
1295 device_printf(dev, "could not allocate dma tag\n");
1296 return (ENOMEM);
1297 }
1298
1299 /* Allocate DMA'able memory for the RX ring */
1300
1301 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1302 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1303 &sc->rl_ldata.rl_rx_list_map);
1304 if (error)
1305 return (ENOMEM);
1306
1307 /* Load the map for the RX ring. */
1308
1309 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1310 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1311 RL_TX_LIST_SZ, rl_dma_map_addr,
1312 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1313
1314 /* Create DMA maps for RX buffers */
1315
1316 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1317 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1318 &sc->rl_ldata.rl_rx_dmamap[i]);
1319 if (error) {
1320 device_printf(dev, "can't create DMA map for RX\n");
1321 return(ENOMEM);
1322 }
1323 }
1324
1325 return(0);
1326}
1327
1328/*
1329 * Attach the interface. Allocate softc structures, do ifmedia
1330 * setup and ethernet/BPF attach.
1331 */
1332static int
1333rl_attach(dev)
1334 device_t dev;
1335{
1336 u_char eaddr[ETHER_ADDR_LEN];
1337 u_int16_t as[3];
1338 struct rl_softc *sc;
1339 struct ifnet *ifp;
899 * Attach the interface. Allocate softc structures, do ifmedia
900 * setup and ethernet/BPF attach.
901 */
902static int
903rl_attach(dev)
904 device_t dev;
905{
906 u_char eaddr[ETHER_ADDR_LEN];
907 u_int16_t as[3];
908 struct rl_softc *sc;
909 struct ifnet *ifp;
1340 struct rl_type *t;
1341 struct rl_hwrev *hw_rev;
1342 int hwrev;
1343 u_int16_t rl_did = 0;
910 u_int16_t rl_did = 0;
911 struct rl_type *t;
1344 int unit, error = 0, rid, i;
1345
1346 sc = device_get_softc(dev);
1347 unit = device_get_unit(dev);
1348
1349 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1350 MTX_DEF | MTX_RECURSE);
1351#ifndef BURN_BRIDGES

--- 40 unchanged lines hidden (view full) ---

1392#ifdef notdef
1393 /* Detect the Realtek 8139B. For some reason, this chip is very
1394 * unstable when left to autoselect the media
1395 * The best workaround is to set the device to the required
1396 * media type or to set it to the 10 Meg speed.
1397 */
1398
1399 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) {
912 int unit, error = 0, rid, i;
913
914 sc = device_get_softc(dev);
915 unit = device_get_unit(dev);
916
917 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
918 MTX_DEF | MTX_RECURSE);
919#ifndef BURN_BRIDGES

--- 40 unchanged lines hidden (view full) ---

960#ifdef notdef
961 /* Detect the Realtek 8139B. For some reason, this chip is very
962 * unstable when left to autoselect the media
963 * The best workaround is to set the device to the required
964 * media type or to set it to the 10 Meg speed.
965 */
966
967 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) {
1400 printf("rl%d: Realtek 8139B detected. Warning,"
1401 " this may be unstable in autoselect mode\n", unit);
968 printf("rl%d: Realtek 8139B detected. Warning, "
969 "this may be unstable in autoselect mode\n", unit);
1402 }
1403#endif
1404
1405 sc->rl_btag = rman_get_bustag(sc->rl_res);
1406 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1407
1408 /* Allocate interrupt */
1409 rid = 0;

--- 32 unchanged lines hidden (view full) ---

1442
1443 /*
1444 * Now read the exact device type from the EEPROM to find
1445 * out if it's an 8129 or 8139.
1446 */
1447 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
1448
1449 t = rl_devs;
970 }
971#endif
972
973 sc->rl_btag = rman_get_bustag(sc->rl_res);
974 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
975
976 /* Allocate interrupt */
977 rid = 0;

--- 32 unchanged lines hidden (view full) ---

1010
1011 /*
1012 * Now read the exact device type from the EEPROM to find
1013 * out if it's an 8129 or 8139.
1014 */
1015 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
1016
1017 t = rl_devs;
1018 sc->rl_type = 0;
1450 while(t->rl_name != NULL) {
1451 if (rl_did == t->rl_did) {
1452 sc->rl_type = t->rl_basetype;
1453 break;
1454 }
1455 t++;
1456 }
1019 while(t->rl_name != NULL) {
1020 if (rl_did == t->rl_did) {
1021 sc->rl_type = t->rl_basetype;
1022 break;
1023 }
1024 t++;
1025 }
1457 if (t->rl_name == NULL) {
1026
1027 if (sc->rl_type == 0) {
1458 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
1459 error = ENXIO;
1460 goto fail;
1461 }
1028 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
1029 error = ENXIO;
1030 goto fail;
1031 }
1462 if (sc->rl_type == RL_8139) {
1463 hw_rev = rl_hwrevs;
1464 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
1465 while (hw_rev->rl_desc != NULL) {
1466 if (hw_rev->rl_rev == hwrev) {
1467 sc->rl_type = hw_rev->rl_type;
1468 break;
1469 }
1470 hw_rev++;
1471 }
1472 if (hw_rev->rl_desc == NULL) {
1473 printf("rl%d: unknown hwrev: %x\n", unit, hwrev);
1474 }
1475 } else if (rl_did == RT_DEVICEID_8129) {
1476 sc->rl_type = RL_8129;
1477 } else if (rl_did == RT_DEVICEID_8169) {
1478 sc->rl_type = RL_8169;
1479 }
1480
1481 /*
1482 * Allocate the parent bus DMA tag appropriate for PCI.
1483 */
1484#define RL_NSEG_NEW 32
1485 error = bus_dma_tag_create(NULL, /* parent */
1486 1, 0, /* alignment, boundary */
1487 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1488 BUS_SPACE_MAXADDR, /* highaddr */
1489 NULL, NULL, /* filter, filterarg */
1490 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
1491 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1492 BUS_DMA_ALLOCNOW, /* flags */
1493 NULL, NULL, /* lockfunc, lockarg */
1494 &sc->rl_parent_tag);
1495 if (error)
1496 goto fail;
1497
1498 /*
1032
1033 /*
1034 * Allocate the parent bus DMA tag appropriate for PCI.
1035 */
1036#define RL_NSEG_NEW 32
1037 error = bus_dma_tag_create(NULL, /* parent */
1038 1, 0, /* alignment, boundary */
1039 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1040 BUS_SPACE_MAXADDR, /* highaddr */
1041 NULL, NULL, /* filter, filterarg */
1042 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
1043 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1044 BUS_DMA_ALLOCNOW, /* flags */
1045 NULL, NULL, /* lockfunc, lockarg */
1046 &sc->rl_parent_tag);
1047 if (error)
1048 goto fail;
1049
1050 /*
1499 * If this is an 8139C+ or 8169 chip, we have to allocate
1500 * our busdma tags/memory differently. We need to allocate
1501 * a chunk of DMA'able memory for the RX and TX descriptor
1502 * lists.
1051 * Now allocate a tag for the DMA descriptor lists.
1052 * All of our lists are allocated as a contiguous block
1053 * of memory.
1503 */
1054 */
1504 if (sc->rl_type == RL_8139CPLUS || sc->rl_type == RL_8169)
1505 error = rl_allocmemcplus(dev, sc);
1506 else
1507 error = rl_allocmem(dev, sc);
1508
1055 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
1056 1, 0, /* alignment, boundary */
1057 BUS_SPACE_MAXADDR, /* lowaddr */
1058 BUS_SPACE_MAXADDR, /* highaddr */
1059 NULL, NULL, /* filter, filterarg */
1060 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */
1061 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1062 BUS_DMA_ALLOCNOW, /* flags */
1063 NULL, NULL, /* lockfunc, lockarg */
1064 &sc->rl_tag);
1509 if (error)
1510 goto fail;
1511
1065 if (error)
1066 goto fail;
1067
1068 /*
1069 * Now allocate a chunk of DMA-able memory based on the
1070 * tag we just created.
1071 */
1072 error = bus_dmamem_alloc(sc->rl_tag,
1073 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1074 &sc->rl_cdata.rl_rx_dmamap);
1075
1076 if (error) {
1077 printf("rl%d: no memory for list buffers!\n", unit);
1078 bus_dma_tag_destroy(sc->rl_tag);
1079 sc->rl_tag = NULL;
1080 goto fail;
1081 }
1082
1083 /* Leave a few bytes before the start of the RX ring buffer. */
1084 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1085 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
1086
1512 /* Do MII setup */
1513 if (mii_phy_probe(dev, &sc->rl_miibus,
1514 rl_ifmedia_upd, rl_ifmedia_sts)) {
1515 printf("rl%d: MII without any phy!\n", sc->rl_unit);
1516 error = ENXIO;
1517 goto fail;
1518 }
1519
1520 ifp = &sc->arpcom.ac_if;
1521 ifp->if_softc = sc;
1522 ifp->if_unit = unit;
1523 ifp->if_name = "rl";
1524 ifp->if_mtu = ETHERMTU;
1525 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1526 ifp->if_ioctl = rl_ioctl;
1527 ifp->if_output = ether_output;
1087 /* Do MII setup */
1088 if (mii_phy_probe(dev, &sc->rl_miibus,
1089 rl_ifmedia_upd, rl_ifmedia_sts)) {
1090 printf("rl%d: MII without any phy!\n", sc->rl_unit);
1091 error = ENXIO;
1092 goto fail;
1093 }
1094
1095 ifp = &sc->arpcom.ac_if;
1096 ifp->if_softc = sc;
1097 ifp->if_unit = unit;
1098 ifp->if_name = "rl";
1099 ifp->if_mtu = ETHERMTU;
1100 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1101 ifp->if_ioctl = rl_ioctl;
1102 ifp->if_output = ether_output;
1528 ifp->if_capabilities = IFCAP_VLAN_MTU;
1529 if (RL_ISCPLUS(sc)) {
1530 ifp->if_start = rl_startcplus;
1531 ifp->if_hwassist = RL_CSUM_FEATURES;
1532 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1533 } else
1534 ifp->if_start = rl_start;
1103 ifp->if_start = rl_start;
1535 ifp->if_watchdog = rl_watchdog;
1536 ifp->if_init = rl_init;
1537 ifp->if_baudrate = 10000000;
1104 ifp->if_watchdog = rl_watchdog;
1105 ifp->if_init = rl_init;
1106 ifp->if_baudrate = 10000000;
1538 ifp->if_snd.ifq_maxlen = RL_IFQ_MAXLEN;
1539 ifp->if_capenable = ifp->if_capabilities;
1107 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1540
1541 callout_handle_init(&sc->rl_stat_ch);
1542
1543 /*
1544 * Call MI attach routine.
1545 */
1546 ether_ifattach(ifp, eaddr);
1547
1548 /* Hook interrupt last to avoid having to lock softc */
1549 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET,
1108
1109 callout_handle_init(&sc->rl_stat_ch);
1110
1111 /*
1112 * Call MI attach routine.
1113 */
1114 ether_ifattach(ifp, eaddr);
1115
1116 /* Hook interrupt last to avoid having to lock softc */
1117 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET,
1550 RL_ISCPLUS(sc) ? rl_intrcplus : rl_intr, sc, &sc->rl_intrhand);
1118 rl_intr, sc, &sc->rl_intrhand);
1551
1552 if (error) {
1553 printf("rl%d: couldn't set up irq\n", unit);
1554 ether_ifdetach(ifp);
1555 goto fail;
1556 }
1557
1558fail:

--- 11 unchanged lines hidden (view full) ---

1570 * allocated.
1571 */
1572static int
1573rl_detach(dev)
1574 device_t dev;
1575{
1576 struct rl_softc *sc;
1577 struct ifnet *ifp;
1119
1120 if (error) {
1121 printf("rl%d: couldn't set up irq\n", unit);
1122 ether_ifdetach(ifp);
1123 goto fail;
1124 }
1125
1126fail:

--- 11 unchanged lines hidden (view full) ---

1138 * allocated.
1139 */
1140static int
1141rl_detach(dev)
1142 device_t dev;
1143{
1144 struct rl_softc *sc;
1145 struct ifnet *ifp;
1578 int i;
1579
1580 sc = device_get_softc(dev);
1581 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
1582 RL_LOCK(sc);
1583 ifp = &sc->arpcom.ac_if;
1584
1585 /* These should only be active if attach succeeded */
1586 if (device_is_attached(dev)) {

--- 6 unchanged lines hidden (view full) ---

1593
1594 if (sc->rl_intrhand)
1595 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1596 if (sc->rl_irq)
1597 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1598 if (sc->rl_res)
1599 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1600
1146
1147 sc = device_get_softc(dev);
1148 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
1149 RL_LOCK(sc);
1150 ifp = &sc->arpcom.ac_if;
1151
1152 /* These should only be active if attach succeeded */
1153 if (device_is_attached(dev)) {

--- 6 unchanged lines hidden (view full) ---

1160
1161 if (sc->rl_intrhand)
1162 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1163 if (sc->rl_irq)
1164 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1165 if (sc->rl_res)
1166 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1167
1601 if (RL_ISCPLUS(sc)) {
1602
1603 /* Unload and free the RX DMA ring memory and map */
1604
1605 if (sc->rl_ldata.rl_rx_list_tag) {
1606 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1607 sc->rl_ldata.rl_rx_list_map);
1608 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1609 sc->rl_ldata.rl_rx_list,
1610 sc->rl_ldata.rl_rx_list_map);
1611 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1612 }
1613
1614 /* Unload and free the TX DMA ring memory and map */
1615
1616 if (sc->rl_ldata.rl_tx_list_tag) {
1617 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1618 sc->rl_ldata.rl_tx_list_map);
1619 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1620 sc->rl_ldata.rl_tx_list,
1621 sc->rl_ldata.rl_tx_list_map);
1622 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1623 }
1624
1625 /* Destroy all the RX and TX buffer maps */
1626
1627 if (sc->rl_ldata.rl_mtag) {
1628 for (i = 0; i < RL_TX_DESC_CNT; i++)
1629 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1630 sc->rl_ldata.rl_tx_dmamap[i]);
1631 for (i = 0; i < RL_RX_DESC_CNT; i++)
1632 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1633 sc->rl_ldata.rl_rx_dmamap[i]);
1634 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag);
1635 }
1636
1637 /* Unload and free the stats buffer and map */
1638
1639 if (sc->rl_ldata.rl_stag) {
1640 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1641 sc->rl_ldata.rl_rx_list_map);
1642 bus_dmamem_free(sc->rl_ldata.rl_stag,
1643 sc->rl_ldata.rl_stats,
1644 sc->rl_ldata.rl_smap);
1645 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1646 }
1647
1648 } else {
1649 if (sc->rl_tag) {
1650 bus_dmamap_unload(sc->rl_tag,
1651 sc->rl_cdata.rl_rx_dmamap);
1652 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
1653 sc->rl_cdata.rl_rx_dmamap);
1654 bus_dma_tag_destroy(sc->rl_tag);
1655 }
1168 if (sc->rl_tag) {
1169 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1170 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
1171 sc->rl_cdata.rl_rx_dmamap);
1172 bus_dma_tag_destroy(sc->rl_tag);
1656 }
1173 }
1657
1658 if (sc->rl_parent_tag)
1659 bus_dma_tag_destroy(sc->rl_parent_tag);
1660
1661 RL_UNLOCK(sc);
1662 mtx_destroy(&sc->rl_mtx);
1663
1664 return(0);
1665}

--- 16 unchanged lines hidden (view full) ---

1682 }
1683
1684 sc->rl_cdata.cur_tx = 0;
1685 sc->rl_cdata.last_tx = 0;
1686
1687 return(0);
1688}
1689
1174 if (sc->rl_parent_tag)
1175 bus_dma_tag_destroy(sc->rl_parent_tag);
1176
1177 RL_UNLOCK(sc);
1178 mtx_destroy(&sc->rl_mtx);
1179
1180 return(0);
1181}

--- 16 unchanged lines hidden (view full) ---

1198 }
1199
1200 sc->rl_cdata.cur_tx = 0;
1201 sc->rl_cdata.last_tx = 0;
1202
1203 return(0);
1204}
1205
1690static int
1691rl_newbuf (sc, idx, m)
1692 struct rl_softc *sc;
1693 int idx;
1694 struct mbuf *m;
1695{
1696 struct rl_dmaload_arg arg;
1697 struct mbuf *n = NULL;
1698 int error;
1699
1700 if (m == NULL) {
1701 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1702 if (n == NULL)
1703 return(ENOBUFS);
1704 m = n;
1705 } else
1706 m->m_data = m->m_ext.ext_buf;
1707
1708 /*
1709 * Initialize mbuf length fields and fixup
1710 * alignment so that the frame payload is
1711 * longword aligned.
1712 */
1713 m->m_len = m->m_pkthdr.len = 1536;
1714 m_adj(m, ETHER_ALIGN);
1715
1716 arg.sc = sc;
1717 arg.rl_idx = idx;
1718 arg.rl_maxsegs = 1;
1719 arg.rl_flags = 0;
1720 arg.rl_ring = sc->rl_ldata.rl_rx_list;
1721
1722 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag,
1723 sc->rl_ldata.rl_rx_dmamap[idx], m, rl_dma_map_desc,
1724 &arg, BUS_DMA_NOWAIT);
1725 if (error || arg.rl_maxsegs != 1) {
1726 if (n != NULL)
1727 m_freem(n);
1728 return (ENOMEM);
1729 }
1730
1731 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN);
1732 sc->rl_ldata.rl_rx_mbuf[idx] = m;
1733
1734 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1735 sc->rl_ldata.rl_rx_dmamap[idx],
1736 BUS_DMASYNC_PREREAD);
1737
1738 return(0);
1739}
1740
1741static int
1742rl_tx_list_init(sc)
1743 struct rl_softc *sc;
1744{
1745 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ);
1746 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf,
1747 (RL_TX_DESC_CNT * sizeof(struct mbuf *)));
1748
1749 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1750 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE);
1751 sc->rl_ldata.rl_tx_prodidx = 0;
1752 sc->rl_ldata.rl_tx_considx = 0;
1753 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT;
1754
1755 return(0);
1756}
1757
1758static int
1759rl_rx_list_init(sc)
1760 struct rl_softc *sc;
1761{
1762 int i;
1763
1764 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ);
1765 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf,
1766 (RL_RX_DESC_CNT * sizeof(struct mbuf *)));
1767
1768 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1769 if (rl_newbuf(sc, i, NULL) == ENOBUFS)
1770 return(ENOBUFS);
1771 }
1772
1773 /* Flush the RX descriptors */
1774
1775 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1776 sc->rl_ldata.rl_rx_list_map,
1777 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1778
1779 sc->rl_ldata.rl_rx_prodidx = 0;
1780
1781 return(0);
1782}
1783
1784/*
1206/*
1785 * RX handler for C+. This is pretty much like any other
1786 * descriptor-based RX handler.
1787 */
1788static void
1789rl_rxeofcplus(sc)
1790 struct rl_softc *sc;
1791{
1792 struct mbuf *m;
1793 struct ifnet *ifp;
1794 int i, total_len;
1795 struct rl_desc *cur_rx;
1796 u_int32_t rxstat, rxvlan;
1797
1798 ifp = &sc->arpcom.ac_if;
1799 i = sc->rl_ldata.rl_rx_prodidx;
1800
1801 /* Invalidate the descriptor memory */
1802
1803 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1804 sc->rl_ldata.rl_rx_list_map,
1805 BUS_DMASYNC_POSTREAD);
1806
1807 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) {
1808
1809 cur_rx = &sc->rl_ldata.rl_rx_list[i];
1810 m = sc->rl_ldata.rl_rx_mbuf[i];
1811 total_len = RL_RXBYTES(cur_rx) - ETHER_CRC_LEN;
1812 rxstat = le32toh(cur_rx->rl_cmdstat);
1813 rxvlan = le32toh(cur_rx->rl_vlanctl);
1814
1815 /* Invalidate the RX mbuf and unload its map */
1816
1817 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1818 sc->rl_ldata.rl_rx_dmamap[i],
1819 BUS_DMASYNC_POSTREAD);
1820 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1821 sc->rl_ldata.rl_rx_dmamap[i]);
1822
1823 /*
1824 * NOTE: For some reason that I can't comprehend,
1825 * the RealTek engineers decided not to implement
1826 * the 'frame alignment error' bit in the 8169's
1827 * status word. Unfortunately, rather than simply
1828 * mark the bit as 'reserved,' they took it away
1829 * completely and shifted the other status bits
1830 * over one slot. The OWN, EOR, FS and LS bits are
1831 * still in the same places, as is the frame length
1832 * field. We have already extracted the frame length
1833 * and checked the OWN bit, so to work around this
1834 * problem, we shift the status bits one space to
1835 * the right so that we can evaluate everything else
1836 * correctly.
1837 */
1838 if (sc->rl_type == RL_8169)
1839 rxstat >>= 1;
1840
1841 if (rxstat & RL_RDESC_STAT_RXERRSUM) {
1842 ifp->if_ierrors++;
1843 rl_newbuf(sc, i, m);
1844 RL_DESC_INC(i);
1845 continue;
1846 }
1847
1848 /*
1849 * If allocating a replacement mbuf fails,
1850 * reload the current one.
1851 */
1852
1853 if (rl_newbuf(sc, i, NULL)) {
1854 ifp->if_ierrors++;
1855 rl_newbuf(sc, i, m);
1856 RL_DESC_INC(i);
1857 continue;
1858 }
1859
1860 RL_DESC_INC(i);
1861
1862 ifp->if_ipackets++;
1863 m->m_pkthdr.len = m->m_len = total_len;
1864 m->m_pkthdr.rcvif = ifp;
1865
1866 /* Do RX checksumming if enabled */
1867
1868 if (ifp->if_capenable & IFCAP_RXCSUM) {
1869
1870 /* Check IP header checksum */
1871 if (rxstat & RL_RDESC_STAT_PROTOID)
1872 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1873 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
1874 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1875
1876 /* Check TCP/UDP checksum */
1877 if ((RL_TCPPKT(rxstat) &&
1878 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
1879 (RL_UDPPKT(rxstat) &&
1880 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
1881 m->m_pkthdr.csum_flags |=
1882 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1883 m->m_pkthdr.csum_data = 0xffff;
1884 }
1885 }
1886
1887 if (rxvlan & RL_RDESC_VLANCTL_TAG)
1888 VLAN_INPUT_TAG(ifp, m,
1889 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue);
1890 (*ifp->if_input)(ifp, m);
1891 }
1892
1893 /* Flush the RX DMA ring */
1894
1895 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1896 sc->rl_ldata.rl_rx_list_map,
1897 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1898
1899 sc->rl_ldata.rl_rx_prodidx = i;
1900
1901 return;
1902}
1903
1904/*
1905 * A frame has been uploaded: pass the resulting mbuf chain up to
1906 * the higher level protocols.
1907 *
1908 * You know there's something wrong with a PCI bus-master chip design
1909 * when you have to use m_devget().
1910 *
1911 * The receive operation is badly documented in the datasheet, so I'll
1912 * attempt to document it here. The driver provides a buffer area and

--- 124 unchanged lines hidden (view full) ---

2037
2038 ifp->if_ipackets++;
2039 (*ifp->if_input)(ifp, m);
2040 }
2041
2042 return;
2043}
2044
1207 * A frame has been uploaded: pass the resulting mbuf chain up to
1208 * the higher level protocols.
1209 *
1210 * You know there's something wrong with a PCI bus-master chip design
1211 * when you have to use m_devget().
1212 *
1213 * The receive operation is badly documented in the datasheet, so I'll
1214 * attempt to document it here. The driver provides a buffer area and

--- 124 unchanged lines hidden (view full) ---

1339
1340 ifp->if_ipackets++;
1341 (*ifp->if_input)(ifp, m);
1342 }
1343
1344 return;
1345}
1346
2045static void
2046rl_txeofcplus(sc)
2047 struct rl_softc *sc;
2048{
2049 struct ifnet *ifp;
2050 u_int32_t txstat;
2051 int idx;
2052
2053 ifp = &sc->arpcom.ac_if;
2054 idx = sc->rl_ldata.rl_tx_considx;
2055
2056 /* Invalidate the TX descriptor list */
2057
2058 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2059 sc->rl_ldata.rl_tx_list_map,
2060 BUS_DMASYNC_POSTREAD);
2061
2062 while (idx != sc->rl_ldata.rl_tx_prodidx) {
2063
2064 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat);
2065 if (txstat & RL_TDESC_CMD_OWN)
2066 break;
2067
2068 /*
2069 * We only stash mbufs in the last descriptor
2070 * in a fragment chain, which also happens to
2071 * be the only place where the TX status bits
2072 * are valid.
2073 */
2074
2075 if (txstat & RL_TDESC_CMD_EOF) {
2076 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]);
2077 sc->rl_ldata.rl_tx_mbuf[idx] = NULL;
2078 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2079 sc->rl_ldata.rl_tx_dmamap[idx]);
2080 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
2081 RL_TDESC_STAT_COLCNT))
2082 ifp->if_collisions++;
2083 if (txstat & RL_TDESC_STAT_TXERRSUM)
2084 ifp->if_oerrors++;
2085 else
2086 ifp->if_opackets++;
2087 }
2088 sc->rl_ldata.rl_tx_free++;
2089 RL_DESC_INC(idx);
2090 }
2091
2092 /* No changes made to the TX ring, so no flush needed */
2093
2094 if (idx != sc->rl_ldata.rl_tx_considx) {
2095 sc->rl_ldata.rl_tx_considx = idx;
2096 ifp->if_flags &= ~IFF_OACTIVE;
2097 ifp->if_timer = 0;
2098 }
2099
2100 return;
2101}
2102
2103/*
2104 * A frame was downloaded to the chip. It's safe for us to clean up
2105 * the list buffers.
2106 */
2107static void
2108rl_txeof(sc)
2109 struct rl_softc *sc;
2110{

--- 72 unchanged lines hidden (view full) ---

2183#ifdef DEVICE_POLLING
2184static void
2185rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count)
2186{
2187 struct rl_softc *sc = ifp->if_softc;
2188
2189 RL_LOCK(sc);
2190 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1347/*
1348 * A frame was downloaded to the chip. It's safe for us to clean up
1349 * the list buffers.
1350 */
1351static void
1352rl_txeof(sc)
1353 struct rl_softc *sc;
1354{

--- 72 unchanged lines hidden (view full) ---

1427#ifdef DEVICE_POLLING
1428static void
1429rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count)
1430{
1431 struct rl_softc *sc = ifp->if_softc;
1432
1433 RL_LOCK(sc);
1434 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
2191 if (RL_ISCPLUS(sc))
2192 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2193 else
2194 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1435 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
2195 goto done;
2196 }
2197
2198 sc->rxcycles = count;
1436 goto done;
1437 }
1438
1439 sc->rxcycles = count;
2199 if (RL_ISCPLUS(sc)) {
2200 rl_rxeofcplus(sc);
2201 rl_txeofcplus(sc);
2202 } else {
2203 rl_rxeof(sc);
2204 rl_txeof(sc);
2205 }
2206
1440 rl_rxeof(sc);
1441 rl_txeof(sc);
2207 if (ifp->if_snd.ifq_head != NULL)
1442 if (ifp->if_snd.ifq_head != NULL)
2208 (*ifp->if_start)(ifp);
1443 rl_start(ifp);
2209
2210 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2211 u_int16_t status;
2212
2213 status = CSR_READ_2(sc, RL_ISR);
2214 if (status == 0xffff)
2215 goto done;
2216 if (status)

--- 9 unchanged lines hidden (view full) ---

2226 }
2227 }
2228done:
2229 RL_UNLOCK(sc);
2230}
2231#endif /* DEVICE_POLLING */
2232
2233static void
1444
1445 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1446 u_int16_t status;
1447
1448 status = CSR_READ_2(sc, RL_ISR);
1449 if (status == 0xffff)
1450 goto done;
1451 if (status)

--- 9 unchanged lines hidden (view full) ---

1461 }
1462 }
1463done:
1464 RL_UNLOCK(sc);
1465}
1466#endif /* DEVICE_POLLING */
1467
1468static void
2234rl_intrcplus(arg)
2235 void *arg;
2236{
2237 struct rl_softc *sc;
2238 struct ifnet *ifp;
2239 u_int16_t status;
2240
2241 sc = arg;
2242
2243 if (sc->suspended) {
2244 return;
2245 }
2246
2247 RL_LOCK(sc);
2248 ifp = &sc->arpcom.ac_if;
2249
2250#ifdef DEVICE_POLLING
2251 if (ifp->if_flags & IFF_POLLING)
2252 goto done;
2253 if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */
2254 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2255 rl_poll(ifp, 0, 1);
2256 goto done;
2257 }
2258#endif /* DEVICE_POLLING */
2259
2260 for (;;) {
2261
2262 status = CSR_READ_2(sc, RL_ISR);
2263 /* If the card has gone away the read returns 0xffff. */
2264 if (status == 0xffff)
2265 break;
2266 if (status)
2267 CSR_WRITE_2(sc, RL_ISR, status);
2268
2269 if ((status & RL_INTRS_CPLUS) == 0)
2270 break;
2271
2272 if (status & RL_ISR_RX_OK)
2273 rl_rxeofcplus(sc);
2274
2275 if (status & RL_ISR_RX_ERR)
2276 rl_rxeofcplus(sc);
2277
2278 if ((status & RL_ISR_TIMEOUT_EXPIRED) ||
2279 (status & RL_ISR_TX_ERR) ||
2280 (status & RL_ISR_TX_DESC_UNAVAIL))
2281 rl_txeofcplus(sc);
2282
2283 if (status & RL_ISR_SYSTEM_ERR) {
2284 rl_reset(sc);
2285 rl_init(sc);
2286 }
2287
2288 }
2289
2290 if (ifp->if_snd.ifq_head != NULL)
2291 (*ifp->if_start)(ifp);
2292
2293#ifdef DEVICE_POLLING
2294done:
2295#endif
2296 RL_UNLOCK(sc);
2297
2298 return;
2299}
2300
2301static void
2302rl_intr(arg)
2303 void *arg;
2304{
2305 struct rl_softc *sc;
2306 struct ifnet *ifp;
2307 u_int16_t status;
2308
2309 sc = arg;

--- 39 unchanged lines hidden (view full) ---

2349 if (status & RL_ISR_SYSTEM_ERR) {
2350 rl_reset(sc);
2351 rl_init(sc);
2352 }
2353
2354 }
2355
2356 if (ifp->if_snd.ifq_head != NULL)
1469rl_intr(arg)
1470 void *arg;
1471{
1472 struct rl_softc *sc;
1473 struct ifnet *ifp;
1474 u_int16_t status;
1475
1476 sc = arg;

--- 39 unchanged lines hidden (view full) ---

1516 if (status & RL_ISR_SYSTEM_ERR) {
1517 rl_reset(sc);
1518 rl_init(sc);
1519 }
1520
1521 }
1522
1523 if (ifp->if_snd.ifq_head != NULL)
2357 (*ifp->if_start)(ifp);
1524 rl_start(ifp);
2358
2359#ifdef DEVICE_POLLING
2360done:
2361#endif
2362 RL_UNLOCK(sc);
2363
2364 return;
2365}
2366
1525
1526#ifdef DEVICE_POLLING
1527done:
1528#endif
1529 RL_UNLOCK(sc);
1530
1531 return;
1532}
1533
2367static int
2368rl_encapcplus(sc, m_head, idx)
2369 struct rl_softc *sc;
2370 struct mbuf *m_head;
2371 int *idx;
2372{
2373 struct mbuf *m_new = NULL;
2374 struct rl_dmaload_arg arg;
2375 bus_dmamap_t map;
2376 int error;
2377 struct m_tag *mtag;
2378
2379 if (sc->rl_ldata.rl_tx_free < 4)
2380 return(EFBIG);
2381
2382 /*
2383 * Set up checksum offload. Note: checksum offload bits must
2384 * appear in all descriptors of a multi-descriptor transmit
2385 * attempt. (This is according to testing done with an 8169
2386 * chip. I'm not sure if this is a requirement or a bug.)
2387 */
2388
2389 arg.rl_flags = 0;
2390
2391 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2392 arg.rl_flags |= RL_TDESC_CMD_IPCSUM;
2393 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
2394 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM;
2395 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
2396 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM;
2397
2398 arg.sc = sc;
2399 arg.rl_idx = *idx;
2400 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
2401 arg.rl_ring = sc->rl_ldata.rl_tx_list;
2402
2403 map = sc->rl_ldata.rl_tx_dmamap[*idx];
2404 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
2405 m_head, rl_dma_map_desc, &arg, BUS_DMA_NOWAIT);
2406
2407 if (error && error != EFBIG) {
2408 printf("rl%d: can't map mbuf (error %d)\n", sc->rl_unit, error);
2409 return(ENOBUFS);
2410 }
2411
2412 /* Too many segments to map, coalesce into a single mbuf */
2413
2414 if (error || arg.rl_maxsegs == 0) {
2415 m_new = m_defrag(m_head, M_DONTWAIT);
2416 if (m_new == NULL)
2417 return(1);
2418 else
2419 m_head = m_new;
2420
2421 arg.sc = sc;
2422 arg.rl_idx = *idx;
2423 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
2424 arg.rl_ring = sc->rl_ldata.rl_tx_list;
2425
2426 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
2427 m_head, rl_dma_map_desc, &arg, BUS_DMA_NOWAIT);
2428 if (error) {
2429 printf("rl%d: can't map mbuf (error %d)\n",
2430 sc->rl_unit, error);
2431 return(EFBIG);
2432 }
2433 }
2434
2435 /*
2436 * Insure that the map for this transmission
2437 * is placed at the array index of the last descriptor
2438 * in this chain.
2439 */
2440 sc->rl_ldata.rl_tx_dmamap[*idx] =
2441 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx];
2442 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map;
2443
2444 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = m_head;
2445 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs;
2446
2447 /*
2448 * Set up hardware VLAN tagging. Note: vlan tag info must
2449 * appear in the first descriptor of a multi-descriptor
2450 * transmission attempt.
2451 */
2452
2453 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head);
2454 if (mtag != NULL)
2455 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl =
2456 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG);
2457
2458 /* Transfer ownership of packet to the chip. */
2459
2460 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |=
2461 htole32(RL_TDESC_CMD_OWN);
2462 if (*idx != arg.rl_idx)
2463 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |=
2464 htole32(RL_TDESC_CMD_OWN);
2465
2466 RL_DESC_INC(arg.rl_idx);
2467 *idx = arg.rl_idx;
2468
2469 return(0);
2470}
2471
2472/*
1534/*
2473 * Main transmit routine for C+ and gigE NICs.
2474 */
2475
2476static void
2477rl_startcplus(ifp)
2478 struct ifnet *ifp;
2479{
2480 struct rl_softc *sc;
2481 struct mbuf *m_head = NULL;
2482 int idx;
2483
2484 sc = ifp->if_softc;
2485 RL_LOCK(sc);
2486
2487 idx = sc->rl_ldata.rl_tx_prodidx;
2488
2489 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) {
2490 IF_DEQUEUE(&ifp->if_snd, m_head);
2491 if (m_head == NULL)
2492 break;
2493
2494 if (rl_encapcplus(sc, m_head, &idx)) {
2495 IF_PREPEND(&ifp->if_snd, m_head);
2496 ifp->if_flags |= IFF_OACTIVE;
2497 break;
2498 }
2499
2500 /*
2501 * If there's a BPF listener, bounce a copy of this frame
2502 * to him.
2503 */
2504 BPF_MTAP(ifp, m_head);
2505 }
2506
2507 /* Flush the TX descriptors */
2508
2509 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2510 sc->rl_ldata.rl_tx_list_map,
2511 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2512
2513 sc->rl_ldata.rl_tx_prodidx = idx;
2514
2515 /*
2516 * RealTek put the TX poll request register in a different
2517 * location on the 8169 gigE chip. I don't know why.
2518 */
2519
2520 if (sc->rl_type == RL_8169)
2521 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START);
2522 else
2523 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START);
2524
2525 /*
2526 * Use the countdown timer for interrupt moderation.
2527 * 'TX done' interrupts are disabled. Instead, we reset the
2528 * countdown timer, which will begin counting until it hits
2529 * the value in the TIMERINT register, and then trigger an
2530 * interrupt. Each time we write to the TIMERCNT register,
2531 * the timer count is reset to 0.
2532 */
2533 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2534
2535 RL_UNLOCK(sc);
2536
2537 /*
2538 * Set a timeout in case the chip goes out to lunch.
2539 */
2540 ifp->if_timer = 5;
2541
2542 return;
2543}
2544
2545/*
2546 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2547 * pointers to the fragment pointers.
2548 */
2549static int
2550rl_encap(sc, m_head)
2551 struct rl_softc *sc;
2552 struct mbuf *m_head;
2553{

--- 62 unchanged lines hidden (view full) ---

2616 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
2617
2618 /*
2619 * Transmit the frame.
2620 */
2621 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
2622 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
2623 mtod(RL_CUR_TXMBUF(sc), void *),
1535 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1536 * pointers to the fragment pointers.
1537 */
1538static int
1539rl_encap(sc, m_head)
1540 struct rl_softc *sc;
1541 struct mbuf *m_head;
1542{

--- 62 unchanged lines hidden (view full) ---

1605 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1606
1607 /*
1608 * Transmit the frame.
1609 */
1610 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1611 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1612 mtod(RL_CUR_TXMBUF(sc), void *),
2624 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf,
2625 sc, BUS_DMA_NOWAIT);
1613 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0);
2626 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
2627 BUS_DMASYNC_PREREAD);
2628 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
2629 RL_TXTHRESH(sc->rl_txthresh) |
2630 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
2631
2632 RL_INC(sc->rl_cdata.cur_tx);
2633

--- 40 unchanged lines hidden (view full) ---

2674 */
2675 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2676 CSR_WRITE_STREAM_4(sc, RL_IDR0,
2677 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
2678 CSR_WRITE_STREAM_4(sc, RL_IDR4,
2679 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
2680 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2681
1614 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1615 BUS_DMASYNC_PREREAD);
1616 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1617 RL_TXTHRESH(sc->rl_txthresh) |
1618 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1619
1620 RL_INC(sc->rl_cdata.cur_tx);
1621

--- 40 unchanged lines hidden (view full) ---

1662 */
1663 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1664 CSR_WRITE_STREAM_4(sc, RL_IDR0,
1665 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1666 CSR_WRITE_STREAM_4(sc, RL_IDR4,
1667 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1668 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1669
2682 /*
2683 * For C+ mode, initialize the RX descriptors and mbufs.
2684 */
2685 if (RL_ISCPLUS(sc)) {
2686 rl_rx_list_init(sc);
2687 rl_tx_list_init(sc);
2688 } else {
1670 /* Init the RX buffer pointer register. */
1671 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1672 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0);
1673 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1674 BUS_DMASYNC_PREWRITE);
2689
1675
2690 /* Init the RX buffer pointer register. */
2691 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
2692 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN,
2693 rl_dma_map_rxbuf, sc, BUS_DMA_NOWAIT);
2694 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
2695 BUS_DMASYNC_PREWRITE);
1676 /* Init TX descriptors. */
1677 rl_list_tx_init(sc);
2696
1678
2697 /* Init TX descriptors. */
2698 rl_list_tx_init(sc);
2699 }
2700
2701 /*
2702 * Enable transmit and receive.
2703 */
2704 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2705
2706 /*
2707 * Set the initial TX and RX configuration.
2708 */

--- 35 unchanged lines hidden (view full) ---

2744 */
2745 if (ifp->if_flags & IFF_POLLING)
2746 CSR_WRITE_2(sc, RL_IMR, 0);
2747 else /* otherwise ... */
2748#endif /* DEVICE_POLLING */
2749 /*
2750 * Enable interrupts.
2751 */
1679 /*
1680 * Enable transmit and receive.
1681 */
1682 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1683
1684 /*
1685 * Set the initial TX and RX configuration.
1686 */

--- 35 unchanged lines hidden (view full) ---

1722 */
1723 if (ifp->if_flags & IFF_POLLING)
1724 CSR_WRITE_2(sc, RL_IMR, 0);
1725 else /* otherwise ... */
1726#endif /* DEVICE_POLLING */
1727 /*
1728 * Enable interrupts.
1729 */
2752 if (RL_ISCPLUS(sc))
2753 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2754 else
2755 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1730 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
2756
2757 /* Set initial TX threshold */
2758 sc->rl_txthresh = RL_TX_THRESH_INIT;
2759
2760 /* Start RX/TX process. */
2761 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1731
1732 /* Set initial TX threshold */
1733 sc->rl_txthresh = RL_TX_THRESH_INIT;
1734
1735 /* Start RX/TX process. */
1736 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
2762#ifdef notdef
1737
2763 /* Enable receiver and transmitter. */
2764 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1738 /* Enable receiver and transmitter. */
1739 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2765#endif
2766 /*
2767 * If this is a C+ capable chip, enable C+ RX and TX mode,
2768 * and load the addresses of the RX and TX lists into the chip.
2769 */
2770 if (RL_ISCPLUS(sc)) {
2771 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB|
2772 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW|
2773 RL_CPLUSCMD_VLANSTRIP|
2774 (ifp->if_capenable & IFCAP_RXCSUM ?
2775 RL_CPLUSCMD_RXCSUM_ENB : 0));
2776
1740
2777 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
2778 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
2779 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
2780 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
2781
2782 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
2783 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
2784 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
2785 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
2786
2787 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, RL_EARLYTXTHRESH_CNT);
2788
2789 /*
2790 * Initialize the timer interrupt register so that
2791 * a timer interrupt will be generated once the timer
2792 * reaches a certain number of ticks. The timer is
2793 * reloaded on each transmit. This gives us TX interrupt
2794 * moderation, which dramatically improves TX frame rate.
2795 */
2796
2797 if (sc->rl_type == RL_8169)
2798 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
2799 else
2800 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
2801
2802 /*
2803 * For 8169 gigE NICs, set the max allowed RX packet
2804 * size so we can receive jumbo frames.
2805 */
2806 if (sc->rl_type == RL_8169)
2807 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RL_PKTSZ(16384));
2808
2809 }
2810
2811 mii_mediachg(mii);
2812
2813 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
2814
2815 ifp->if_flags |= IFF_RUNNING;
2816 ifp->if_flags &= ~IFF_OACTIVE;
2817
2818 sc->rl_stat_ch = timeout(rl_tick, sc, hz);

--- 68 unchanged lines hidden (view full) ---

2887 rl_setmulti(sc);
2888 error = 0;
2889 break;
2890 case SIOCGIFMEDIA:
2891 case SIOCSIFMEDIA:
2892 mii = device_get_softc(sc->rl_miibus);
2893 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2894 break;
1741 mii_mediachg(mii);
1742
1743 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1744
1745 ifp->if_flags |= IFF_RUNNING;
1746 ifp->if_flags &= ~IFF_OACTIVE;
1747
1748 sc->rl_stat_ch = timeout(rl_tick, sc, hz);

--- 68 unchanged lines hidden (view full) ---

1817 rl_setmulti(sc);
1818 error = 0;
1819 break;
1820 case SIOCGIFMEDIA:
1821 case SIOCSIFMEDIA:
1822 mii = device_get_softc(sc->rl_miibus);
1823 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1824 break;
2895 case SIOCSIFCAP:
2896 ifp->if_capenable = ifr->ifr_reqcap;
2897 if (ifp->if_capenable & IFCAP_TXCSUM)
2898 ifp->if_hwassist = RL_CSUM_FEATURES;
2899 else
2900 ifp->if_hwassist = 0;
2901 if (ifp->if_flags & IFF_RUNNING)
2902 rl_init(sc);
2903 break;
2904 default:
2905 error = ether_ioctl(ifp, command, data);
2906 break;
2907 }
2908
2909 RL_UNLOCK(sc);
2910
2911 return(error);

--- 5 unchanged lines hidden (view full) ---

2917{
2918 struct rl_softc *sc;
2919
2920 sc = ifp->if_softc;
2921 RL_LOCK(sc);
2922 printf("rl%d: watchdog timeout\n", sc->rl_unit);
2923 ifp->if_oerrors++;
2924
1825 default:
1826 error = ether_ioctl(ifp, command, data);
1827 break;
1828 }
1829
1830 RL_UNLOCK(sc);
1831
1832 return(error);

--- 5 unchanged lines hidden (view full) ---

1838{
1839 struct rl_softc *sc;
1840
1841 sc = ifp->if_softc;
1842 RL_LOCK(sc);
1843 printf("rl%d: watchdog timeout\n", sc->rl_unit);
1844 ifp->if_oerrors++;
1845
2925 if (RL_ISCPLUS(sc)) {
2926 rl_txeofcplus(sc);
2927 rl_rxeofcplus(sc);
2928 } else {
2929 rl_txeof(sc);
2930 rl_rxeof(sc);
2931 }
2932
1846 rl_txeof(sc);
1847 rl_rxeof(sc);
2933 rl_init(sc);
1848 rl_init(sc);
2934
2935 RL_UNLOCK(sc);
2936
2937 return;
2938}
2939
2940/*
2941 * Stop the adapter and free any mbufs allocated to the
2942 * RX and TX lists.

--- 12 unchanged lines hidden (view full) ---

2955 untimeout(rl_tick, sc, sc->rl_stat_ch);
2956 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2957#ifdef DEVICE_POLLING
2958 ether_poll_deregister(ifp);
2959#endif /* DEVICE_POLLING */
2960
2961 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
2962 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1849 RL_UNLOCK(sc);
1850
1851 return;
1852}
1853
1854/*
1855 * Stop the adapter and free any mbufs allocated to the
1856 * RX and TX lists.

--- 12 unchanged lines hidden (view full) ---

1869 untimeout(rl_tick, sc, sc->rl_stat_ch);
1870 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1871#ifdef DEVICE_POLLING
1872 ether_poll_deregister(ifp);
1873#endif /* DEVICE_POLLING */
1874
1875 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1876 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1877 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
2963
1878
2964 if (RL_ISCPLUS(sc)) {
2965
2966 /* Free the TX list buffers. */
2967
2968 for (i = 0; i < RL_TX_DESC_CNT; i++) {
2969 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) {
2970 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2971 sc->rl_ldata.rl_tx_dmamap[i]);
2972 m_freem(sc->rl_ldata.rl_tx_mbuf[i]);
2973 sc->rl_ldata.rl_tx_mbuf[i] = NULL;
2974 }
1879 /*
1880 * Free the TX list buffers.
1881 */
1882 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1883 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1884 bus_dmamap_unload(sc->rl_tag,
1885 sc->rl_cdata.rl_tx_dmamap[i]);
1886 bus_dmamap_destroy(sc->rl_tag,
1887 sc->rl_cdata.rl_tx_dmamap[i]);
1888 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1889 sc->rl_cdata.rl_tx_chain[i] = NULL;
1890 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
2975 }
1891 }
2976
2977 /* Free the RX list buffers. */
2978
2979 for (i = 0; i < RL_RX_DESC_CNT; i++) {
2980 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) {
2981 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2982 sc->rl_ldata.rl_rx_dmamap[i]);
2983 m_freem(sc->rl_ldata.rl_rx_mbuf[i]);
2984 sc->rl_ldata.rl_rx_mbuf[i] = NULL;
2985 }
2986 }
2987
2988 } else {
2989
2990 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
2991
2992 /*
2993 * Free the TX list buffers.
2994 */
2995 for (i = 0; i < RL_TX_LIST_CNT; i++) {
2996 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
2997 bus_dmamap_unload(sc->rl_tag,
2998 sc->rl_cdata.rl_tx_dmamap[i]);
2999 bus_dmamap_destroy(sc->rl_tag,
3000 sc->rl_cdata.rl_tx_dmamap[i]);
3001 m_freem(sc->rl_cdata.rl_tx_chain[i]);
3002 sc->rl_cdata.rl_tx_chain[i] = NULL;
3003 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
3004 }
3005 }
3006 }
3007
3008 RL_UNLOCK(sc);
3009 return;
3010}
3011
3012/*
3013 * Device suspend routine. Stop the interface and save some PCI

--- 7 unchanged lines hidden (view full) ---

3021 register int i;
3022 struct rl_softc *sc;
3023
3024 sc = device_get_softc(dev);
3025
3026 rl_stop(sc);
3027
3028 for (i = 0; i < 5; i++)
1892 }
1893
1894 RL_UNLOCK(sc);
1895 return;
1896}
1897
1898/*
1899 * Device suspend routine. Stop the interface and save some PCI

--- 7 unchanged lines hidden (view full) ---

1907 register int i;
1908 struct rl_softc *sc;
1909
1910 sc = device_get_softc(dev);
1911
1912 rl_stop(sc);
1913
1914 for (i = 0; i < 5; i++)
3029 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
1915 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
3030 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
3031 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
3032 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3033 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3034
3035 sc->suspended = 1;
3036
3037 return (0);

--- 12 unchanged lines hidden (view full) ---

3050 struct rl_softc *sc;
3051 struct ifnet *ifp;
3052
3053 sc = device_get_softc(dev);
3054 ifp = &sc->arpcom.ac_if;
3055
3056 /* better way to do this? */
3057 for (i = 0; i < 5; i++)
1916 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
1917 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
1918 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
1919 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
1920
1921 sc->suspended = 1;
1922
1923 return (0);

--- 12 unchanged lines hidden (view full) ---

1936 struct rl_softc *sc;
1937 struct ifnet *ifp;
1938
1939 sc = device_get_softc(dev);
1940 ifp = &sc->arpcom.ac_if;
1941
1942 /* better way to do this? */
1943 for (i = 0; i < 5; i++)
3058 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
1944 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
3059 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
3060 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
3061 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
3062 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
3063
3064 /* reenable busmastering */
3065 pci_enable_busmaster(dev);
3066 pci_enable_io(dev, RL_RES);

--- 26 unchanged lines hidden --- 		1945 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
1946 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
1947 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
1948 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
1949
1950 /* reenable busmastering */
1951 pci_enable_busmaster(dev);
1952 pci_enable_io(dev, RL_RES);

--- 26 unchanged lines hidden ---