| if_rl.c (118586) | if_rl.c (118712) |
|---|---|
| 1/* 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 66 unchanged lines hidden (view full) --- 75 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 76 * filter. 77 * 78 * The 8129 chip is an older version of the 8139 that uses an external PHY 79 * chip. The 8129 has a serial MDIO interface for accessing the MII where 80 * the 8139 lets you directly access the on-board PHY registers. We need 81 * to select which interface to use depending on the chip type. 82 * | 1/* 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 66 unchanged lines hidden (view full) --- 75 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 76 * filter. 77 * 78 * The 8129 chip is an older version of the 8139 that uses an external PHY 79 * chip. The 8129 has a serial MDIO interface for accessing the MII where 80 * the 8139 lets you directly access the on-board PHY registers. We need 81 * to select which interface to use depending on the chip type. 82 * |
| 83 * Fast forward a few years. RealTek how has a new chip called the | 83 * Fast forward a few years. RealTek now has a new chip called the |
| 84 * 8139C+ which at long last implements descriptor-based DMA. Not | 84 * 8139C+ which at long last implements descriptor-based DMA. Not |
| 85 * only that, in supports RX and TX TCP/IP checksum offload, VLAN | 85 * only that, it supports RX and TX TCP/IP checksum offload, VLAN |
| 86 * tagging and insertion, TCP large send and 64-bit addressing. 87 * Better still, it allows arbitrary byte alignments for RX and 88 * TX buffers, meaning no copying is necessary on any architecture. 89 * There are a few limitations however: the RX and TX descriptor 90 * rings must be aligned on 256 byte boundaries, they must be in 91 * contiguous RAM, and each ring can have a maximum of 64 descriptors. 92 * There are two TX descriptor queues: one normal priority and one 93 * high. Descriptor ring addresses and DMA buffer addresses are 94 * 64 bits wide. The 8139C+ is also backwards compatible with the 95 * 8139, so the chip will still function with older drivers: C+ 96 * mode has to be enabled by setting the appropriate bits in the C+ 97 * command register. The PHY access mechanism appears to be unchanged. 98 * | 86 * tagging and insertion, TCP large send and 64-bit addressing. 87 * Better still, it allows arbitrary byte alignments for RX and 88 * TX buffers, meaning no copying is necessary on any architecture. 89 * There are a few limitations however: the RX and TX descriptor 90 * rings must be aligned on 256 byte boundaries, they must be in 91 * contiguous RAM, and each ring can have a maximum of 64 descriptors. 92 * There are two TX descriptor queues: one normal priority and one 93 * high. Descriptor ring addresses and DMA buffer addresses are 94 * 64 bits wide. The 8139C+ is also backwards compatible with the 95 * 8139, so the chip will still function with older drivers: C+ 96 * mode has to be enabled by setting the appropriate bits in the C+ 97 * command register. The PHY access mechanism appears to be unchanged. 98 * |
| 99 * The 8169 is a 10/100/1000 ethernet MAC with built-in tri-speed 100 * copper PHY. It has almost the same programming API as the C+ mode 101 * of the 8139C+, with a couple of minor changes and additions: the 102 * TX start register is located at a different offset, and there are 103 * additional registers for GMII PHY status and control, as well as 104 * TBI-mode status and control. There is also a maximum RX packet 105 * size register to allow the chip to receive jumbo frames. The 106 * 8169 can only be programmed in C+ mode: the old 8139 programming | 99 * The 8169 is a 10/100/1000 ethernet MAC. It has almost the same 100 * programming API as the C+ mode of the 8139C+, with a couple of 101 * minor changes and additions: TX start register and timer interrupt 102 * register are located at different offsets, and there are additional 103 * registers for GMII PHY status and control, as well as TBI-mode 104 * status and control. There is also a maximum RX packet size 105 * register to allow the chip to receive jumbo frames. The 8169 106 * can only be programmed in C+ mode: the old 8139 programming |
| 107 * method isn't supported with this chip. Also, RealTek has a LOM 108 * (LAN On Motherboard) gigabit MAC chip called the RTL8110S which | 107 * method isn't supported with this chip. Also, RealTek has a LOM 108 * (LAN On Motherboard) gigabit MAC chip called the RTL8110S which |
| 109 * I believe to be register compatible with the 8169. | 109 * I believe to be register compatible with the 8169. Unlike the 110 * 8139C+, the 8169 can have up to 1024 descriptors per DMA ring. 111 * The reference 8169 board design uses a Marvell 88E1000 'Alaska' 112 * copper PHY. |
| 110 * | 113 * |
| 111 * Unfortunately, RealTek has not released a programming manual for 112 * the 8169 or 8110 yet. The datasheet for the 8139C+ provides most | 114 * The 8169S and 8110S are newer versions of the 8169. Available 115 * in both 32-bit and 64-bit forms, these devices have built-in 116 * copper 10/100/1000 PHYs. The 8110S is a lan-on-motherboard chip 117 * that is pin-for-pin compatible with the 8100. Unfortunately, 118 * RealTek has not released programming manuals for the 8169S and 119 * 8110S yet. The datasheet for the original 8169 provides most |
| 113 * of the information, but you must refer to RealTek's 8169 Linux | 120 * of the information, but you must refer to RealTek's 8169 Linux |
| 114 * driver to fill in the gaps. | 121 * driver to fill in the gaps. Mostly, it appears that the built-in 122 * PHY requires some special initialization. The original 8169 123 * datasheet and the 8139C+ datasheet can be obtained from 124 * http://www.freebsd.org/~wpaul/RealTek. |
| 115 * 116 * This driver now supports both the old 8139 and new 8139C+ | 125 * 126 * This driver now supports both the old 8139 and new 8139C+ |
| 117 * programming models. We detect the 8139C+ by looking for a PCI 118 * revision ID of 0x20 or higher, and we detect the 8169 by its | 127 * programming models. We detect the 8139C+ by looking for the 128 * corresponding hardware rev bits, and we detect the 8169 by its |
| 119 * PCI ID. Two new NIC type codes, RL_8139CPLUS and RL_8169 have 120 * been added to distinguish the chips at runtime. Separate RX and 121 * TX handling routines have been added to handle C+ mode, which 122 * are selected via function pointers that are initialized during 123 * the driver attach phase. 124 */ 125 126#include <sys/cdefs.h> | 129 * PCI ID. Two new NIC type codes, RL_8139CPLUS and RL_8169 have 130 * been added to distinguish the chips at runtime. Separate RX and 131 * TX handling routines have been added to handle C+ mode, which 132 * are selected via function pointers that are initialized during 133 * the driver attach phase. 134 */ 135 136#include <sys/cdefs.h> |
| 127__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 118586 2003-08-07 07:00:30Z wpaul $"); | 137__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 118712 2003-08-10 01:41:35Z wpaul $"); |
| 128 129#include <sys/param.h> 130#include <sys/endian.h> 131#include <sys/systm.h> 132#include <sys/sockio.h> 133#include <sys/mbuf.h> 134#include <sys/malloc.h> 135#include <sys/kernel.h> --- 35 unchanged lines hidden (view full) --- 171 * can hang the bus. I'm inclined to blame this on crummy design/construction 172 * on the part of RealTek. Memory mapped mode does appear to work on 173 * uniprocessor systems though. 174 */ 175#define RL_USEIOSPACE 176 177#include <pci/if_rlreg.h> 178 | 138 139#include <sys/param.h> 140#include <sys/endian.h> 141#include <sys/systm.h> 142#include <sys/sockio.h> 143#include <sys/mbuf.h> 144#include <sys/malloc.h> 145#include <sys/kernel.h> --- 35 unchanged lines hidden (view full) --- 181 * can hang the bus. I'm inclined to blame this on crummy design/construction 182 * on the part of RealTek. Memory mapped mode does appear to work on 183 * uniprocessor systems though. 184 */ 185#define RL_USEIOSPACE 186 187#include <pci/if_rlreg.h> 188 |
| 179__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 118586 2003-08-07 07:00:30Z wpaul $"); | 189__FBSDID("$FreeBSD: head/sys/pci/if_rl.c 118712 2003-08-10 01:41:35Z wpaul $"); |
| 180 181#define RL_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 182 183/* 184 * Various supported device vendors/types and their names. 185 */ 186static struct rl_type rl_devs[] = { 187 { RT_VENDORID, RT_DEVICEID_8129, RL_8129, --- 929 unchanged lines hidden (view full) --- 1117 while(1) { 1118 u_int32_t cmdstat; 1119 d = &ctx->rl_ring[idx]; 1120 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 1121 ctx->rl_maxsegs = 0; 1122 return; 1123 } 1124 cmdstat = segs[i].ds_len; | 190 191#define RL_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 192 193/* 194 * Various supported device vendors/types and their names. 195 */ 196static struct rl_type rl_devs[] = { 197 { RT_VENDORID, RT_DEVICEID_8129, RL_8129, --- 929 unchanged lines hidden (view full) --- 1127 while(1) { 1128 u_int32_t cmdstat; 1129 d = &ctx->rl_ring[idx]; 1130 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 1131 ctx->rl_maxsegs = 0; 1132 return; 1133 } 1134 cmdstat = segs[i].ds_len; |
| 1125 d->rl_bufaddr_lo = htole32(segs[i].ds_addr); 1126 d->rl_bufaddr_hi = 0; | 1135 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 1136 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); |
| 1127 if (i == 0) 1128 cmdstat |= RL_TDESC_CMD_SOF; 1129 else 1130 cmdstat |= RL_TDESC_CMD_OWN; 1131 if (idx == (RL_RX_DESC_CNT - 1)) 1132 cmdstat |= RL_TDESC_CMD_EOR; 1133 d->rl_cmdstat = htole32(cmdstat); 1134 i++; --- 694 unchanged lines hidden (view full) --- 1829 } 1830 1831 RL_DESC_INC(i); 1832 1833 ifp->if_ipackets++; 1834 m->m_pkthdr.len = m->m_len = total_len; 1835 m->m_pkthdr.rcvif = ifp; 1836 | 1137 if (i == 0) 1138 cmdstat |= RL_TDESC_CMD_SOF; 1139 else 1140 cmdstat |= RL_TDESC_CMD_OWN; 1141 if (idx == (RL_RX_DESC_CNT - 1)) 1142 cmdstat |= RL_TDESC_CMD_EOR; 1143 d->rl_cmdstat = htole32(cmdstat); 1144 i++; --- 694 unchanged lines hidden (view full) --- 1839 } 1840 1841 RL_DESC_INC(i); 1842 1843 ifp->if_ipackets++; 1844 m->m_pkthdr.len = m->m_len = total_len; 1845 m->m_pkthdr.rcvif = ifp; 1846 |
| 1837 /* Check IP header checksum */ 1838 if (rxstat & RL_RDESC_STAT_PROTOID) 1839 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1840 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1841 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; | 1847 /* Do RX checksumming if enabled */ |
| 1842 | 1848 |
| 1843 /* Check TCP/UDP checksum */ 1844 if ((RL_TCPPKT(rxstat) && 1845 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1846 (RL_UDPPKT(rxstat) && 1847 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1848 m->m_pkthdr.csum_flags |= 1849 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1850 m->m_pkthdr.csum_data = 0xffff; | 1849 if (ifp->if_capenable & IFCAP_RXCSUM) { 1850 1851 /* Check IP header checksum */ 1852 if (rxstat & RL_RDESC_STAT_PROTOID) 1853 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1854 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1855 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1856 1857 /* Check TCP/UDP checksum */ 1858 if ((RL_TCPPKT(rxstat) && 1859 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1860 (RL_UDPPKT(rxstat) && 1861 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1862 m->m_pkthdr.csum_flags |= 1863 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1864 m->m_pkthdr.csum_data = 0xffff; 1865 } |
| 1851 } 1852 1853 if (rxvlan & RL_RDESC_VLANCTL_TAG) 1854 VLAN_INPUT_TAG(ifp, m, 1855 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue); 1856 (*ifp->if_input)(ifp, m); 1857 } 1858 --- 870 unchanged lines hidden (view full) --- 2729 */ 2730 if (RL_ISCPLUS(sc)) { 2731 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2732 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2733 RL_CPLUSCMD_VLANSTRIP| 2734 (ifp->if_capenable & IFCAP_RXCSUM ? 2735 RL_CPLUSCMD_RXCSUM_ENB : 0)); 2736 | 1866 } 1867 1868 if (rxvlan & RL_RDESC_VLANCTL_TAG) 1869 VLAN_INPUT_TAG(ifp, m, 1870 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue); 1871 (*ifp->if_input)(ifp, m); 1872 } 1873 --- 870 unchanged lines hidden (view full) --- 2744 */ 2745 if (RL_ISCPLUS(sc)) { 2746 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2747 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2748 RL_CPLUSCMD_VLANSTRIP| 2749 (ifp->if_capenable & IFCAP_RXCSUM ? 2750 RL_CPLUSCMD_RXCSUM_ENB : 0)); 2751 |
| 2737 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 0); | 2752 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2753 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); |
| 2738 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, | 2754 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, |
| 2739 sc->rl_ldata.rl_rx_list_addr); | 2755 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); |
| 2740 | 2756 |
| 2741 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 0); | 2757 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2758 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); |
| 2742 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, | 2759 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, |
| 2743 sc->rl_ldata.rl_tx_list_addr); | 2760 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); |
| 2744 2745 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, RL_EARLYTXTHRESH_CNT); 2746 2747 /* 2748 * Initialize the timer interrupt register so that 2749 * a timer interrupt will be generated once the timer 2750 * reaches a certain number of ticks. The timer is 2751 * reloaded on each transmit. This gives us TX interrupt 2752 * moderation, which dramatically improves TX frame rate. 2753 */ 2754 2755 if (sc->rl_type == RL_8169) | 2761 2762 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, RL_EARLYTXTHRESH_CNT); 2763 2764 /* 2765 * Initialize the timer interrupt register so that 2766 * a timer interrupt will be generated once the timer 2767 * reaches a certain number of ticks. The timer is 2768 * reloaded on each transmit. This gives us TX interrupt 2769 * moderation, which dramatically improves TX frame rate. 2770 */ 2771 2772 if (sc->rl_type == RL_8169) |
| 2756 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x400); | 2773 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); |
| 2757 else 2758 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2759 2760 /* 2761 * For 8169 gigE NICs, set the max allowed RX packet 2762 * size so we can receive jumbo frames. 2763 */ 2764 if (sc->rl_type == RL_8169) --- 286 unchanged lines hidden --- | 2774 else 2775 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2776 2777 /* 2778 * For 8169 gigE NICs, set the max allowed RX packet 2779 * size so we can receive jumbo frames. 2780 */ 2781 if (sc->rl_type == RL_8169) --- 286 unchanged lines hidden --- |