34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
35 * from: i386/isa sio.c,v 1.234
36 */
37
38#include "opt_comconsole.h"
39#include "opt_compat.h"
40#include "opt_ddb.h"
41#include "opt_sio.h"
42#include "card.h"
43#include "pci.h"
44#include "sio.h"
45
46/*
47 * Serial driver, based on 386BSD-0.1 com driver.
48 * Mostly rewritten to use pseudo-DMA.
49 * Works for National Semiconductor NS8250-NS16550AF UARTs.
50 * COM driver, based on HP dca driver.
51 *
52 * Changes for PC-Card integration:
53 * - Added PC-Card driver table and handlers
54 */
55/*===============================================================
56 * 386BSD(98),FreeBSD-1.1x(98) com driver.
57 * -----
58 * modified for PC9801 by M.Ishii
59 * Kyoto University Microcomputer Club (KMC)
60 * Chou "TEFUTEFU" Hirotomi
61 * Kyoto Univ. the faculty of medicine
62 *===============================================================
63 * FreeBSD-2.0.1(98) sio driver.
64 * -----
65 * modified for pc98 Internal i8251 and MICRO CORE MC16550II
66 * T.Koike(hfc01340@niftyserve.or.jp)
67 * implement kernel device configuration
68 * aizu@orient.center.nitech.ac.jp
69 *
70 * Notes.
71 * -----
72 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local
73 * functions.
74 * This driver is under debugging,has bugs.
75 *
76 * 1) config
77 * options COM_MULTIPORT #if using MC16550II
78 * device sio0 at nec? port 0x30 tty irq 4 #internal
79 * device sio1 at nec? port 0xd2 tty irq 5 flags 0x101 #mc1
80 * device sio2 at nec? port 0x8d2 tty flags 0x101 #mc2
81 * # ~~~~~iobase ~~multi port flag
82 * # ~ master device is sio1
83 * 2) device
84 * cd /dev; MAKEDEV ttyd0 ttyd1 ..
85 * 3) /etc/rc.serial
86 * 57600bps is too fast for sio0(internal8251)
87 * my ex.
88 * #set default speed 9600
89 * modem()
90 * :
91 * stty </dev/ttyid$i crtscts 9600
92 * : # ~~~~ default speed(can change after init.)
93 * modem 0 1 2
94 * 4) COMCONSOLE
95 * not changed.
96 * 5) PC9861K,PIO9032B,B98_01
97 * not tested.
98 */
99/*
100 * modified for AIWA B98-01
101 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995
102 *
103 * How to configure...
104 * # options COM_MULTIPORT # support for MICROCORE MC16550II
105 * ... comment-out this line, which will conflict with B98_01.
106 * options "B98_01" # support for AIWA B98-01
107 * device sio1 at nec? port 0x00d1 tty irq ?
108 * device sio2 at nec? port 0x00d5 tty irq ?
109 * ... you can leave these lines `irq ?', irq will be autodetected.
110 */
111/*
112 * Modified by Y.Takahashi of Kogakuin University.
113 */
114/*
115 * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org>
116 */
117
118#ifdef PC98
119#define COM_IF_INTERNAL 0x00
120#define COM_IF_PC9861K_1 0x01
121#define COM_IF_PC9861K_2 0x02
122#define COM_IF_IND_SS_1 0x03
123#define COM_IF_IND_SS_2 0x04
124#define COM_IF_PIO9032B_1 0x05
125#define COM_IF_PIO9032B_2 0x06
126#define COM_IF_B98_01_1 0x07
127#define COM_IF_B98_01_2 0x08
128#define COM_IF_END1 COM_IF_B98_01_2
129#define COM_IF_RSA98 0x10 /* same as COM_IF_NS16550 */
130#define COM_IF_NS16550 0x11
131#define COM_IF_SECOND_CCU 0x12 /* same as COM_IF_NS16550 */
132#define COM_IF_MC16550II 0x13
133#define COM_IF_MCRS98 0x14 /* same as COM_IF_MC16550II */
134#define COM_IF_RSB3000 0x15
135#define COM_IF_RSB384 0x16
136#define COM_IF_MODEM_CARD 0x17 /* same as COM_IF_NS16550 */
137#define COM_IF_RSA98III 0x18
138#define COM_IF_ESP98 0x19
139#define COM_IF_END2 COM_IF_ESP98
140#endif /* PC98 */
141
142#include <sys/param.h>
143#include <sys/systm.h>
144#include <sys/reboot.h>
145#include <sys/malloc.h>
146#include <sys/tty.h>
147#include <sys/proc.h>
148#include <sys/module.h>
149#include <sys/conf.h>
150#include <sys/dkstat.h>
151#include <sys/fcntl.h>
152#include <sys/interrupt.h>
153#include <sys/kernel.h>
154#include <sys/syslog.h>
155#include <sys/sysctl.h>
156#include <sys/bus.h>
157#include <machine/bus.h>
158#include <sys/rman.h>
159#include <sys/timetc.h>
160#include <sys/timepps.h>
161
162#ifdef PC98
163#include <pc98/pc98/pc98.h>
164#include <pc98/pc98/pc98_machdep.h>
165#include <i386/isa/ic/i8251.h>
166#else
167#include <isa/isareg.h>
168#endif
169#include <isa/isavar.h>
170#if NPCI > 0
171#include <pci/pcireg.h>
172#include <pci/pcivar.h>
173#endif
174#include <machine/lock.h>
175
176#include <machine/clock.h>
177#include <machine/ipl.h>
178#ifndef SMP
179#include <machine/lock.h>
180#endif
181#include <machine/resource.h>
182
183#include <isa/sioreg.h>
184
185#ifdef COM_ESP
186#include <i386/isa/ic/esp.h>
187#endif
188#include <i386/isa/ic/ns16550.h>
189#ifdef PC98
190#include <i386/isa/ic/rsa.h>
191#endif
192
193#ifndef __i386__
194#define disable_intr()
195#define enable_intr()
196#endif
197
198#ifdef SMP
199#define disable_intr() COM_DISABLE_INTR()
200#define enable_intr() COM_ENABLE_INTR()
201#endif /* SMP */
202
203#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */
204
205#define CALLOUT_MASK 0x80
206#define CONTROL_MASK 0x60
207#define CONTROL_INIT_STATE 0x20
208#define CONTROL_LOCK_STATE 0x40
209#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev)))
210#define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK)
211#define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK)
212
213#ifdef COM_MULTIPORT
214/* checks in flags for multiport and which is multiport "master chip"
215 * for a given card
216 */
217#define COM_ISMULTIPORT(flags) ((flags) & 0x01)
218#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff)
219#define COM_NOTAST4(flags) ((flags) & 0x04)
220#endif /* COM_MULTIPORT */
221
222#define COM_CONSOLE(flags) ((flags) & 0x10)
223#define COM_FORCECONSOLE(flags) ((flags) & 0x20)
224#define COM_LLCONSOLE(flags) ((flags) & 0x40)
225#define COM_DEBUGGER(flags) ((flags) & 0x80)
226#define COM_LOSESOUTINTS(flags) ((flags) & 0x08)
227#define COM_NOFIFO(flags) ((flags) & 0x02)
228#define COM_ST16650A(flags) ((flags) & 0x20000)
229#define COM_C_NOPROBE (0x40000)
230#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE)
231#define COM_C_IIR_TXRDYBUG (0x80000)
232#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG)
233#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24)
234
235#ifdef PC98
236#define com_emr com_msr /* Extension mode register for RSB-2000/3000 */
237#endif
238#define com_scr 7 /* scratch register for 16450-16550 (R/W) */
239
240#define sio_getreg(com, off) \
241 (bus_space_read_1((com)->bst, (com)->bsh, (off)))
242#define sio_setreg(com, off, value) \
243 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value)))
244
245/*
246 * com state bits.
247 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
248 * than the other bits so that they can be tested as a group without masking
249 * off the low bits.
250 *
251 * The following com and tty flags correspond closely:
252 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and
253 * comstop())
254 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart())
255 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam())
256 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam())
257 * TS_FLUSH is not used.
258 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON.
259 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state).
260 */
261#define CS_BUSY 0x80 /* output in progress */
262#define CS_TTGO 0x40 /* output not stopped by XOFF */
263#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */
264#define CS_CHECKMSR 1 /* check of MSR scheduled */
265#define CS_CTS_OFLOW 2 /* use CTS output flow control */
266#define CS_DTR_OFF 0x10 /* DTR held off */
267#define CS_ODONE 4 /* output completed */
268#define CS_RTS_IFLOW 8 /* use RTS input flow control */
269#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */
270
271static char const * const error_desc[] = {
272#define CE_OVERRUN 0
273 "silo overflow",
274#define CE_INTERRUPT_BUF_OVERFLOW 1
275 "interrupt-level buffer overflow",
276#define CE_TTY_BUF_OVERFLOW 2
277 "tty-level buffer overflow",
278};
279
280#define CE_NTYPES 3
281#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum])
282
283/* types. XXX - should be elsewhere */
284typedef u_int Port_t; /* hardware port */
285typedef u_char bool_t; /* boolean */
286
287/* queue of linear buffers */
288struct lbq {
289 u_char *l_head; /* next char to process */
290 u_char *l_tail; /* one past the last char to process */
291 struct lbq *l_next; /* next in queue */
292 bool_t l_queued; /* nonzero if queued */
293};
294
295/* com device structure */
296struct com_s {
297 u_int flags; /* Copy isa device flags */
298 u_char state; /* miscellaneous flag bits */
299 bool_t active_out; /* nonzero if the callout device is open */
300 u_char cfcr_image; /* copy of value written to CFCR */
301#ifdef COM_ESP
302 bool_t esp; /* is this unit a hayes esp board? */
303#endif
304 u_char extra_state; /* more flag bits, separate for order trick */
305 u_char fifo_image; /* copy of value written to FIFO */
306 bool_t hasfifo; /* nonzero for 16550 UARTs */
307 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */
308 bool_t loses_outints; /* nonzero if device loses output interrupts */
309 u_char mcr_image; /* copy of value written to MCR */
310#ifdef COM_MULTIPORT
311 bool_t multiport; /* is this unit part of a multiport device? */
312#endif /* COM_MULTIPORT */
313 bool_t no_irq; /* nonzero if irq is not attached */
314 bool_t gone; /* hardware disappeared */
315 bool_t poll; /* nonzero if polling is required */
316 bool_t poll_output; /* nonzero if polling for output is required */
317 int unit; /* unit number */
318 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */
319 u_int tx_fifo_size;
320 u_int wopeners; /* # processes waiting for DCD in open() */
321
322 /*
323 * The high level of the driver never reads status registers directly
324 * because there would be too many side effects to handle conveniently.
325 * Instead, it reads copies of the registers stored here by the
326 * interrupt handler.
327 */
328 u_char last_modem_status; /* last MSR read by intr handler */
329 u_char prev_modem_status; /* last MSR handled by high level */
330
331 u_char hotchar; /* ldisc-specific char to be handled ASAP */
332 u_char *ibuf; /* start of input buffer */
333 u_char *ibufend; /* end of input buffer */
334 u_char *ibufold; /* old input buffer, to be freed */
335 u_char *ihighwater; /* threshold in input buffer */
336 u_char *iptr; /* next free spot in input buffer */
337 int ibufsize; /* size of ibuf (not include error bytes) */
338 int ierroff; /* offset of error bytes in ibuf */
339
340 struct lbq obufq; /* head of queue of output buffers */
341 struct lbq obufs[2]; /* output buffers */
342
343 bus_space_tag_t bst;
344 bus_space_handle_t bsh;
345
346#ifdef PC98
347 Port_t cmd_port;
348 Port_t sts_port;
349 Port_t in_modem_port;
350 Port_t intr_ctrl_port;
351 Port_t rsabase; /* iobase address of a I/O-DATA RSA board */
352 int intr_enable;
353 int pc98_prev_modem_status;
354 int pc98_modem_delta;
355 int modem_car_chg_timer;
356 int pc98_prev_siocmd;
357 int pc98_prev_siomod;
358 int modem_checking;
359 int pc98_if_type;
360
361 bool_t pc98_8251fifo;
362 bool_t pc98_8251fifo_enable;
363#endif /* PC98 */
364 Port_t data_port; /* i/o ports */
365#ifdef COM_ESP
366 Port_t esp_port;
367#endif
368 Port_t int_id_port;
369 Port_t modem_ctl_port;
370 Port_t line_status_port;
371 Port_t modem_status_port;
372 Port_t intr_ctl_port; /* Ports of IIR register */
373
374 struct tty *tp; /* cross reference */
375
376 /* Initial state. */
377 struct termios it_in; /* should be in struct tty */
378 struct termios it_out;
379
380 /* Lock state. */
381 struct termios lt_in; /* should be in struct tty */
382 struct termios lt_out;
383
384 bool_t do_timestamp;
385 bool_t do_dcd_timestamp;
386 struct timeval timestamp;
387 struct timeval dcd_timestamp;
388 struct pps_state pps;
389
390 u_long bytes_in; /* statistics */
391 u_long bytes_out;
392 u_int delta_error_counts[CE_NTYPES];
393 u_long error_counts[CE_NTYPES];
394
395 struct resource *irqres;
396 struct resource *ioportres;
397 void *cookie;
398
399 /*
400 * Data area for output buffers. Someday we should build the output
401 * buffer queue without copying data.
402 */
403#ifdef PC98
404 int obufsize;
405 u_char *obuf1;
406 u_char *obuf2;
407#else
408 u_char obuf1[256];
409 u_char obuf2[256];
410#endif
411};
412
413#ifdef COM_ESP
414static int espattach __P((struct com_s *com, Port_t esp_port));
415#endif
416static int sioattach __P((device_t dev, int rid));
417static int sio_isa_attach __P((device_t dev));
418
419static timeout_t siobusycheck;
420static timeout_t siodtrwakeup;
421static void comhardclose __P((struct com_s *com));
422static void sioinput __P((struct com_s *com));
423static void siointr1 __P((struct com_s *com));
424static void siointr __P((void *arg));
425static int commctl __P((struct com_s *com, int bits, int how));
426static int comparam __P((struct tty *tp, struct termios *t));
427static swihand_t siopoll;
428static int sioprobe __P((device_t dev, int xrid));
429static int sio_isa_probe __P((device_t dev));
430static void siosettimeout __P((void));
431static int siosetwater __P((struct com_s *com, speed_t speed));
432static void comstart __P((struct tty *tp));
433static void comstop __P((struct tty *tp, int rw));
434static timeout_t comwakeup;
435static void disc_optim __P((struct tty *tp, struct termios *t,
436 struct com_s *com));
437
438#if NCARD > 0
439static int sio_pccard_attach __P((device_t dev));
440static int sio_pccard_detach __P((device_t dev));
441static int sio_pccard_probe __P((device_t dev));
442#endif /* NCARD > 0 */
443
444#if NPCI > 0
445static int sio_pci_attach __P((device_t dev));
446static void sio_pci_kludge_unit __P((device_t dev));
447static int sio_pci_probe __P((device_t dev));
448#endif /* NPCI > 0 */
449
450static char driver_name[] = "sio";
451
452/* table and macro for fast conversion from a unit number to its com struct */
453static devclass_t sio_devclass;
454#define com_addr(unit) ((struct com_s *) \
455 devclass_get_softc(sio_devclass, unit))
456
457static device_method_t sio_isa_methods[] = {
458 /* Device interface */
459 DEVMETHOD(device_probe, sio_isa_probe),
460 DEVMETHOD(device_attach, sio_isa_attach),
461
462 { 0, 0 }
463};
464
465static driver_t sio_isa_driver = {
466 driver_name,
467 sio_isa_methods,
468 sizeof(struct com_s),
469};
470
471#if NCARD > 0
472static device_method_t sio_pccard_methods[] = {
473 /* Device interface */
474 DEVMETHOD(device_probe, sio_pccard_probe),
475 DEVMETHOD(device_attach, sio_pccard_attach),
476 DEVMETHOD(device_detach, sio_pccard_detach),
477
478 { 0, 0 }
479};
480
481static driver_t sio_pccard_driver = {
482 driver_name,
483 sio_pccard_methods,
484 sizeof(struct com_s),
485};
486#endif /* NCARD > 0 */
487
488#if NPCI > 0
489static device_method_t sio_pci_methods[] = {
490 /* Device interface */
491 DEVMETHOD(device_probe, sio_pci_probe),
492 DEVMETHOD(device_attach, sio_pci_attach),
493
494 { 0, 0 }
495};
496
497static driver_t sio_pci_driver = {
498 driver_name,
499 sio_pci_methods,
500 sizeof(struct com_s),
501};
502#endif /* NPCI > 0 */
503
504static d_open_t sioopen;
505static d_close_t sioclose;
506static d_read_t sioread;
507static d_write_t siowrite;
508static d_ioctl_t sioioctl;
509
510#define CDEV_MAJOR 28
511static struct cdevsw sio_cdevsw = {
512 /* open */ sioopen,
513 /* close */ sioclose,
514 /* read */ sioread,
515 /* write */ siowrite,
516 /* ioctl */ sioioctl,
517 /* poll */ ttypoll,
518 /* mmap */ nommap,
519 /* strategy */ nostrategy,
520 /* name */ driver_name,
521 /* maj */ CDEV_MAJOR,
522 /* dump */ nodump,
523 /* psize */ nopsize,
524 /* flags */ D_TTY,
525 /* bmaj */ -1
526};
527
528int comconsole = -1;
529static volatile speed_t comdefaultrate = CONSPEED;
530#ifdef __alpha__
531static volatile speed_t gdbdefaultrate = CONSPEED;
532#endif
533static u_int com_events; /* input chars + weighted output completions */
534static Port_t siocniobase;
535static int siocnunit;
536static Port_t siogdbiobase;
537static int siogdbunit = -1;
538static bool_t sio_registered;
539static int sio_timeout;
540static int sio_timeouts_until_log;
541static struct callout_handle sio_timeout_handle
542 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
543static int sio_numunits;
544
545#ifdef PC98
546struct siodev {
547 short if_type;
548 short irq;
549 Port_t cmd, sts, ctrl, mod;
550};
551static int sysclock;
552
553#define COM_INT_DISABLE {int previpri; previpri=spltty();
554#define COM_INT_ENABLE splx(previpri);}
555#define IEN_TxFLAG IEN_Tx
556
557#define COM_CARRIER_DETECT_EMULATE 0
558#define PC98_CHECK_MODEM_INTERVAL (hz/10)
559#define DCD_OFF_TOLERANCE 2
560#define DCD_ON_RECOGNITION 2
561#define GET_IFTYPE(flags) ((flags >> 24) & 0x1f)
562#define SET_IFTYPE(type) (type << 24)
563#define IS_8251(if_type) (!(if_type & 0x10))
564#define COM1_EXT_CLOCK 0x40000
565
566static void commint __P((dev_t dev));
567static void com_tiocm_set __P((struct com_s *com, int msr));
568static void com_tiocm_bis __P((struct com_s *com, int msr));
569static void com_tiocm_bic __P((struct com_s *com, int msr));
570static int com_tiocm_get __P((struct com_s *com));
571static int com_tiocm_get_delta __P((struct com_s *com));
572static void pc98_msrint_start __P((dev_t dev));
573static void com_cflag_and_speed_set __P((struct com_s *com, int cflag, int speed));
574static int pc98_ttspeedtab __P((struct com_s *com, int speed));
575static int pc98_get_modem_status __P((struct com_s *com));
576static timeout_t pc98_check_msr;
577static void pc98_set_baud_rate __P((struct com_s *com, int count));
578static void pc98_i8251_reset __P((struct com_s *com, int mode, int command));
579static void pc98_disable_i8251_interrupt __P((struct com_s *com, int mod));
580static void pc98_enable_i8251_interrupt __P((struct com_s *com, int mod));
581static int pc98_check_i8251_interrupt __P((struct com_s *com));
582static int pc98_i8251_get_cmd __P((struct com_s *com));
583static int pc98_i8251_get_mod __P((struct com_s *com));
584static void pc98_i8251_set_cmd __P((struct com_s *com, int x));
585static void pc98_i8251_or_cmd __P((struct com_s *com, int x));
586static void pc98_i8251_clear_cmd __P((struct com_s *com, int x));
587static void pc98_i8251_clear_or_cmd __P((struct com_s *com, int clr, int x));
588static int pc98_check_if_type __P((device_t dev, struct siodev *iod));
589static int pc98_check_8251vfast __P((void));
590static int pc98_check_8251fifo __P((void));
591static void pc98_check_sysclock __P((void));
592static void pc98_set_ioport __P((struct com_s *com));
593
594#define com_int_Tx_disable(com) \
595 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP)
596#define com_int_Tx_enable(com) \
597 pc98_enable_i8251_interrupt(com,IEN_TxFLAG)
598#define com_int_Rx_disable(com) \
599 pc98_disable_i8251_interrupt(com,IEN_Rx)
600#define com_int_Rx_enable(com) \
601 pc98_enable_i8251_interrupt(com,IEN_Rx)
602#define com_int_TxRx_disable(com) \
603 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx)
604#define com_int_TxRx_enable(com) \
605 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx)
606#define com_send_break_on(com) \
607 pc98_i8251_or_cmd(com,CMD8251_SBRK)
608#define com_send_break_off(com) \
609 pc98_i8251_clear_cmd(com,CMD8251_SBRK)
610
611static struct speedtab pc98speedtab[] = { /* internal RS232C interface */
612 { 0, 0, },
613 { 50, 50, },
614 { 75, 75, },
615 { 150, 150, },
616 { 200, 200, },
617 { 300, 300, },
618 { 600, 600, },
619 { 1200, 1200, },
620 { 2400, 2400, },
621 { 4800, 4800, },
622 { 9600, 9600, },
623 { 19200, 19200, },
624 { 38400, 38400, },
625 { 51200, 51200, },
626 { 76800, 76800, },
627 { 20800, 20800, },
628 { 31200, 31200, },
629 { 41600, 41600, },
630 { 62400, 62400, },
631 { -1, -1 }
632};
633static struct speedtab pc98fast_speedtab[] = {
634 { 9600, 0x80 | COMBRD(9600), },
635 { 19200, 0x80 | COMBRD(19200), },
636 { 38400, 0x80 | COMBRD(38400), },
637 { 57600, 0x80 | COMBRD(57600), },
638 { 115200, 0x80 | COMBRD(115200), },
639 { -1, -1 }
640};
641static struct speedtab comspeedtab_pio9032b[] = {
642 { 300, 6, },
643 { 600, 5, },
644 { 1200, 4, },
645 { 2400, 3, },
646 { 4800, 2, },
647 { 9600, 1, },
648 { 19200, 0, },
649 { 38400, 7, },
650 { -1, -1 }
651};
652static struct speedtab comspeedtab_b98_01[] = {
653 { 75, 11, },
654 { 150, 10, },
655 { 300, 9, },
656 { 600, 8, },
657 { 1200, 7, },
658 { 2400, 6, },
659 { 4800, 5, },
660 { 9600, 4, },
661 { 19200, 3, },
662 { 38400, 2, },
663 { 76800, 1, },
664 { 153600, 0, },
665 { -1, -1 }
666};
667static struct speedtab comspeedtab_mc16550[] = {
668 { 300, 1536, },
669 { 600, 768, },
670 { 1200, 384, },
671 { 2400, 192, },
672 { 4800, 96, },
673 { 9600, 48, },
674 { 19200, 24, },
675 { 38400, 12, },
676 { 57600, 8, },
677 { 115200, 4, },
678 { 153600, 3, },
679 { 230400, 2, },
680 { 460800, 1, },
681 { -1, -1 }
682};
683static struct speedtab comspeedtab_rsb384[] = {
684 { 300, 3840, },
685 { 600, 1920, },
686 { 1200, 960, },
687 { 2400, 480, },
688 { 4800, 240, },
689 { 9600, 120, },
690 { 19200, 60, },
691 { 38400, 30, },
692 { 57600, 20, },
693 { 115200, 10, },
694 { 128000, 9, },
695 { 144000, 8, },
696 { 192000, 6, },
697 { 230400, 5, },
698 { 288000, 4, },
699 { 384000, 3, },
700 { 576000, 2, },
701 { 1152000, 1, },
702 { -1, -1 }
703};
704static struct speedtab comspeedtab_rsa[] = {
705 { 0, 0 },
706 { 50, COMBRD_RSA(50) },
707 { 75, COMBRD_RSA(75) },
708 { 110, COMBRD_RSA(110) },
709 { 134, COMBRD_RSA(134) },
710 { 150, COMBRD_RSA(150) },
711 { 200, COMBRD_RSA(200) },
712 { 300, COMBRD_RSA(300) },
713 { 600, COMBRD_RSA(600) },
714 { 1200, COMBRD_RSA(1200) },
715 { 1800, COMBRD_RSA(1800) },
716 { 2400, COMBRD_RSA(2400) },
717 { 4800, COMBRD_RSA(4800) },
718 { 9600, COMBRD_RSA(9600) },
719 { 19200, COMBRD_RSA(19200) },
720 { 38400, COMBRD_RSA(38400) },
721 { 57600, COMBRD_RSA(57600) },
722 { 115200, COMBRD_RSA(115200) },
723 { 230400, COMBRD_RSA(230400) },
724 { 460800, COMBRD_RSA(460800) },
725 { 921600, COMBRD_RSA(921600) },
726 { -1, -1 }
727};
728#endif /* PC98 */
729
730static struct speedtab comspeedtab[] = {
731 { 0, 0 },
732 { 50, COMBRD(50) },
733 { 75, COMBRD(75) },
734 { 110, COMBRD(110) },
735 { 134, COMBRD(134) },
736 { 150, COMBRD(150) },
737 { 200, COMBRD(200) },
738 { 300, COMBRD(300) },
739 { 600, COMBRD(600) },
740 { 1200, COMBRD(1200) },
741 { 1800, COMBRD(1800) },
742 { 2400, COMBRD(2400) },
743 { 4800, COMBRD(4800) },
744 { 9600, COMBRD(9600) },
745 { 19200, COMBRD(19200) },
746 { 38400, COMBRD(38400) },
747 { 57600, COMBRD(57600) },
748 { 115200, COMBRD(115200) },
749 { -1, -1 }
750};
751
752#ifdef PC98
753struct {
754 char *name;
755 short port_table[7];
756 short irr_mask;
757 struct speedtab *speedtab;
758 short check_irq;
759} if_8251_type[] = {
760 /* COM_IF_INTERNAL */
761 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1},
762 -1, pc98speedtab, 1 },
763 /* COM_IF_PC9861K_1 */
764 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1},
765 3, NULL, 1 },
766 /* COM_IF_PC9861K_2 */
767 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1},
768 3, NULL, 1 },
769 /* COM_IF_IND_SS_1 */
770 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1},
771 3, comspeedtab_mc16550, 1 },
772 /* COM_IF_IND_SS_2 */
773 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1},
774 3, comspeedtab_mc16550, 1 },
775 /* COM_IF_PIO9032B_1 */
776 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1},
777 7, comspeedtab_pio9032b, 1 },
778 /* COM_IF_PIO9032B_2 */
779 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1},
780 7, comspeedtab_pio9032b, 1 },
781 /* COM_IF_B98_01_1 */
782 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3},
783 7, comspeedtab_b98_01, 0 },
784 /* COM_IF_B98_01_2 */
785 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7},
786 7, comspeedtab_b98_01, 0 },
787};
788#define PC98SIO_data_port(type) (if_8251_type[type].port_table[0])
789#define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1])
790#define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2])
791#define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3])
792#define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4])
793#define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5])
794#define PC98SIO_func_port(type) (if_8251_type[type].port_table[6])
795
796#define I8251F_data 0x130
797#define I8251F_lsr 0x132
798#define I8251F_msr 0x134
799#define I8251F_iir 0x136
800#define I8251F_fcr 0x138
801#define I8251F_div 0x13a
802
803
804static bus_addr_t port_table_0[] =
805 {0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007};
806static bus_addr_t port_table_1[] =
807 {0x000, 0x002, 0x004, 0x006, 0x008, 0x00a, 0x00c, 0x00e};
808static bus_addr_t port_table_8[] =
809 {0x000, 0x100, 0x200, 0x300, 0x400, 0x500, 0x600, 0x700};
810static bus_addr_t port_table_rsa[] = {
811 0x008, 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f,
812 0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007
813};
814
815struct {
816 char *name;
817 short irr_read;
818 short irr_write;
819 bus_addr_t *iat;
820 bus_size_t iatsz;
821 struct speedtab *speedtab;
822} if_16550a_type[] = {
823 /* COM_IF_RSA98 */
824 {" (RSA-98)", -1, -1, port_table_0, IO_COMSIZE, comspeedtab},
825 /* COM_IF_NS16550 */
826 {"", -1, -1, port_table_0, IO_COMSIZE, comspeedtab},
827 /* COM_IF_SECOND_CCU */
828 {"", -1, -1, port_table_0, IO_COMSIZE, comspeedtab},
829 /* COM_IF_MC16550II */
830 {" (MC16550II)", -1, 0x1000, port_table_8, IO_COMSIZE,
831 comspeedtab_mc16550},
832 /* COM_IF_MCRS98 */
833 {" (MC-RS98)", -1, 0x1000, port_table_8, IO_COMSIZE,
834 comspeedtab_mc16550},
835 /* COM_IF_RSB3000 */
836 {" (RSB-3000)", 0xbf, -1, port_table_1, IO_COMSIZE,
837 comspeedtab_rsb384},
838 /* COM_IF_RSB384 */
839 {" (RSB-384)", 0xbf, -1, port_table_1, IO_COMSIZE, comspeedtab_rsb384},
840 /* COM_IF_MODEM_CARD */
841 {"", -1, -1, port_table_0, IO_COMSIZE, comspeedtab},
842 /* COM_IF_RSA98III */
843 {" (RSA-98III)", -1, -1, port_table_rsa, 16, comspeedtab_rsa},
844 /* COM_IF_ESP98 */
845 {" (ESP98)", -1, -1, port_table_1, IO_COMSIZE, comspeedtab_mc16550},
846};
847#endif /* PC98 */
848
849#ifdef COM_ESP
850#ifdef PC98
851
852/* XXX configure this properly. */
853static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 };
854static Port_t likely_esp_ports[] = { 0xc0d0, 0 };
855
856#define ESP98_CMD1 (ESP_CMD1 * 0x100)
857#define ESP98_CMD2 (ESP_CMD2 * 0x100)
858#define ESP98_STATUS1 (ESP_STATUS1 * 0x100)
859#define ESP98_STATUS2 (ESP_STATUS2 * 0x100)
860
861#else /* PC98 */
862
863/* XXX configure this properly. */
864static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
865static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
866
867#endif /* PC98 */
868#endif
869
870/*
871 * handle sysctl read/write requests for console speed
872 *
873 * In addition to setting comdefaultrate for I/O through /dev/console,
874 * also set the initial and lock values for the /dev/ttyXX device
875 * if there is one associated with the console. Finally, if the /dev/tty
876 * device has already been open, change the speed on the open running port
877 * itself.
878 */
879
880static int
| 34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
35 * from: i386/isa sio.c,v 1.234
36 */
37
38#include "opt_comconsole.h"
39#include "opt_compat.h"
40#include "opt_ddb.h"
41#include "opt_sio.h"
42#include "card.h"
43#include "pci.h"
44#include "sio.h"
45
46/*
47 * Serial driver, based on 386BSD-0.1 com driver.
48 * Mostly rewritten to use pseudo-DMA.
49 * Works for National Semiconductor NS8250-NS16550AF UARTs.
50 * COM driver, based on HP dca driver.
51 *
52 * Changes for PC-Card integration:
53 * - Added PC-Card driver table and handlers
54 */
55/*===============================================================
56 * 386BSD(98),FreeBSD-1.1x(98) com driver.
57 * -----
58 * modified for PC9801 by M.Ishii
59 * Kyoto University Microcomputer Club (KMC)
60 * Chou "TEFUTEFU" Hirotomi
61 * Kyoto Univ. the faculty of medicine
62 *===============================================================
63 * FreeBSD-2.0.1(98) sio driver.
64 * -----
65 * modified for pc98 Internal i8251 and MICRO CORE MC16550II
66 * T.Koike(hfc01340@niftyserve.or.jp)
67 * implement kernel device configuration
68 * aizu@orient.center.nitech.ac.jp
69 *
70 * Notes.
71 * -----
72 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local
73 * functions.
74 * This driver is under debugging,has bugs.
75 *
76 * 1) config
77 * options COM_MULTIPORT #if using MC16550II
78 * device sio0 at nec? port 0x30 tty irq 4 #internal
79 * device sio1 at nec? port 0xd2 tty irq 5 flags 0x101 #mc1
80 * device sio2 at nec? port 0x8d2 tty flags 0x101 #mc2
81 * # ~~~~~iobase ~~multi port flag
82 * # ~ master device is sio1
83 * 2) device
84 * cd /dev; MAKEDEV ttyd0 ttyd1 ..
85 * 3) /etc/rc.serial
86 * 57600bps is too fast for sio0(internal8251)
87 * my ex.
88 * #set default speed 9600
89 * modem()
90 * :
91 * stty </dev/ttyid$i crtscts 9600
92 * : # ~~~~ default speed(can change after init.)
93 * modem 0 1 2
94 * 4) COMCONSOLE
95 * not changed.
96 * 5) PC9861K,PIO9032B,B98_01
97 * not tested.
98 */
99/*
100 * modified for AIWA B98-01
101 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995
102 *
103 * How to configure...
104 * # options COM_MULTIPORT # support for MICROCORE MC16550II
105 * ... comment-out this line, which will conflict with B98_01.
106 * options "B98_01" # support for AIWA B98-01
107 * device sio1 at nec? port 0x00d1 tty irq ?
108 * device sio2 at nec? port 0x00d5 tty irq ?
109 * ... you can leave these lines `irq ?', irq will be autodetected.
110 */
111/*
112 * Modified by Y.Takahashi of Kogakuin University.
113 */
114/*
115 * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org>
116 */
117
118#ifdef PC98
119#define COM_IF_INTERNAL 0x00
120#define COM_IF_PC9861K_1 0x01
121#define COM_IF_PC9861K_2 0x02
122#define COM_IF_IND_SS_1 0x03
123#define COM_IF_IND_SS_2 0x04
124#define COM_IF_PIO9032B_1 0x05
125#define COM_IF_PIO9032B_2 0x06
126#define COM_IF_B98_01_1 0x07
127#define COM_IF_B98_01_2 0x08
128#define COM_IF_END1 COM_IF_B98_01_2
129#define COM_IF_RSA98 0x10 /* same as COM_IF_NS16550 */
130#define COM_IF_NS16550 0x11
131#define COM_IF_SECOND_CCU 0x12 /* same as COM_IF_NS16550 */
132#define COM_IF_MC16550II 0x13
133#define COM_IF_MCRS98 0x14 /* same as COM_IF_MC16550II */
134#define COM_IF_RSB3000 0x15
135#define COM_IF_RSB384 0x16
136#define COM_IF_MODEM_CARD 0x17 /* same as COM_IF_NS16550 */
137#define COM_IF_RSA98III 0x18
138#define COM_IF_ESP98 0x19
139#define COM_IF_END2 COM_IF_ESP98
140#endif /* PC98 */
141
142#include <sys/param.h>
143#include <sys/systm.h>
144#include <sys/reboot.h>
145#include <sys/malloc.h>
146#include <sys/tty.h>
147#include <sys/proc.h>
148#include <sys/module.h>
149#include <sys/conf.h>
150#include <sys/dkstat.h>
151#include <sys/fcntl.h>
152#include <sys/interrupt.h>
153#include <sys/kernel.h>
154#include <sys/syslog.h>
155#include <sys/sysctl.h>
156#include <sys/bus.h>
157#include <machine/bus.h>
158#include <sys/rman.h>
159#include <sys/timetc.h>
160#include <sys/timepps.h>
161
162#ifdef PC98
163#include <pc98/pc98/pc98.h>
164#include <pc98/pc98/pc98_machdep.h>
165#include <i386/isa/ic/i8251.h>
166#else
167#include <isa/isareg.h>
168#endif
169#include <isa/isavar.h>
170#if NPCI > 0
171#include <pci/pcireg.h>
172#include <pci/pcivar.h>
173#endif
174#include <machine/lock.h>
175
176#include <machine/clock.h>
177#include <machine/ipl.h>
178#ifndef SMP
179#include <machine/lock.h>
180#endif
181#include <machine/resource.h>
182
183#include <isa/sioreg.h>
184
185#ifdef COM_ESP
186#include <i386/isa/ic/esp.h>
187#endif
188#include <i386/isa/ic/ns16550.h>
189#ifdef PC98
190#include <i386/isa/ic/rsa.h>
191#endif
192
193#ifndef __i386__
194#define disable_intr()
195#define enable_intr()
196#endif
197
198#ifdef SMP
199#define disable_intr() COM_DISABLE_INTR()
200#define enable_intr() COM_ENABLE_INTR()
201#endif /* SMP */
202
203#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */
204
205#define CALLOUT_MASK 0x80
206#define CONTROL_MASK 0x60
207#define CONTROL_INIT_STATE 0x20
208#define CONTROL_LOCK_STATE 0x40
209#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev)))
210#define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK)
211#define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK)
212
213#ifdef COM_MULTIPORT
214/* checks in flags for multiport and which is multiport "master chip"
215 * for a given card
216 */
217#define COM_ISMULTIPORT(flags) ((flags) & 0x01)
218#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff)
219#define COM_NOTAST4(flags) ((flags) & 0x04)
220#endif /* COM_MULTIPORT */
221
222#define COM_CONSOLE(flags) ((flags) & 0x10)
223#define COM_FORCECONSOLE(flags) ((flags) & 0x20)
224#define COM_LLCONSOLE(flags) ((flags) & 0x40)
225#define COM_DEBUGGER(flags) ((flags) & 0x80)
226#define COM_LOSESOUTINTS(flags) ((flags) & 0x08)
227#define COM_NOFIFO(flags) ((flags) & 0x02)
228#define COM_ST16650A(flags) ((flags) & 0x20000)
229#define COM_C_NOPROBE (0x40000)
230#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE)
231#define COM_C_IIR_TXRDYBUG (0x80000)
232#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG)
233#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24)
234
235#ifdef PC98
236#define com_emr com_msr /* Extension mode register for RSB-2000/3000 */
237#endif
238#define com_scr 7 /* scratch register for 16450-16550 (R/W) */
239
240#define sio_getreg(com, off) \
241 (bus_space_read_1((com)->bst, (com)->bsh, (off)))
242#define sio_setreg(com, off, value) \
243 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value)))
244
245/*
246 * com state bits.
247 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
248 * than the other bits so that they can be tested as a group without masking
249 * off the low bits.
250 *
251 * The following com and tty flags correspond closely:
252 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and
253 * comstop())
254 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart())
255 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam())
256 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam())
257 * TS_FLUSH is not used.
258 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON.
259 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state).
260 */
261#define CS_BUSY 0x80 /* output in progress */
262#define CS_TTGO 0x40 /* output not stopped by XOFF */
263#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */
264#define CS_CHECKMSR 1 /* check of MSR scheduled */
265#define CS_CTS_OFLOW 2 /* use CTS output flow control */
266#define CS_DTR_OFF 0x10 /* DTR held off */
267#define CS_ODONE 4 /* output completed */
268#define CS_RTS_IFLOW 8 /* use RTS input flow control */
269#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */
270
271static char const * const error_desc[] = {
272#define CE_OVERRUN 0
273 "silo overflow",
274#define CE_INTERRUPT_BUF_OVERFLOW 1
275 "interrupt-level buffer overflow",
276#define CE_TTY_BUF_OVERFLOW 2
277 "tty-level buffer overflow",
278};
279
280#define CE_NTYPES 3
281#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum])
282
283/* types. XXX - should be elsewhere */
284typedef u_int Port_t; /* hardware port */
285typedef u_char bool_t; /* boolean */
286
287/* queue of linear buffers */
288struct lbq {
289 u_char *l_head; /* next char to process */
290 u_char *l_tail; /* one past the last char to process */
291 struct lbq *l_next; /* next in queue */
292 bool_t l_queued; /* nonzero if queued */
293};
294
295/* com device structure */
296struct com_s {
297 u_int flags; /* Copy isa device flags */
298 u_char state; /* miscellaneous flag bits */
299 bool_t active_out; /* nonzero if the callout device is open */
300 u_char cfcr_image; /* copy of value written to CFCR */
301#ifdef COM_ESP
302 bool_t esp; /* is this unit a hayes esp board? */
303#endif
304 u_char extra_state; /* more flag bits, separate for order trick */
305 u_char fifo_image; /* copy of value written to FIFO */
306 bool_t hasfifo; /* nonzero for 16550 UARTs */
307 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */
308 bool_t loses_outints; /* nonzero if device loses output interrupts */
309 u_char mcr_image; /* copy of value written to MCR */
310#ifdef COM_MULTIPORT
311 bool_t multiport; /* is this unit part of a multiport device? */
312#endif /* COM_MULTIPORT */
313 bool_t no_irq; /* nonzero if irq is not attached */
314 bool_t gone; /* hardware disappeared */
315 bool_t poll; /* nonzero if polling is required */
316 bool_t poll_output; /* nonzero if polling for output is required */
317 int unit; /* unit number */
318 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */
319 u_int tx_fifo_size;
320 u_int wopeners; /* # processes waiting for DCD in open() */
321
322 /*
323 * The high level of the driver never reads status registers directly
324 * because there would be too many side effects to handle conveniently.
325 * Instead, it reads copies of the registers stored here by the
326 * interrupt handler.
327 */
328 u_char last_modem_status; /* last MSR read by intr handler */
329 u_char prev_modem_status; /* last MSR handled by high level */
330
331 u_char hotchar; /* ldisc-specific char to be handled ASAP */
332 u_char *ibuf; /* start of input buffer */
333 u_char *ibufend; /* end of input buffer */
334 u_char *ibufold; /* old input buffer, to be freed */
335 u_char *ihighwater; /* threshold in input buffer */
336 u_char *iptr; /* next free spot in input buffer */
337 int ibufsize; /* size of ibuf (not include error bytes) */
338 int ierroff; /* offset of error bytes in ibuf */
339
340 struct lbq obufq; /* head of queue of output buffers */
341 struct lbq obufs[2]; /* output buffers */
342
343 bus_space_tag_t bst;
344 bus_space_handle_t bsh;
345
346#ifdef PC98
347 Port_t cmd_port;
348 Port_t sts_port;
349 Port_t in_modem_port;
350 Port_t intr_ctrl_port;
351 Port_t rsabase; /* iobase address of a I/O-DATA RSA board */
352 int intr_enable;
353 int pc98_prev_modem_status;
354 int pc98_modem_delta;
355 int modem_car_chg_timer;
356 int pc98_prev_siocmd;
357 int pc98_prev_siomod;
358 int modem_checking;
359 int pc98_if_type;
360
361 bool_t pc98_8251fifo;
362 bool_t pc98_8251fifo_enable;
363#endif /* PC98 */
364 Port_t data_port; /* i/o ports */
365#ifdef COM_ESP
366 Port_t esp_port;
367#endif
368 Port_t int_id_port;
369 Port_t modem_ctl_port;
370 Port_t line_status_port;
371 Port_t modem_status_port;
372 Port_t intr_ctl_port; /* Ports of IIR register */
373
374 struct tty *tp; /* cross reference */
375
376 /* Initial state. */
377 struct termios it_in; /* should be in struct tty */
378 struct termios it_out;
379
380 /* Lock state. */
381 struct termios lt_in; /* should be in struct tty */
382 struct termios lt_out;
383
384 bool_t do_timestamp;
385 bool_t do_dcd_timestamp;
386 struct timeval timestamp;
387 struct timeval dcd_timestamp;
388 struct pps_state pps;
389
390 u_long bytes_in; /* statistics */
391 u_long bytes_out;
392 u_int delta_error_counts[CE_NTYPES];
393 u_long error_counts[CE_NTYPES];
394
395 struct resource *irqres;
396 struct resource *ioportres;
397 void *cookie;
398
399 /*
400 * Data area for output buffers. Someday we should build the output
401 * buffer queue without copying data.
402 */
403#ifdef PC98
404 int obufsize;
405 u_char *obuf1;
406 u_char *obuf2;
407#else
408 u_char obuf1[256];
409 u_char obuf2[256];
410#endif
411};
412
413#ifdef COM_ESP
414static int espattach __P((struct com_s *com, Port_t esp_port));
415#endif
416static int sioattach __P((device_t dev, int rid));
417static int sio_isa_attach __P((device_t dev));
418
419static timeout_t siobusycheck;
420static timeout_t siodtrwakeup;
421static void comhardclose __P((struct com_s *com));
422static void sioinput __P((struct com_s *com));
423static void siointr1 __P((struct com_s *com));
424static void siointr __P((void *arg));
425static int commctl __P((struct com_s *com, int bits, int how));
426static int comparam __P((struct tty *tp, struct termios *t));
427static swihand_t siopoll;
428static int sioprobe __P((device_t dev, int xrid));
429static int sio_isa_probe __P((device_t dev));
430static void siosettimeout __P((void));
431static int siosetwater __P((struct com_s *com, speed_t speed));
432static void comstart __P((struct tty *tp));
433static void comstop __P((struct tty *tp, int rw));
434static timeout_t comwakeup;
435static void disc_optim __P((struct tty *tp, struct termios *t,
436 struct com_s *com));
437
438#if NCARD > 0
439static int sio_pccard_attach __P((device_t dev));
440static int sio_pccard_detach __P((device_t dev));
441static int sio_pccard_probe __P((device_t dev));
442#endif /* NCARD > 0 */
443
444#if NPCI > 0
445static int sio_pci_attach __P((device_t dev));
446static void sio_pci_kludge_unit __P((device_t dev));
447static int sio_pci_probe __P((device_t dev));
448#endif /* NPCI > 0 */
449
450static char driver_name[] = "sio";
451
452/* table and macro for fast conversion from a unit number to its com struct */
453static devclass_t sio_devclass;
454#define com_addr(unit) ((struct com_s *) \
455 devclass_get_softc(sio_devclass, unit))
456
457static device_method_t sio_isa_methods[] = {
458 /* Device interface */
459 DEVMETHOD(device_probe, sio_isa_probe),
460 DEVMETHOD(device_attach, sio_isa_attach),
461
462 { 0, 0 }
463};
464
465static driver_t sio_isa_driver = {
466 driver_name,
467 sio_isa_methods,
468 sizeof(struct com_s),
469};
470
471#if NCARD > 0
472static device_method_t sio_pccard_methods[] = {
473 /* Device interface */
474 DEVMETHOD(device_probe, sio_pccard_probe),
475 DEVMETHOD(device_attach, sio_pccard_attach),
476 DEVMETHOD(device_detach, sio_pccard_detach),
477
478 { 0, 0 }
479};
480
481static driver_t sio_pccard_driver = {
482 driver_name,
483 sio_pccard_methods,
484 sizeof(struct com_s),
485};
486#endif /* NCARD > 0 */
487
488#if NPCI > 0
489static device_method_t sio_pci_methods[] = {
490 /* Device interface */
491 DEVMETHOD(device_probe, sio_pci_probe),
492 DEVMETHOD(device_attach, sio_pci_attach),
493
494 { 0, 0 }
495};
496
497static driver_t sio_pci_driver = {
498 driver_name,
499 sio_pci_methods,
500 sizeof(struct com_s),
501};
502#endif /* NPCI > 0 */
503
504static d_open_t sioopen;
505static d_close_t sioclose;
506static d_read_t sioread;
507static d_write_t siowrite;
508static d_ioctl_t sioioctl;
509
510#define CDEV_MAJOR 28
511static struct cdevsw sio_cdevsw = {
512 /* open */ sioopen,
513 /* close */ sioclose,
514 /* read */ sioread,
515 /* write */ siowrite,
516 /* ioctl */ sioioctl,
517 /* poll */ ttypoll,
518 /* mmap */ nommap,
519 /* strategy */ nostrategy,
520 /* name */ driver_name,
521 /* maj */ CDEV_MAJOR,
522 /* dump */ nodump,
523 /* psize */ nopsize,
524 /* flags */ D_TTY,
525 /* bmaj */ -1
526};
527
528int comconsole = -1;
529static volatile speed_t comdefaultrate = CONSPEED;
530#ifdef __alpha__
531static volatile speed_t gdbdefaultrate = CONSPEED;
532#endif
533static u_int com_events; /* input chars + weighted output completions */
534static Port_t siocniobase;
535static int siocnunit;
536static Port_t siogdbiobase;
537static int siogdbunit = -1;
538static bool_t sio_registered;
539static int sio_timeout;
540static int sio_timeouts_until_log;
541static struct callout_handle sio_timeout_handle
542 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
543static int sio_numunits;
544
545#ifdef PC98
546struct siodev {
547 short if_type;
548 short irq;
549 Port_t cmd, sts, ctrl, mod;
550};
551static int sysclock;
552
553#define COM_INT_DISABLE {int previpri; previpri=spltty();
554#define COM_INT_ENABLE splx(previpri);}
555#define IEN_TxFLAG IEN_Tx
556
557#define COM_CARRIER_DETECT_EMULATE 0
558#define PC98_CHECK_MODEM_INTERVAL (hz/10)
559#define DCD_OFF_TOLERANCE 2
560#define DCD_ON_RECOGNITION 2
561#define GET_IFTYPE(flags) ((flags >> 24) & 0x1f)
562#define SET_IFTYPE(type) (type << 24)
563#define IS_8251(if_type) (!(if_type & 0x10))
564#define COM1_EXT_CLOCK 0x40000
565
566static void commint __P((dev_t dev));
567static void com_tiocm_set __P((struct com_s *com, int msr));
568static void com_tiocm_bis __P((struct com_s *com, int msr));
569static void com_tiocm_bic __P((struct com_s *com, int msr));
570static int com_tiocm_get __P((struct com_s *com));
571static int com_tiocm_get_delta __P((struct com_s *com));
572static void pc98_msrint_start __P((dev_t dev));
573static void com_cflag_and_speed_set __P((struct com_s *com, int cflag, int speed));
574static int pc98_ttspeedtab __P((struct com_s *com, int speed));
575static int pc98_get_modem_status __P((struct com_s *com));
576static timeout_t pc98_check_msr;
577static void pc98_set_baud_rate __P((struct com_s *com, int count));
578static void pc98_i8251_reset __P((struct com_s *com, int mode, int command));
579static void pc98_disable_i8251_interrupt __P((struct com_s *com, int mod));
580static void pc98_enable_i8251_interrupt __P((struct com_s *com, int mod));
581static int pc98_check_i8251_interrupt __P((struct com_s *com));
582static int pc98_i8251_get_cmd __P((struct com_s *com));
583static int pc98_i8251_get_mod __P((struct com_s *com));
584static void pc98_i8251_set_cmd __P((struct com_s *com, int x));
585static void pc98_i8251_or_cmd __P((struct com_s *com, int x));
586static void pc98_i8251_clear_cmd __P((struct com_s *com, int x));
587static void pc98_i8251_clear_or_cmd __P((struct com_s *com, int clr, int x));
588static int pc98_check_if_type __P((device_t dev, struct siodev *iod));
589static int pc98_check_8251vfast __P((void));
590static int pc98_check_8251fifo __P((void));
591static void pc98_check_sysclock __P((void));
592static void pc98_set_ioport __P((struct com_s *com));
593
594#define com_int_Tx_disable(com) \
595 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP)
596#define com_int_Tx_enable(com) \
597 pc98_enable_i8251_interrupt(com,IEN_TxFLAG)
598#define com_int_Rx_disable(com) \
599 pc98_disable_i8251_interrupt(com,IEN_Rx)
600#define com_int_Rx_enable(com) \
601 pc98_enable_i8251_interrupt(com,IEN_Rx)
602#define com_int_TxRx_disable(com) \
603 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx)
604#define com_int_TxRx_enable(com) \
605 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx)
606#define com_send_break_on(com) \
607 pc98_i8251_or_cmd(com,CMD8251_SBRK)
608#define com_send_break_off(com) \
609 pc98_i8251_clear_cmd(com,CMD8251_SBRK)
610
611static struct speedtab pc98speedtab[] = { /* internal RS232C interface */
612 { 0, 0, },
613 { 50, 50, },
614 { 75, 75, },
615 { 150, 150, },
616 { 200, 200, },
617 { 300, 300, },
618 { 600, 600, },
619 { 1200, 1200, },
620 { 2400, 2400, },
621 { 4800, 4800, },
622 { 9600, 9600, },
623 { 19200, 19200, },
624 { 38400, 38400, },
625 { 51200, 51200, },
626 { 76800, 76800, },
627 { 20800, 20800, },
628 { 31200, 31200, },
629 { 41600, 41600, },
630 { 62400, 62400, },
631 { -1, -1 }
632};
633static struct speedtab pc98fast_speedtab[] = {
634 { 9600, 0x80 | COMBRD(9600), },
635 { 19200, 0x80 | COMBRD(19200), },
636 { 38400, 0x80 | COMBRD(38400), },
637 { 57600, 0x80 | COMBRD(57600), },
638 { 115200, 0x80 | COMBRD(115200), },
639 { -1, -1 }
640};
641static struct speedtab comspeedtab_pio9032b[] = {
642 { 300, 6, },
643 { 600, 5, },
644 { 1200, 4, },
645 { 2400, 3, },
646 { 4800, 2, },
647 { 9600, 1, },
648 { 19200, 0, },
649 { 38400, 7, },
650 { -1, -1 }
651};
652static struct speedtab comspeedtab_b98_01[] = {
653 { 75, 11, },
654 { 150, 10, },
655 { 300, 9, },
656 { 600, 8, },
657 { 1200, 7, },
658 { 2400, 6, },
659 { 4800, 5, },
660 { 9600, 4, },
661 { 19200, 3, },
662 { 38400, 2, },
663 { 76800, 1, },
664 { 153600, 0, },
665 { -1, -1 }
666};
667static struct speedtab comspeedtab_mc16550[] = {
668 { 300, 1536, },
669 { 600, 768, },
670 { 1200, 384, },
671 { 2400, 192, },
672 { 4800, 96, },
673 { 9600, 48, },
674 { 19200, 24, },
675 { 38400, 12, },
676 { 57600, 8, },
677 { 115200, 4, },
678 { 153600, 3, },
679 { 230400, 2, },
680 { 460800, 1, },
681 { -1, -1 }
682};
683static struct speedtab comspeedtab_rsb384[] = {
684 { 300, 3840, },
685 { 600, 1920, },
686 { 1200, 960, },
687 { 2400, 480, },
688 { 4800, 240, },
689 { 9600, 120, },
690 { 19200, 60, },
691 { 38400, 30, },
692 { 57600, 20, },
693 { 115200, 10, },
694 { 128000, 9, },
695 { 144000, 8, },
696 { 192000, 6, },
697 { 230400, 5, },
698 { 288000, 4, },
699 { 384000, 3, },
700 { 576000, 2, },
701 { 1152000, 1, },
702 { -1, -1 }
703};
704static struct speedtab comspeedtab_rsa[] = {
705 { 0, 0 },
706 { 50, COMBRD_RSA(50) },
707 { 75, COMBRD_RSA(75) },
708 { 110, COMBRD_RSA(110) },
709 { 134, COMBRD_RSA(134) },
710 { 150, COMBRD_RSA(150) },
711 { 200, COMBRD_RSA(200) },
712 { 300, COMBRD_RSA(300) },
713 { 600, COMBRD_RSA(600) },
714 { 1200, COMBRD_RSA(1200) },
715 { 1800, COMBRD_RSA(1800) },
716 { 2400, COMBRD_RSA(2400) },
717 { 4800, COMBRD_RSA(4800) },
718 { 9600, COMBRD_RSA(9600) },
719 { 19200, COMBRD_RSA(19200) },
720 { 38400, COMBRD_RSA(38400) },
721 { 57600, COMBRD_RSA(57600) },
722 { 115200, COMBRD_RSA(115200) },
723 { 230400, COMBRD_RSA(230400) },
724 { 460800, COMBRD_RSA(460800) },
725 { 921600, COMBRD_RSA(921600) },
726 { -1, -1 }
727};
728#endif /* PC98 */
729
730static struct speedtab comspeedtab[] = {
731 { 0, 0 },
732 { 50, COMBRD(50) },
733 { 75, COMBRD(75) },
734 { 110, COMBRD(110) },
735 { 134, COMBRD(134) },
736 { 150, COMBRD(150) },
737 { 200, COMBRD(200) },
738 { 300, COMBRD(300) },
739 { 600, COMBRD(600) },
740 { 1200, COMBRD(1200) },
741 { 1800, COMBRD(1800) },
742 { 2400, COMBRD(2400) },
743 { 4800, COMBRD(4800) },
744 { 9600, COMBRD(9600) },
745 { 19200, COMBRD(19200) },
746 { 38400, COMBRD(38400) },
747 { 57600, COMBRD(57600) },
748 { 115200, COMBRD(115200) },
749 { -1, -1 }
750};
751
752#ifdef PC98
753struct {
754 char *name;
755 short port_table[7];
756 short irr_mask;
757 struct speedtab *speedtab;
758 short check_irq;
759} if_8251_type[] = {
760 /* COM_IF_INTERNAL */
761 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1},
762 -1, pc98speedtab, 1 },
763 /* COM_IF_PC9861K_1 */
764 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1},
765 3, NULL, 1 },
766 /* COM_IF_PC9861K_2 */
767 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1},
768 3, NULL, 1 },
769 /* COM_IF_IND_SS_1 */
770 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1},
771 3, comspeedtab_mc16550, 1 },
772 /* COM_IF_IND_SS_2 */
773 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1},
774 3, comspeedtab_mc16550, 1 },
775 /* COM_IF_PIO9032B_1 */
776 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1},
777 7, comspeedtab_pio9032b, 1 },
778 /* COM_IF_PIO9032B_2 */
779 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1},
780 7, comspeedtab_pio9032b, 1 },
781 /* COM_IF_B98_01_1 */
782 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3},
783 7, comspeedtab_b98_01, 0 },
784 /* COM_IF_B98_01_2 */
785 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7},
786 7, comspeedtab_b98_01, 0 },
787};
788#define PC98SIO_data_port(type) (if_8251_type[type].port_table[0])
789#define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1])
790#define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2])
791#define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3])
792#define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4])
793#define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5])
794#define PC98SIO_func_port(type) (if_8251_type[type].port_table[6])
795
796#define I8251F_data 0x130
797#define I8251F_lsr 0x132
798#define I8251F_msr 0x134
799#define I8251F_iir 0x136
800#define I8251F_fcr 0x138
801#define I8251F_div 0x13a
802
803
804static bus_addr_t port_table_0[] =
805 {0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007};
806static bus_addr_t port_table_1[] =
807 {0x000, 0x002, 0x004, 0x006, 0x008, 0x00a, 0x00c, 0x00e};
808static bus_addr_t port_table_8[] =
809 {0x000, 0x100, 0x200, 0x300, 0x400, 0x500, 0x600, 0x700};
810static bus_addr_t port_table_rsa[] = {
811 0x008, 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f,
812 0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007
813};
814
815struct {
816 char *name;
817 short irr_read;
818 short irr_write;
819 bus_addr_t *iat;
820 bus_size_t iatsz;
821 struct speedtab *speedtab;
822} if_16550a_type[] = {
823 /* COM_IF_RSA98 */
824 {" (RSA-98)", -1, -1, port_table_0, IO_COMSIZE, comspeedtab},
825 /* COM_IF_NS16550 */
826 {"", -1, -1, port_table_0, IO_COMSIZE, comspeedtab},
827 /* COM_IF_SECOND_CCU */
828 {"", -1, -1, port_table_0, IO_COMSIZE, comspeedtab},
829 /* COM_IF_MC16550II */
830 {" (MC16550II)", -1, 0x1000, port_table_8, IO_COMSIZE,
831 comspeedtab_mc16550},
832 /* COM_IF_MCRS98 */
833 {" (MC-RS98)", -1, 0x1000, port_table_8, IO_COMSIZE,
834 comspeedtab_mc16550},
835 /* COM_IF_RSB3000 */
836 {" (RSB-3000)", 0xbf, -1, port_table_1, IO_COMSIZE,
837 comspeedtab_rsb384},
838 /* COM_IF_RSB384 */
839 {" (RSB-384)", 0xbf, -1, port_table_1, IO_COMSIZE, comspeedtab_rsb384},
840 /* COM_IF_MODEM_CARD */
841 {"", -1, -1, port_table_0, IO_COMSIZE, comspeedtab},
842 /* COM_IF_RSA98III */
843 {" (RSA-98III)", -1, -1, port_table_rsa, 16, comspeedtab_rsa},
844 /* COM_IF_ESP98 */
845 {" (ESP98)", -1, -1, port_table_1, IO_COMSIZE, comspeedtab_mc16550},
846};
847#endif /* PC98 */
848
849#ifdef COM_ESP
850#ifdef PC98
851
852/* XXX configure this properly. */
853static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 };
854static Port_t likely_esp_ports[] = { 0xc0d0, 0 };
855
856#define ESP98_CMD1 (ESP_CMD1 * 0x100)
857#define ESP98_CMD2 (ESP_CMD2 * 0x100)
858#define ESP98_STATUS1 (ESP_STATUS1 * 0x100)
859#define ESP98_STATUS2 (ESP_STATUS2 * 0x100)
860
861#else /* PC98 */
862
863/* XXX configure this properly. */
864static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
865static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
866
867#endif /* PC98 */
868#endif
869
870/*
871 * handle sysctl read/write requests for console speed
872 *
873 * In addition to setting comdefaultrate for I/O through /dev/console,
874 * also set the initial and lock values for the /dev/ttyXX device
875 * if there is one associated with the console. Finally, if the /dev/tty
876 * device has already been open, change the speed on the open running port
877 * itself.
878 */
879
880static int
|
882{
883 int error, s;
884 speed_t newspeed;
885 struct com_s *com;
886 struct tty *tp;
887
888 newspeed = comdefaultrate;
889
890 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req);
891 if (error || !req->newptr)
892 return (error);
893
894 comdefaultrate = newspeed;
895
896 if (comconsole < 0) /* serial console not selected? */
897 return (0);
898
899 com = com_addr(comconsole);
900 if (com == NULL)
901 return (ENXIO);
902
903 /*
904 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX
905 * (note, the lock rates really are boolean -- if non-zero, disallow
906 * speed changes)
907 */
908 com->it_in.c_ispeed = com->it_in.c_ospeed =
909 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
910 com->it_out.c_ispeed = com->it_out.c_ospeed =
911 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate;
912
913 /*
914 * if we're open, change the running rate too
915 */
916 tp = com->tp;
917 if (tp && (tp->t_state & TS_ISOPEN)) {
918 tp->t_termios.c_ispeed =
919 tp->t_termios.c_ospeed = comdefaultrate;
920 s = spltty();
921 error = comparam(tp, &tp->t_termios);
922 splx(s);
923 }
924 return error;
925}
926
927SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW,
928 0, 0, sysctl_machdep_comdefaultrate, "I", "");
929
930#define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit))
931#define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit))
932
933#if NCARD > 0
934static int
935sio_pccard_probe(dev)
936 device_t dev;
937{
938 /* Do not probe IRQ - pccard doesn't turn on the interrupt line */
939 /* until bus_setup_intr */
940 SET_FLAG(dev, COM_C_NOPROBE);
941
942 return (sioprobe(dev, 0));
943}
944
945static int
946sio_pccard_attach(dev)
947 device_t dev;
948{
949 return (sioattach(dev, 0));
950}
951
952/*
953 * sio_detach - unload the driver and clear the table.
954 * XXX TODO:
955 * This is usually called when the card is ejected, but
956 * can be caused by a modunload of a controller driver.
957 * The idea is to reset the driver's view of the device
958 * and ensure that any driver entry points such as
959 * read and write do not hang.
960 */
961static int
962sio_pccard_detach(dev)
963 device_t dev;
964{
965 struct com_s *com;
966
967 com = (struct com_s *) device_get_softc(dev);
968 if (com == NULL) {
969 device_printf(dev, "NULL com in siounload\n");
970 return (0);
971 }
972 com->gone = 1;
973 if (com->irqres) {
974 bus_teardown_intr(dev, com->irqres, com->cookie);
975 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres);
976 }
977 if (com->ioportres)
978 bus_release_resource(dev, SYS_RES_IOPORT, 0, com->ioportres);
979 if (com->tp && (com->tp->t_state & TS_ISOPEN)) {
980 device_printf(dev, "still open, forcing close\n");
981 com->tp->t_gen++;
982 ttyclose(com->tp);
983 ttwakeup(com->tp);
984 ttwwakeup(com->tp);
985 } else {
986 if (com->ibuf != NULL)
987 free(com->ibuf, M_DEVBUF);
988 }
989 device_printf(dev, "unloaded\n");
990 return (0);
991}
992#endif /* NCARD > 0 */
993
994#if NPCI > 0
995struct pci_ids {
996 u_int32_t type;
997 const char *desc;
998 int rid;
999};
1000
1001static struct pci_ids pci_ids[] = {
1002 { 0x100812b9, "3COM PCI FaxModem", 0x10 },
1003 { 0x048011c1, "ActionTec 56k FAX PCI Modem", 0x14 },
1004 { 0x00000000, NULL, 0 }
1005};
1006
1007static int
1008sio_pci_attach(dev)
1009 device_t dev;
1010{
1011 u_int32_t type;
1012 struct pci_ids *id;
1013
1014 type = pci_get_devid(dev);
1015 id = pci_ids;
1016 while (id->type && id->type != type)
1017 id++;
1018 if (id->desc == NULL)
1019 return (ENXIO);
1020 sio_pci_kludge_unit(dev);
1021 return (sioattach(dev, id->rid));
1022}
1023
1024/*
1025 * Don't cut and paste this to other drivers. It is a horrible kludge
1026 * which will fail to work and also be unnecessary in future versions.
1027 */
1028static void
1029sio_pci_kludge_unit(dev)
1030 device_t dev;
1031{
1032 devclass_t dc;
1033 int err;
1034 int start;
1035 int unit;
1036
1037 unit = 0;
1038 start = 0;
1039 while (resource_int_value("sio", unit, "port", &start) == 0 &&
1040 start > 0)
1041 unit++;
1042 if (device_get_unit(dev) < unit) {
1043 dc = device_get_devclass(dev);
1044 while (devclass_get_device(dc, unit))
1045 unit++;
1046 device_printf(dev, "moving to sio%d\n", unit);
1047 err = device_set_unit(dev, unit); /* EVIL DO NOT COPY */
1048 if (err)
1049 device_printf(dev, "error moving device %d\n", err);
1050 }
1051}
1052
1053static int
1054sio_pci_probe(dev)
1055 device_t dev;
1056{
1057 u_int32_t type;
1058 struct pci_ids *id;
1059
1060 type = pci_get_devid(dev);
1061 id = pci_ids;
1062 while (id->type && id->type != type)
1063 id++;
1064 if (id->desc == NULL)
1065 return (ENXIO);
1066 device_set_desc(dev, id->desc);
1067 return (sioprobe(dev, id->rid));
1068}
1069#endif /* NPCI > 0 */
1070
1071static struct isa_pnp_id sio_ids[] = {
1072 {0x0005d041, "Standard PC COM port"}, /* PNP0500 */
1073 {0x0105d041, "16550A-compatible COM port"}, /* PNP0501 */
1074 {0x0205d041, "Multiport serial device (non-intelligent 16550)"}, /* PNP0502 */
1075 {0x1005d041, "Generic IRDA-compatible device"}, /* PNP0510 */
1076 {0x1105d041, "Generic IRDA-compatible device"}, /* PNP0511 */
1077 /* Devices that do not have a compatid */
1078 {0x7602a904, NULL}, /* AEI0276 - 56K v.90 Fax Modem (LKT) */
1079 {0x00007905, NULL}, /* AKY0000 - 56K Plug&Play Modem */
1080 {0x01405407, NULL}, /* AZT4001 - AZT3000 PnP SOUND DEVICE, MODEM */
1081 {0x56039008, NULL}, /* BDP0356 - Best Data 56x2 */
1082 {0x36339008, NULL}, /* BDP3336 - Best Data Prods. 336F */
1083 {0x0014490a, NULL}, /* BRI1400 - Boca 33.6 PnP */
1084 {0x0015490a, NULL}, /* BRI1500 - Internal Fax Data */
1085 {0x0034490a, NULL}, /* BRI3400 - Internal ACF Modem */
1086 {0x00b4490a, NULL}, /* BRIB400 - Boca 56k PnP */
1087 {0x0030320d, NULL}, /* CIR3000 - Cirrus Logic V43 */
1088 {0x0100440e, NULL}, /* CRD0001 - Cardinal MVP288IV ? */
1089 {0x1200c31e, NULL}, /* GVC0012 - VF1128HV-R9 (win modem?) */
1090 {0x0303c31e, NULL}, /* GVC0303 - MaxTech 33.6 PnP D/F/V */
1091 {0x0505c31e, NULL}, /* GVC0505 - GVC 56k Faxmodem */
1092 {0x0050c31e, NULL}, /* GVC5000 - some GVC modem */
1093 {0x3800f91e, NULL}, /* GWY0038 - Telepath with v.90 */
1094 {0x9062f91e, NULL}, /* GWY6290 - Telepath with x2 Technology */
1095 {0x0000f435, NULL}, /* MOT0000 - Motorola ModemSURFR 33.6 Intern */
1096 {0x5015f435, NULL}, /* MOT1550 - Motorola ModemSURFR 56K Modem */
1097 {0xf015f435, NULL}, /* MOT15F0 - Motorola VoiceSURFR 56K Modem */
1098 {0x6045f435, NULL}, /* MOT4560 - Motorola ? */
1099 {0x61e7a338, NULL}, /* NECE761 - 33.6Modem */
1100 {0x39804f3f, NULL}, /* OZO8039 - Zoom 56k flex */
1101 {0x3024a341, NULL}, /* PMC2430 - Pace 56 Voice Internal Modem */
1102 {0x1000eb49, NULL}, /* ROK0010 - Rockwell ? */
1103 {0x5002734a, NULL}, /* RSS0250 - 5614Jx3(G) Internal Modem */
1104 {0xc100ad4d, NULL}, /* SMM00C1 - Leopard 56k PnP */
1105 {0x9012b04e, NULL}, /* SUP1290 - Supra ? */
1106 {0x1013b04e, NULL}, /* SUP1310 - SupraExpress 336i PnP */
1107 {0x8013b04e, NULL}, /* SUP1380 - SupraExpress 288i PnP Voice */
1108 {0x8113b04e, NULL}, /* SUP1381 - SupraExpress 336i PnP Voice */
1109 {0x5016b04e, NULL}, /* SUP1650 - Supra 336i Sp Intl */
1110 {0x7420b04e, NULL}, /* SUP2070 - Supra ? */
1111 {0x8020b04e, NULL}, /* SUP2080 - Supra ? */
1112 {0x8420b04e, NULL}, /* SUP2084 - SupraExpress 56i PnP */
1113 {0x7121b04e, NULL}, /* SUP2171 - SupraExpress 56i Sp? */
1114 {0x8024b04e, NULL}, /* SUP2480 - Supra ? */
1115 {0x01007256, NULL}, /* USR0001 - U.S. Robotics Inc., Sportster W */
1116 {0x02007256, NULL}, /* USR0002 - U.S. Robotics Inc. Sportster 33. */
1117 {0x04007256, NULL}, /* USR0004 - USR Sportster 14.4k */
1118 {0x06007256, NULL}, /* USR0006 - USR Sportster 33.6k */
1119 {0x11007256, NULL}, /* USR0011 - USR ? */
1120 {0x01017256, NULL}, /* USR0101 - USR ? */
1121 {0x30207256, NULL}, /* USR2030 - U.S.Robotics Inc. Sportster 560 */
1122 {0x50207256, NULL}, /* USR2050 - U.S.Robotics Inc. Sportster 33. */
1123 {0x70207256, NULL}, /* USR2070 - U.S.Robotics Inc. Sportster 560 */
1124 {0x30307256, NULL}, /* USR3030 - U.S. Robotics 56K FAX INT */
1125 {0x31307256, NULL}, /* USR3031 - U.S. Robotics 56K FAX INT */
1126 {0x50307256, NULL}, /* USR3050 - U.S. Robotics 56K FAX INT */
1127 {0x70307256, NULL}, /* USR3070 - U.S. Robotics 56K Voice INT */
1128 {0x90307256, NULL}, /* USR3090 - USR ? */
1129 {0x90917256, NULL}, /* USR9190 - USR 56k Voice INT */
1130 {0x0300695c, NULL}, /* WCI0003 - Fax/Voice/Modem/Speakphone/Asvd */
1131 {0x61f7896a, NULL}, /* ZTIF761 - Zoom ComStar 33.6 */
1132#ifdef PC98
1133 {0x0100e4a5, "RSA-98III"},
1134#endif
1135 {0}
1136};
1137
1138
1139
1140static int
1141sio_isa_probe(dev)
1142 device_t dev;
1143{
1144#ifdef PC98
1145 int logical_id;
1146#endif
1147 /* Check isapnp ids */
1148 if (ISA_PNP_PROBE(device_get_parent(dev), dev, sio_ids) == ENXIO)
1149 return (ENXIO);
1150#ifdef PC98
1151 logical_id = isa_get_logicalid(dev);
1152 if (logical_id == 0x0100e4a5) /* RSA-98III */
1153 device_set_flags(dev, SET_IFTYPE(COM_IF_RSA98III));
1154#endif
1155 return (sioprobe(dev, 0));
1156}
1157
1158static int
1159sioprobe(dev, xrid)
1160 device_t dev;
1161 int xrid;
1162{
1163#if 0
1164 static bool_t already_init;
1165 device_t xdev;
1166#endif
1167 struct com_s *com;
1168 bool_t failures[10];
1169 int fn;
1170 device_t idev;
1171 Port_t iobase;
1172 intrmask_t irqmap[4];
1173 intrmask_t irqs;
1174 u_char mcr_image;
1175 int result;
1176 u_long xirq;
1177 u_int flags = device_get_flags(dev);
1178 int rid;
1179 struct resource *port;
1180#ifdef PC98
1181 int tmp;
1182 struct siodev iod;
1183#endif
1184
1185#ifdef PC98
1186 iod.if_type = GET_IFTYPE(flags);
1187 if ((iod.if_type < 0 || iod.if_type > COM_IF_END1) &&
1188 (iod.if_type < 0x10 || iod.if_type > COM_IF_END2))
1189 return ENXIO;
1190#endif
1191
1192 rid = xrid;
1193#ifdef PC98
1194 if (IS_8251(iod.if_type)) {
1195 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1196 0, ~0, 1, RF_ACTIVE);
1197 } else if (iod.if_type == COM_IF_RSA98III ||
1198 isa_get_vendorid(dev)) {
1199 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0,
1200 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE);
1201 } else {
1202 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid,
1203 if_16550a_type[iod.if_type & 0x0f].iat,
1204 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE);
1205 }
1206#else
1207 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1208 0, ~0, IO_COMSIZE, RF_ACTIVE);
1209#endif
1210 if (!port)
1211 return (ENXIO);
1212#ifdef PC98
1213 if (!IS_8251(iod.if_type)) {
1214 if (isa_load_resourcev(port,
1215 if_16550a_type[iod.if_type & 0x0f].iat,
1216 if_16550a_type[iod.if_type & 0x0f].iatsz) != 0) {
1217 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1218 return ENXIO;
1219 }
1220 }
1221#endif
1222
1223 com = device_get_softc(dev);
1224 com->bst = rman_get_bustag(port);
1225 com->bsh = rman_get_bushandle(port);
1226
1227#if 0
1228 /*
1229 * XXX this is broken - when we are first called, there are no
1230 * previously configured IO ports. We could hard code
1231 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse.
1232 * This code has been doing nothing since the conversion since
1233 * "count" is zero the first time around.
1234 */
1235 if (!already_init) {
1236 /*
1237 * Turn off MCR_IENABLE for all likely serial ports. An unused
1238 * port with its MCR_IENABLE gate open will inhibit interrupts
1239 * from any used port that shares the interrupt vector.
1240 * XXX the gate enable is elsewhere for some multiports.
1241 */
1242 device_t *devs;
1243 int count, i, xioport;
1244#ifdef PC98
1245 int xiftype;
1246#endif
1247
1248 devclass_get_devices(sio_devclass, &devs, &count);
1249#ifdef PC98
1250 for (i = 0; i < count; i++) {
1251 xdev = devs[i];
1252 xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0);
1253 xiftype = GET_IFTYPE(device_get_flags(xdev));
1254 if (device_is_enabled(xdev) && xioport > 0) {
1255 if (IS_8251(xiftype))
1256 outb((xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2);
1257 else
1258 outb(xioport + if_16550a_type[xiftype & 0x0f].iat[com_mcr], 0);
1259 }
1260 }
1261#else
1262 for (i = 0; i < count; i++) {
1263 xdev = devs[i];
1264 if (device_is_enabled(xdev) &&
1265 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport,
1266 NULL) == 0)
1267 outb(xioport + com_mcr, 0);
1268 }
1269#endif
1270 free(devs, M_TEMP);
1271 already_init = TRUE;
1272 }
1273#endif
1274
1275 if (COM_LLCONSOLE(flags)) {
1276 printf("sio%d: reserved for low-level i/o\n",
1277 device_get_unit(dev));
1278 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1279 return (ENXIO);
1280 }
1281
1282#ifdef PC98
1283 DELAY(10);
1284
1285 /*
1286 * If the port is i8251 UART (internal, B98_01)
1287 */
1288 if (pc98_check_if_type(dev, &iod) == -1) {
1289 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1290 return (ENXIO);
1291 }
1292 if (iod.irq > 0)
1293 bus_set_resource(dev, SYS_RES_IRQ, 0, iod.irq, 1);
1294 if (IS_8251(iod.if_type)) {
1295 outb(iod.cmd, 0);
1296 DELAY(10);
1297 outb(iod.cmd, 0);
1298 DELAY(10);
1299 outb(iod.cmd, 0);
1300 DELAY(10);
1301 outb(iod.cmd, CMD8251_RESET);
1302 DELAY(1000); /* for a while...*/
1303 outb(iod.cmd, 0xf2); /* MODE (dummy) */
1304 DELAY(10);
1305 outb(iod.cmd, 0x01); /* CMD (dummy) */
1306 DELAY(1000); /* for a while...*/
1307 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) {
1308 result = (ENXIO);
1309 }
1310 if (if_8251_type[iod.if_type & 0x0f].check_irq) {
1311 COM_INT_DISABLE
1312 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx));
1313 outb( iod.ctrl, tmp|IEN_TxEMP );
1314 DELAY(10);
1315 result = isa_irq_pending() ? 0 : ENXIO;
1316 outb( iod.ctrl, tmp );
1317 COM_INT_ENABLE
1318 } else {
1319 /*
1320 * B98_01 doesn't activate TxEMP interrupt line
1321 * when being reset, so we can't check irq pending.
1322 */
1323 result = 0;
1324 }
1325 if (epson_machine_id==0x20) { /* XXX */
1326 result = 0;
1327 }
1328 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1329 return result;
1330 }
1331#endif /* PC98 */
1332 /*
1333 * If the device is on a multiport card and has an AST/4
1334 * compatible interrupt control register, initialize this
1335 * register and prepare to leave MCR_IENABLE clear in the mcr.
1336 * Otherwise, prepare to set MCR_IENABLE in the mcr.
1337 * Point idev to the device struct giving the correct id_irq.
1338 * This is the struct for the master device if there is one.
1339 */
1340 idev = dev;
1341 mcr_image = MCR_IENABLE;
1342#ifdef COM_MULTIPORT
1343 if (COM_ISMULTIPORT(flags)) {
1344#ifndef PC98
1345 Port_t xiobase;
1346 u_long io;
1347#endif
1348
1349 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
1350 if (idev == NULL) {
1351 printf("sio%d: master device %d not configured\n",
1352 device_get_unit(dev), COM_MPMASTER(flags));
1353 idev = dev;
1354 }
1355#ifndef PC98
1356 if (!COM_NOTAST4(flags)) {
1357 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io,
1358 NULL) == 0) {
1359 xiobase = io;
1360 if (bus_get_resource(idev, SYS_RES_IRQ, 0,
1361 NULL, NULL) == 0)
1362 outb(xiobase + com_scr, 0x80);
1363 else
1364 outb(xiobase + com_scr, 0);
1365 }
1366 mcr_image = 0;
1367 }
1368#endif
1369 }
1370#endif /* COM_MULTIPORT */
1371 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0)
1372 mcr_image = 0;
1373
1374 bzero(failures, sizeof failures);
1375 iobase = rman_get_start(port);
1376
1377#ifdef PC98
1378 if (iod.if_type == COM_IF_RSA98III) {
1379 mcr_image = 0;
1380
1381 outb(iobase + rsa_msr, 0x04);
1382 outb(iobase + rsa_frr, 0x00);
1383 if ((inb(iobase + rsa_srr) & 0x36) != 0x36) {
1384 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1385 return (ENXIO);
1386 }
1387 outb(iobase + rsa_ier, 0x00);
1388 outb(iobase + rsa_frr, 0x00);
1389 outb(iobase + rsa_tivsr, 0x00);
1390 outb(iobase + rsa_tcr, 0x00);
1391 }
1392
1393 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write;
1394 if (tmp != -1) {
1395 /* MC16550II */
1396 int irqout;
1397 switch (isa_get_irq(idev)) {
1398 case 3: irqout = 4; break;
1399 case 5: irqout = 5; break;
1400 case 6: irqout = 6; break;
1401 case 12: irqout = 7; break;
1402 default:
1403 printf("sio%d: irq configuration error\n",
1404 device_get_unit(dev));
1405 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1406 return (ENXIO);
1407 }
1408 outb((iobase & 0x00ff) | tmp, irqout);
1409 }
1410#endif
1411
1412 /*
1413 * We don't want to get actual interrupts, just masked ones.
1414 * Interrupts from this line should already be masked in the ICU,
1415 * but mask them in the processor as well in case there are some
1416 * (misconfigured) shared interrupts.
1417 */
1418 disable_intr();
1419/* EXTRA DELAY? */
1420
1421 /*
1422 * Initialize the speed and the word size and wait long enough to
1423 * drain the maximum of 16 bytes of junk in device output queues.
1424 * The speed is undefined after a master reset and must be set
1425 * before relying on anything related to output. There may be
1426 * junk after a (very fast) soft reboot and (apparently) after
1427 * master reset.
1428 * XXX what about the UART bug avoided by waiting in comparam()?
1429 * We don't want to to wait long enough to drain at 2 bps.
1430 */
1431 if (iobase == siocniobase)
1432 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
1433 else {
1434#ifdef PC98
1435 tmp = ttspeedtab(SIO_TEST_SPEED,
1436 if_16550a_type[iod.if_type & 0x0f].speedtab);
1437 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS);
1438 sio_setreg(com, com_dlbl, tmp & 0xff);
1439 sio_setreg(com, com_dlbh, (tmp >> 8) & 0xff);
1440 sio_setreg(com, com_cfcr, CFCR_8BITS);
1441#else
1442 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS);
1443 sio_setreg(com, com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff);
1444 sio_setreg(com, com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8);
1445 sio_setreg(com, com_cfcr, CFCR_8BITS);
1446#endif
1447 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
1448 }
1449
1450 /*
1451 * Enable the interrupt gate and disable device interupts. This
1452 * should leave the device driving the interrupt line low and
1453 * guarantee an edge trigger if an interrupt can be generated.
1454 */
1455/* EXTRA DELAY? */
1456 sio_setreg(com, com_mcr, mcr_image);
1457 sio_setreg(com, com_ier, 0);
1458 DELAY(1000); /* XXX */
1459 irqmap[0] = isa_irq_pending();
1460
1461 /*
1462 * Attempt to set loopback mode so that we can send a null byte
1463 * without annoying any external device.
1464 */
1465/* EXTRA DELAY? */
1466 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK);
1467
1468 /*
1469 * Attempt to generate an output interrupt. On 8250's, setting
1470 * IER_ETXRDY generates an interrupt independent of the current
1471 * setting and independent of whether the THR is empty. On 16450's,
1472 * setting IER_ETXRDY generates an interrupt independent of the
1473 * current setting. On 16550A's, setting IER_ETXRDY only
1474 * generates an interrupt when IER_ETXRDY is not already set.
1475 */
1476 sio_setreg(com, com_ier, IER_ETXRDY);
1477#ifdef PC98
1478 if (iod.if_type == COM_IF_RSA98III)
1479 outb(iobase + rsa_ier, 0x04);
1480#endif
1481
1482 /*
1483 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
1484 * an interrupt. They'd better generate one for actually doing
1485 * output. Loopback may be broken on the same incompatibles but
1486 * it's unlikely to do more than allow the null byte out.
1487 */
1488 sio_setreg(com, com_data, 0);
1489 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
1490
1491 /*
1492 * Turn off loopback mode so that the interrupt gate works again
1493 * (MCR_IENABLE was hidden). This should leave the device driving
1494 * an interrupt line high. It doesn't matter if the interrupt
1495 * line oscillates while we are not looking at it, since interrupts
1496 * are disabled.
1497 */
1498/* EXTRA DELAY? */
1499 sio_setreg(com, com_mcr, mcr_image);
1500
1501 /*
1502 * Some pcmcia cards have the "TXRDY bug", so we check everyone
1503 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... )
1504 */
1505 if (COM_NOPROBE(flags)) {
1506 /* Reading IIR register twice */
1507 for (fn = 0; fn < 2; fn ++) {
1508 DELAY(10000);
1509 failures[6] = sio_getreg(com, com_iir);
1510 }
1511 /* Check IIR_TXRDY clear ? */
1512 result = 0;
1513 if (failures[6] & IIR_TXRDY) {
1514 /* Nop, Double check with clearing IER */
1515 sio_setreg(com, com_ier, 0);
1516 if (sio_getreg(com, com_iir) & IIR_NOPEND) {
1517 /* Ok. we're familia this gang */
1518 SET_FLAG(dev, COM_C_IIR_TXRDYBUG);
1519 } else {
1520 /* Unknown, Just omit this chip.. XXX */
1521 result = ENXIO;
1522 }
1523 } else {
1524 /* OK. this is well-known guys */
1525 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG);
1526 }
1527 sio_setreg(com, com_cfcr, CFCR_8BITS);
1528 enable_intr();
1529 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1530 return (iobase == siocniobase ? 0 : result);
1531 }
1532
1533 /*
1534 * Check that
1535 * o the CFCR, IER and MCR in UART hold the values written to them
1536 * (the values happen to be all distinct - this is good for
1537 * avoiding false positive tests from bus echoes).
1538 * o an output interrupt is generated and its vector is correct.
1539 * o the interrupt goes away when the IIR in the UART is read.
1540 */
1541/* EXTRA DELAY? */
1542 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS;
1543 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY;
1544 failures[2] = sio_getreg(com, com_mcr) - mcr_image;
1545 DELAY(10000); /* Some internal modems need this time */
1546 irqmap[1] = isa_irq_pending();
1547 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY;
1548#ifdef PC98
1549 if (iod.if_type == COM_IF_RSA98III)
1550 inb(iobase + rsa_srr);
1551#endif
1552 DELAY(1000); /* XXX */
1553 irqmap[2] = isa_irq_pending();
1554 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
1555#ifdef PC98
1556 if (iod.if_type == COM_IF_RSA98III)
1557 inb(iobase + rsa_srr);
1558#endif
1559
1560 /*
1561 * Turn off all device interrupts and check that they go off properly.
1562 * Leave MCR_IENABLE alone. For ports without a master port, it gates
1563 * the OUT2 output of the UART to
1564 * the ICU input. Closing the gate would give a floating ICU input
1565 * (unless there is another device driving it) and spurious interrupts.
1566 * (On the system that this was first tested on, the input floats high
1567 * and gives a (masked) interrupt as soon as the gate is closed.)
1568 */
1569 sio_setreg(com, com_ier, 0);
1570 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
1571 failures[7] = sio_getreg(com, com_ier);
1572#ifdef PC98
1573 if (iod.if_type == COM_IF_RSA98III)
1574 outb(iobase + rsa_ier, 0x00);
1575#endif
1576 DELAY(1000); /* XXX */
1577 irqmap[3] = isa_irq_pending();
1578 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
1579#ifdef PC98
1580 if (iod.if_type == COM_IF_RSA98III) {
1581 inb(iobase + rsa_srr);
1582 outb(iobase + rsa_frr, 0x00);
1583 }
1584#endif
1585
1586 enable_intr();
1587
1588 irqs = irqmap[1] & ~irqmap[0];
1589 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 &&
1590 ((1 << xirq) & irqs) == 0)
1591 printf(
1592 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n",
1593 device_get_unit(dev), xirq, irqs);
1594 if (bootverbose)
1595 printf("sio%d: irq maps: %#x %#x %#x %#x\n",
1596 device_get_unit(dev),
1597 irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
1598
1599 result = 0;
1600 for (fn = 0; fn < sizeof failures; ++fn)
1601 if (failures[fn]) {
1602 sio_setreg(com, com_mcr, 0);
1603 result = ENXIO;
1604 if (bootverbose) {
1605 printf("sio%d: probe failed test(s):",
1606 device_get_unit(dev));
1607 for (fn = 0; fn < sizeof failures; ++fn)
1608 if (failures[fn])
1609 printf(" %d", fn);
1610 printf("\n");
1611 }
1612 break;
1613 }
1614 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1615 return (iobase == siocniobase ? 0 : result);
1616}
1617
1618#ifdef COM_ESP
1619static int
1620espattach(com, esp_port)
1621 struct com_s *com;
1622 Port_t esp_port;
1623{
1624 u_char dips;
1625 u_char val;
1626
1627 /*
1628 * Check the ESP-specific I/O port to see if we're an ESP
1629 * card. If not, return failure immediately.
1630 */
1631 if ((inb(esp_port) & 0xf3) == 0) {
1632 printf(" port 0x%x is not an ESP board?\n", esp_port);
1633 return (0);
1634 }
1635
1636 /*
1637 * We've got something that claims to be a Hayes ESP card.
1638 * Let's hope so.
1639 */
1640
1641 /* Get the dip-switch configuration */
1642#ifdef PC98
1643 outb(esp_port + ESP98_CMD1, ESP_GETDIPS);
1644 dips = inb(esp_port + ESP98_STATUS1);
1645#else
1646 outb(esp_port + ESP_CMD1, ESP_GETDIPS);
1647 dips = inb(esp_port + ESP_STATUS1);
1648#endif
1649
1650 /*
1651 * Bits 0,1 of dips say which COM port we are.
1652 */
1653#ifdef PC98
1654 if ((rman_get_start(com->ioportres) & 0xff) ==
1655 likely_com_ports[dips & 0x03])
1656#else
1657 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03])
1658#endif
1659 printf(" : ESP");
1660 else {
1661 printf(" esp_port has com %d\n", dips & 0x03);
1662 return (0);
1663 }
1664
1665 /*
1666 * Check for ESP version 2.0 or later: bits 4,5,6 = 010.
1667 */
1668#ifdef PC98
1669 outb(esp_port + ESP98_CMD1, ESP_GETTEST);
1670 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */
1671 val = inb(esp_port + ESP98_STATUS2);
1672#else
1673 outb(esp_port + ESP_CMD1, ESP_GETTEST);
1674 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */
1675 val = inb(esp_port + ESP_STATUS2);
1676#endif
1677 if ((val & 0x70) < 0x20) {
1678 printf("-old (%o)", val & 0x70);
1679 return (0);
1680 }
1681
1682 /*
1683 * Check for ability to emulate 16550: bit 7 == 1
1684 */
1685 if ((dips & 0x80) == 0) {
1686 printf(" slave");
1687 return (0);
1688 }
1689
1690 /*
1691 * Okay, we seem to be a Hayes ESP card. Whee.
1692 */
1693 com->esp = TRUE;
1694 com->esp_port = esp_port;
1695 return (1);
1696}
1697#endif /* COM_ESP */
1698
1699static int
1700sio_isa_attach(dev)
1701 device_t dev;
1702{
1703 return (sioattach(dev, 0));
1704}
1705
1706static int
1707sioattach(dev, xrid)
1708 device_t dev;
1709 int xrid;
1710{
1711 struct com_s *com;
1712#ifdef COM_ESP
1713 Port_t *espp;
1714#endif
1715 Port_t iobase;
1716 int unit;
1717 u_int flags;
1718 int rid;
1719 struct resource *port;
1720 int ret;
1721#ifdef PC98
1722 u_char *obuf;
1723 u_long obufsize;
1724 int if_type = GET_IFTYPE(device_get_flags(dev));
1725#endif
1726
1727 rid = xrid;
1728#ifdef PC98
1729 if (IS_8251(if_type)) {
1730 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1731 0, ~0, 1, RF_ACTIVE);
1732 } else if (if_type == COM_IF_RSA98III ||
1733 isa_get_vendorid(dev)) {
1734 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0,
1735 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE);
1736 } else {
1737 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid,
1738 if_16550a_type[if_type & 0x0f].iat,
1739 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE);
1740 }
1741#else
1742 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1743 0, ~0, IO_COMSIZE, RF_ACTIVE);
1744#endif
1745 if (!port)
1746 return (ENXIO);
1747#ifdef PC98
1748 if (!IS_8251(if_type)) {
1749 if (isa_load_resourcev(port,
1750 if_16550a_type[if_type & 0x0f].iat,
1751 if_16550a_type[if_type & 0x0f].iatsz) != 0) {
1752 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1753 return ENXIO;
1754 }
1755 }
1756#endif
1757
1758 iobase = rman_get_start(port);
1759 unit = device_get_unit(dev);
1760 com = device_get_softc(dev);
1761 flags = device_get_flags(dev);
1762
1763 if (unit >= sio_numunits)
1764 sio_numunits = unit + 1;
1765
1766#ifdef PC98
1767 obufsize = 256;
1768 if (if_type == COM_IF_RSA98III)
1769 obufsize = 2048;
1770 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) {
1771 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1772 return ENXIO;
1773 }
1774 bzero(obuf, obufsize * 2);
1775#endif
1776
1777 /*
1778 * sioprobe() has initialized the device registers as follows:
1779 * o cfcr = CFCR_8BITS.
1780 * It is most important that CFCR_DLAB is off, so that the
1781 * data port is not hidden when we enable interrupts.
1782 * o ier = 0.
1783 * Interrupts are only enabled when the line is open.
1784 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
1785 * interrupt control register or the config specifies no irq.
1786 * Keeping MCR_DTR and MCR_RTS off might stop the external
1787 * device from sending before we are ready.
1788 */
1789 bzero(com, sizeof *com);
1790 com->unit = unit;
1791 com->ioportres = port;
1792 com->bst = rman_get_bustag(port);
1793 com->bsh = rman_get_bushandle(port);
1794 com->cfcr_image = CFCR_8BITS;
1795 com->dtr_wait = 3 * hz;
1796 com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
1797 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0;
1798 com->tx_fifo_size = 1;
1799#ifdef PC98
1800 com->obufsize = obufsize;
1801 com->obuf1 = obuf;
1802 com->obuf2 = obuf + obufsize;
1803#endif
1804 com->obufs[0].l_head = com->obuf1;
1805 com->obufs[1].l_head = com->obuf2;
1806
1807#ifdef PC98
1808 com->pc98_if_type = if_type;
1809
1810 if (IS_8251(if_type)) {
1811 pc98_set_ioport(com);
1812
1813 if (if_type == COM_IF_INTERNAL && pc98_check_8251fifo()) {
1814 com->pc98_8251fifo = 1;
1815 com->pc98_8251fifo_enable = 0;
1816 }
1817 } else {
1818 bus_addr_t *iat = if_16550a_type[if_type & 0x0f].iat;
1819
1820 com->data_port = iobase + iat[com_data];
1821 com->int_id_port = iobase + iat[com_iir];
1822 com->modem_ctl_port = iobase + iat[com_mcr];
1823 com->mcr_image = inb(com->modem_ctl_port);
1824 com->line_status_port = iobase + iat[com_lsr];
1825 com->modem_status_port = iobase + iat[com_msr];
1826 com->intr_ctl_port = iobase + iat[com_ier];
1827 }
1828#else /* not PC98 */
1829 com->data_port = iobase + com_data;
1830 com->int_id_port = iobase + com_iir;
1831 com->modem_ctl_port = iobase + com_mcr;
1832 com->mcr_image = inb(com->modem_ctl_port);
1833 com->line_status_port = iobase + com_lsr;
1834 com->modem_status_port = iobase + com_msr;
1835 com->intr_ctl_port = iobase + com_ier;
1836#endif
1837
1838 /*
1839 * We don't use all the flags from <sys/ttydefaults.h> since they
1840 * are only relevant for logins. It's important to have echo off
1841 * initially so that the line doesn't start blathering before the
1842 * echo flag can be turned off.
1843 */
1844 com->it_in.c_iflag = 0;
1845 com->it_in.c_oflag = 0;
1846 com->it_in.c_cflag = TTYDEF_CFLAG;
1847 com->it_in.c_lflag = 0;
1848 if (unit == comconsole) {
1849#ifdef PC98
1850 if (IS_8251(com->pc98_if_type))
1851 DELAY(100000);
1852#endif
1853 com->it_in.c_iflag = TTYDEF_IFLAG;
1854 com->it_in.c_oflag = TTYDEF_OFLAG;
1855 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL;
1856 com->it_in.c_lflag = TTYDEF_LFLAG;
1857 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL;
1858 com->lt_out.c_ispeed = com->lt_out.c_ospeed =
1859 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
1860 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate;
1861 } else
1862 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED;
1863 if (siosetwater(com, com->it_in.c_ispeed) != 0) {
1864 enable_intr();
1865 /*
1866 * Leave i/o resources allocated if this is a `cn'-level
1867 * console, so that other devices can't snarf them.
1868 */
1869 if (iobase != siocniobase)
1870 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1871 return (ENOMEM);
1872 }
1873 enable_intr();
1874 termioschars(&com->it_in);
1875 com->it_out = com->it_in;
1876
1877 /* attempt to determine UART type */
1878 printf("sio%d: type", unit);
1879
1880
1881#ifndef PC98
1882#ifdef COM_MULTIPORT
1883 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags))
1884#else
1885 if (!COM_IIR_TXRDYBUG(flags))
1886#endif
1887 {
1888 u_char scr;
1889 u_char scr1;
1890 u_char scr2;
1891
1892 scr = sio_getreg(com, com_scr);
1893 sio_setreg(com, com_scr, 0xa5);
1894 scr1 = sio_getreg(com, com_scr);
1895 sio_setreg(com, com_scr, 0x5a);
1896 scr2 = sio_getreg(com, com_scr);
1897 sio_setreg(com, com_scr, scr);
1898 if (scr1 != 0xa5 || scr2 != 0x5a) {
1899 printf(" 8250");
1900 goto determined_type;
1901 }
1902 }
1903#endif /* !PC98 */
1904#ifdef PC98
1905 if (IS_8251(com->pc98_if_type)) {
1906 if (com->pc98_8251fifo && !COM_NOFIFO(flags))
1907 com->tx_fifo_size = 16;
1908 com_int_TxRx_disable( com );
1909 com_cflag_and_speed_set( com, com->it_in.c_cflag, comdefaultrate );
1910 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
1911 com_send_break_off( com );
1912
1913 if (com->pc98_if_type == COM_IF_INTERNAL) {
1914 printf(" (internal%s%s)",
1915 com->pc98_8251fifo ? " fifo" : "",
1916 PC98SIO_baud_rate_port(com->pc98_if_type) != -1 ?
1917 " v-fast" : "");
1918 } else {
1919 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name);
1920 }
1921 } else {
1922#endif /* PC98 */
1923 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
1924 DELAY(100);
1925 com->st16650a = 0;
1926 switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
1927 case FIFO_RX_LOW:
1928 printf(" 16450");
1929 break;
1930 case FIFO_RX_MEDL:
1931 printf(" 16450?");
1932 break;
1933 case FIFO_RX_MEDH:
1934 printf(" 16550?");
1935 break;
1936 case FIFO_RX_HIGH:
1937 if (COM_NOFIFO(flags)) {
1938 printf(" 16550A fifo disabled");
1939 } else {
1940 com->hasfifo = TRUE;
1941#ifdef PC98
1942 com->tx_fifo_size = 0; /* XXX flag conflicts. */
1943 printf(" 16550A");
1944#else
1945 if (COM_ST16650A(flags)) {
1946 com->st16650a = 1;
1947 com->tx_fifo_size = 32;
1948 printf(" ST16650A");
1949 } else {
1950 com->tx_fifo_size = COM_FIFOSIZE(flags);
1951 printf(" 16550A");
1952 }
1953#endif
1954 }
1955#ifdef PC98
1956 if (com->pc98_if_type == COM_IF_RSA98III) {
1957 com->tx_fifo_size = 2048;
1958 com->rsabase = iobase;
1959 outb(com->rsabase + rsa_ier, 0x00);
1960 outb(com->rsabase + rsa_frr, 0x00);
1961 }
1962#endif
1963
1964#ifdef COM_ESP
1965#ifdef PC98
1966 if (com->pc98_if_type == COM_IF_ESP98)
1967#endif
1968 for (espp = likely_esp_ports; *espp != 0; espp++)
1969 if (espattach(com, *espp)) {
1970 com->tx_fifo_size = 1024;
1971 break;
1972 }
1973#endif
1974 if (!com->st16650a) {
1975 if (!com->tx_fifo_size)
1976 com->tx_fifo_size = 16;
1977 else
1978 printf(" lookalike with %d bytes FIFO",
1979 com->tx_fifo_size);
1980 }
1981
1982 break;
1983 }
1984
1985#ifdef PC98
1986 if (com->pc98_if_type == COM_IF_RSB3000) {
1987 /* Set RSB-2000/3000 Extended Buffer mode. */
1988 u_char lcr;
1989 lcr = sio_getreg(com, com_cfcr);
1990 sio_setreg(com, com_cfcr, lcr | CFCR_DLAB);
1991 sio_setreg(com, com_emr, EMR_EXBUFF | EMR_EFMODE);
1992 sio_setreg(com, com_cfcr, lcr);
1993 }
1994#endif
1995
1996#ifdef COM_ESP
1997 if (com->esp) {
1998 /*
1999 * Set 16550 compatibility mode.
2000 * We don't use the ESP_MODE_SCALE bit to increase the
2001 * fifo trigger levels because we can't handle large
2002 * bursts of input.
2003 * XXX flow control should be set in comparam(), not here.
2004 */
2005#ifdef PC98
2006 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE);
2007 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
2008#else
2009 outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
2010 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
2011#endif
2012
2013 /* Set RTS/CTS flow control. */
2014#ifdef PC98
2015 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE);
2016 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS);
2017 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS);
2018#else
2019 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
2020 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
2021 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
2022#endif
2023
2024 /* Set flow-control levels. */
2025#ifdef PC98
2026 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW);
2027 outb(com->esp_port + ESP98_CMD2, HIBYTE(768));
2028 outb(com->esp_port + ESP98_CMD2, LOBYTE(768));
2029 outb(com->esp_port + ESP98_CMD2, HIBYTE(512));
2030 outb(com->esp_port + ESP98_CMD2, LOBYTE(512));
2031#else
2032 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
2033 outb(com->esp_port + ESP_CMD2, HIBYTE(768));
2034 outb(com->esp_port + ESP_CMD2, LOBYTE(768));
2035 outb(com->esp_port + ESP_CMD2, HIBYTE(512));
2036 outb(com->esp_port + ESP_CMD2, LOBYTE(512));
2037#endif
2038
2039#ifdef PC98
2040 /* Set UART clock prescaler. */
2041 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK);
2042 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */
2043#endif
2044 }
2045#endif /* COM_ESP */
2046 sio_setreg(com, com_fifo, 0);
2047#ifdef PC98
2048 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name);
2049#else
2050determined_type: ;
2051#endif
2052
2053#ifdef COM_MULTIPORT
2054 if (COM_ISMULTIPORT(flags)) {
2055 device_t masterdev;
2056
2057 com->multiport = TRUE;
2058 printf(" (multiport");
2059 if (unit == COM_MPMASTER(flags))
2060 printf(" master");
2061 printf(")");
2062 masterdev = devclass_get_device(sio_devclass,
2063 COM_MPMASTER(flags));
2064 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev,
2065 SYS_RES_IRQ, 0, NULL, NULL) != 0);
2066 }
2067#endif /* COM_MULTIPORT */
2068#ifdef PC98
2069 }
2070#endif
2071 if (unit == comconsole)
2072 printf(", console");
2073 if (COM_IIR_TXRDYBUG(flags))
2074 printf(" with a bogus IIR_TXRDY register");
2075 printf("\n");
2076
2077 if (!sio_registered) {
2078 register_swi(SWI_TTY, siopoll);
2079 sio_registered = TRUE;
2080 }
2081 make_dev(&sio_cdevsw, unit,
2082 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit);
2083 make_dev(&sio_cdevsw, unit | CONTROL_INIT_STATE,
2084 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit);
2085 make_dev(&sio_cdevsw, unit | CONTROL_LOCK_STATE,
2086 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit);
2087 make_dev(&sio_cdevsw, unit | CALLOUT_MASK,
2088 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit);
2089 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_INIT_STATE,
2090 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit);
2091 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_LOCK_STATE,
2092 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit);
2093 com->flags = flags;
2094 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
2095 pps_init(&com->pps);
2096
2097 rid = 0;
2098 com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1,
2099 RF_ACTIVE);
2100 if (com->irqres) {
2101 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres,
2102 INTR_TYPE_TTY | INTR_TYPE_FAST,
2103 siointr, com, &com->cookie);
2104 if (ret) {
2105 ret = BUS_SETUP_INTR(device_get_parent(dev), dev,
2106 com->irqres, INTR_TYPE_TTY,
2107 siointr, com, &com->cookie);
2108 if (ret == 0)
2109 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode");
2110 }
2111 if (ret)
2112 device_printf(dev, "could not activate interrupt\n");
2113 }
2114
2115 return (0);
2116}
2117
2118static int
2119sioopen(dev, flag, mode, p)
2120 dev_t dev;
2121 int flag;
2122 int mode;
2123 struct proc *p;
2124{
2125 struct com_s *com;
2126 int error;
2127 int mynor;
2128 int s;
2129 struct tty *tp;
2130 int unit;
2131
2132 mynor = minor(dev);
2133 unit = MINOR_TO_UNIT(mynor);
2134 com = com_addr(unit);
2135 if (com == NULL)
2136 return (ENXIO);
2137 if (com->gone)
2138 return (ENXIO);
2139 if (mynor & CONTROL_MASK)
2140 return (0);
2141 tp = dev->si_tty = com->tp = ttymalloc(com->tp);
2142 s = spltty();
2143 /*
2144 * We jump to this label after all non-interrupted sleeps to pick
2145 * up any changes of the device state.
2146 */
2147open_top:
2148 while (com->state & CS_DTR_OFF) {
2149 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0);
2150 if (com_addr(unit) == NULL)
2151 return (ENXIO);
2152 if (error != 0 || com->gone)
2153 goto out;
2154 }
2155 if (tp->t_state & TS_ISOPEN) {
2156 /*
2157 * The device is open, so everything has been initialized.
2158 * Handle conflicts.
2159 */
2160 if (mynor & CALLOUT_MASK) {
2161 if (!com->active_out) {
2162 error = EBUSY;
2163 goto out;
2164 }
2165 } else {
2166 if (com->active_out) {
2167 if (flag & O_NONBLOCK) {
2168 error = EBUSY;
2169 goto out;
2170 }
2171 error = tsleep(&com->active_out,
2172 TTIPRI | PCATCH, "siobi", 0);
2173 if (com_addr(unit) == NULL)
2174 return (ENXIO);
2175 if (error != 0 || com->gone)
2176 goto out;
2177 goto open_top;
2178 }
2179 }
2180 if (tp->t_state & TS_XCLUDE &&
2181 suser(p)) {
2182 error = EBUSY;
2183 goto out;
2184 }
2185 } else {
2186 /*
2187 * The device isn't open, so there are no conflicts.
2188 * Initialize it. Initialization is done twice in many
2189 * cases: to preempt sleeping callin opens if we are
2190 * callout, and to complete a callin open after DCD rises.
2191 */
2192 tp->t_oproc = comstart;
2193 tp->t_param = comparam;
2194 tp->t_stop = comstop;
2195 tp->t_dev = dev;
2196 tp->t_termios = mynor & CALLOUT_MASK
2197 ? com->it_out : com->it_in;
2198#ifdef PC98
2199 if (!IS_8251(com->pc98_if_type))
2200#endif
2201 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
2202 com->poll = com->no_irq;
2203 com->poll_output = com->loses_outints;
2204 ++com->wopeners;
2205 error = comparam(tp, &tp->t_termios);
2206 --com->wopeners;
2207 if (error != 0)
2208 goto out;
2209#ifdef PC98
2210 if (IS_8251(com->pc98_if_type)) {
2211 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS);
2212 pc98_msrint_start(dev);
2213 if (com->pc98_8251fifo) {
2214 com->pc98_8251fifo_enable = 1;
2215 outb(I8251F_fcr, CTRL8251F_ENABLE |
2216 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST);
2217 }
2218 }
2219#endif
2220 /*
2221 * XXX we should goto open_top if comparam() slept.
2222 */
2223 if (com->hasfifo) {
2224 /*
2225 * (Re)enable and drain fifos.
2226 *
2227 * Certain SMC chips cause problems if the fifos
2228 * are enabled while input is ready. Turn off the
2229 * fifo if necessary to clear the input. We test
2230 * the input ready bit after enabling the fifos
2231 * since we've already enabled them in comparam()
2232 * and to handle races between enabling and fresh
2233 * input.
2234 */
2235 while (TRUE) {
2236 sio_setreg(com, com_fifo,
2237 FIFO_RCV_RST | FIFO_XMT_RST
2238 | com->fifo_image);
2239#ifdef PC98
2240 if (com->pc98_if_type == COM_IF_RSA98III)
2241 outb(com->rsabase + rsa_frr , 0x00);
2242#endif
2243 /*
2244 * XXX the delays are for superstitious
2245 * historical reasons. It must be less than
2246 * the character time at the maximum
2247 * supported speed (87 usec at 115200 bps
2248 * 8N1). Otherwise we might loop endlessly
2249 * if data is streaming in. We used to use
2250 * delays of 100. That usually worked
2251 * because DELAY(100) used to usually delay
2252 * for about 85 usec instead of 100.
2253 */
2254 DELAY(50);
2255#ifdef PC98
2256 if (com->pc98_if_type == COM_IF_RSA98III ?
2257 !(inb(com->rsabase + rsa_srr) & 0x08) :
2258 !(inb(com->line_status_port) & LSR_RXRDY))
2259 break;
2260#else
2261 if (!(inb(com->line_status_port) & LSR_RXRDY))
2262 break;
2263#endif
2264 sio_setreg(com, com_fifo, 0);
2265 DELAY(50);
2266 (void) inb(com->data_port);
2267 }
2268 }
2269
2270 disable_intr();
2271#ifdef PC98
2272 if (IS_8251(com->pc98_if_type)) {
2273 com_tiocm_bis(com, TIOCM_LE);
2274 com->pc98_prev_modem_status = pc98_get_modem_status(com);
2275 com_int_Rx_enable(com);
2276 } else {
2277#endif
2278 (void) inb(com->line_status_port);
2279 (void) inb(com->data_port);
2280 com->prev_modem_status = com->last_modem_status
2281 = inb(com->modem_status_port);
2282 if (COM_IIR_TXRDYBUG(com->flags)) {
2283 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS
2284 | IER_EMSC);
2285 } else {
2286 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY
2287 | IER_ERLS | IER_EMSC);
2288 }
2289#ifdef PC98
2290 if (com->pc98_if_type == COM_IF_RSA98III) {
2291 outb(com->rsabase + rsa_ier, 0x1d);
2292 outb(com->intr_ctl_port, IER_ERLS | IER_EMSC);
2293 }
2294#endif
2295#ifdef PC98
2296 }
2297#endif
2298 enable_intr();
2299 /*
2300 * Handle initial DCD. Callout devices get a fake initial
2301 * DCD (trapdoor DCD). If we are callout, then any sleeping
2302 * callin opens get woken up and resume sleeping on "siobi"
2303 * instead of "siodcd".
2304 */
2305 /*
2306 * XXX `mynor & CALLOUT_MASK' should be
2307 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where
2308 * TRAPDOOR_CARRIER is the default initial state for callout
2309 * devices and SOFT_CARRIER is like CLOCAL except it hides
2310 * the true carrier.
2311 */
2312#ifdef PC98
2313 if ((IS_8251(com->pc98_if_type) &&
2314 (pc98_get_modem_status(com) & TIOCM_CAR)) ||
2315 (!IS_8251(com->pc98_if_type) &&
2316 (com->prev_modem_status & MSR_DCD)) ||
2317 mynor & CALLOUT_MASK)
2318 (*linesw[tp->t_line].l_modem)(tp, 1);
2319#else
2320 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK)
2321 (*linesw[tp->t_line].l_modem)(tp, 1);
2322#endif
2323 }
2324 /*
2325 * Wait for DCD if necessary.
2326 */
2327 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK)
2328 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
2329 ++com->wopeners;
2330 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0);
2331 if (com_addr(unit) == NULL)
2332 return (ENXIO);
2333 --com->wopeners;
2334 if (error != 0 || com->gone)
2335 goto out;
2336 goto open_top;
2337 }
2338 error = (*linesw[tp->t_line].l_open)(dev, tp);
2339 disc_optim(tp, &tp->t_termios, com);
2340 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK)
2341 com->active_out = TRUE;
2342 siosettimeout();
2343out:
2344 splx(s);
2345 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0)
2346 comhardclose(com);
2347 return (error);
2348}
2349
2350static int
2351sioclose(dev, flag, mode, p)
2352 dev_t dev;
2353 int flag;
2354 int mode;
2355 struct proc *p;
2356{
2357 struct com_s *com;
2358 int mynor;
2359 int s;
2360 struct tty *tp;
2361
2362 mynor = minor(dev);
2363 if (mynor & CONTROL_MASK)
2364 return (0);
2365 com = com_addr(MINOR_TO_UNIT(mynor));
2366 if (com == NULL)
2367 return (ENODEV);
2368 tp = com->tp;
2369 s = spltty();
2370 (*linesw[tp->t_line].l_close)(tp, flag);
2371#ifdef PC98
2372 com->modem_checking = 0;
2373#endif
2374 disc_optim(tp, &tp->t_termios, com);
2375 comstop(tp, FREAD | FWRITE);
2376 comhardclose(com);
2377 ttyclose(tp);
2378 siosettimeout();
2379 splx(s);
2380 if (com->gone) {
2381 printf("sio%d: gone\n", com->unit);
2382 s = spltty();
2383 if (com->ibuf != NULL)
2384 free(com->ibuf, M_DEVBUF);
2385 bzero(tp, sizeof *tp);
2386 splx(s);
2387 }
2388 return (0);
2389}
2390
2391static void
2392comhardclose(com)
2393 struct com_s *com;
2394{
2395 int s;
2396 struct tty *tp;
2397 int unit;
2398
2399 unit = com->unit;
2400 s = spltty();
2401 com->poll = FALSE;
2402 com->poll_output = FALSE;
2403 com->do_timestamp = FALSE;
2404 com->do_dcd_timestamp = FALSE;
2405 com->pps.ppsparam.mode = 0;
2406#ifdef PC98
2407 if (IS_8251(com->pc98_if_type))
2408 com_send_break_off(com);
2409 else
2410#endif
2411 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2412 {
2413#ifdef PC98
2414 int tmp;
2415 if (IS_8251(com->pc98_if_type))
2416 com_int_TxRx_disable(com);
2417 else
2418 sio_setreg(com, com_ier, 0);
2419 if (com->pc98_if_type == COM_IF_RSA98III)
2420 outb(com->rsabase + rsa_ier, 0x00);
2421#else
2422 sio_setreg(com, com_ier, 0);
2423#endif
2424 tp = com->tp;
2425#ifdef PC98
2426 if (IS_8251(com->pc98_if_type))
2427 tmp = pc98_get_modem_status(com) & TIOCM_CAR;
2428 else
2429 tmp = com->prev_modem_status & MSR_DCD;
2430#endif
2431 if (tp->t_cflag & HUPCL
2432 /*
2433 * XXX we will miss any carrier drop between here and the
2434 * next open. Perhaps we should watch DCD even when the
2435 * port is closed; it is not sufficient to check it at
2436 * the next open because it might go up and down while
2437 * we're not watching.
2438 */
2439 || (!com->active_out
2440#ifdef PC98
2441 && !(tmp)
2442#else
2443 && !(com->prev_modem_status & MSR_DCD)
2444#endif
2445 && !(com->it_in.c_cflag & CLOCAL))
2446 || !(tp->t_state & TS_ISOPEN)) {
2447#ifdef PC98
2448 if (IS_8251(com->pc98_if_type))
2449 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
2450 else
2451#endif
2452 (void)commctl(com, TIOCM_DTR, DMBIC);
2453 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) {
2454 timeout(siodtrwakeup, com, com->dtr_wait);
2455 com->state |= CS_DTR_OFF;
2456 }
2457 }
2458#ifdef PC98
2459 else {
2460 if (IS_8251(com->pc98_if_type))
2461 com_tiocm_bic(com, TIOCM_LE);
2462 }
2463#endif
2464 }
2465#ifdef PC98
2466 if (com->pc98_8251fifo) {
2467 if (com->pc98_8251fifo_enable)
2468 outb(I8251F_fcr, CTRL8251F_XMT_RST | CTRL8251F_RCV_RST);
2469 com->pc98_8251fifo_enable = 0;
2470 }
2471#endif
2472 if (com->hasfifo) {
2473 /*
2474 * Disable fifos so that they are off after controlled
2475 * reboots. Some BIOSes fail to detect 16550s when the
2476 * fifos are enabled.
2477 */
2478 sio_setreg(com, com_fifo, 0);
2479 }
2480 com->active_out = FALSE;
2481 wakeup(&com->active_out);
2482 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */
2483 splx(s);
2484}
2485
2486static int
2487sioread(dev, uio, flag)
2488 dev_t dev;
2489 struct uio *uio;
2490 int flag;
2491{
2492 int mynor;
2493 struct com_s *com;
2494
2495 mynor = minor(dev);
2496 if (mynor & CONTROL_MASK)
2497 return (ENODEV);
2498 com = com_addr(MINOR_TO_UNIT(mynor));
2499 if (com == NULL || com->gone)
2500 return (ENODEV);
2501 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag));
2502}
2503
2504static int
2505siowrite(dev, uio, flag)
2506 dev_t dev;
2507 struct uio *uio;
2508 int flag;
2509{
2510 int mynor;
2511 struct com_s *com;
2512 int unit;
2513
2514 mynor = minor(dev);
2515 if (mynor & CONTROL_MASK)
2516 return (ENODEV);
2517
2518 unit = MINOR_TO_UNIT(mynor);
2519 com = com_addr(unit);
2520 if (com == NULL || com->gone)
2521 return (ENODEV);
2522 /*
2523 * (XXX) We disallow virtual consoles if the physical console is
2524 * a serial port. This is in case there is a display attached that
2525 * is not the console. In that situation we don't need/want the X
2526 * server taking over the console.
2527 */
2528 if (constty != NULL && unit == comconsole)
2529 constty = NULL;
2530 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag));
2531}
2532
2533static void
2534siobusycheck(chan)
2535 void *chan;
2536{
2537 struct com_s *com;
2538 int s;
2539
2540 com = (struct com_s *)chan;
2541
2542 /*
2543 * Clear TS_BUSY if low-level output is complete.
2544 * spl locking is sufficient because siointr1() does not set CS_BUSY.
2545 * If siointr1() clears CS_BUSY after we look at it, then we'll get
2546 * called again. Reading the line status port outside of siointr1()
2547 * is safe because CS_BUSY is clear so there are no output interrupts
2548 * to lose.
2549 */
2550 s = spltty();
2551 if (com->state & CS_BUSY)
2552 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */
2553#ifdef PC98
2554 else if ((IS_8251(com->pc98_if_type) &&
2555 ((com->pc98_8251fifo_enable &&
2556 (inb(I8251F_lsr) & (STS8251F_TxRDY | STS8251F_TxEMP))
2557 == (STS8251F_TxRDY | STS8251F_TxEMP)) ||
2558 (!com->pc98_8251fifo_enable &&
2559 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP))
2560 == (STS8251_TxRDY | STS8251_TxEMP)))) ||
2561 ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2562 == (LSR_TSRE | LSR_TXRDY))) {
2563#else
2564 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2565 == (LSR_TSRE | LSR_TXRDY)) {
2566#endif
2567 com->tp->t_state &= ~TS_BUSY;
2568 ttwwakeup(com->tp);
2569 com->extra_state &= ~CSE_BUSYCHECK;
2570 } else
2571 timeout(siobusycheck, com, hz / 100);
2572 splx(s);
2573}
2574
2575static void
2576siodtrwakeup(chan)
2577 void *chan;
2578{
2579 struct com_s *com;
2580
2581 com = (struct com_s *)chan;
2582 com->state &= ~CS_DTR_OFF;
2583 wakeup(&com->dtr_wait);
2584}
2585
2586static void
2587sioinput(com)
2588 struct com_s *com;
2589{
2590 u_char *buf;
2591 int incc;
2592 u_char line_status;
2593 int recv_data;
2594 struct tty *tp;
2595
2596 buf = com->ibuf;
2597 tp = com->tp;
2598 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) {
2599 com_events -= (com->iptr - com->ibuf);
2600 com->iptr = com->ibuf;
2601 return;
2602 }
2603 if (tp->t_state & TS_CAN_BYPASS_L_RINT) {
2604 /*
2605 * Avoid the grotesquely inefficient lineswitch routine
2606 * (ttyinput) in "raw" mode. It usually takes about 450
2607 * instructions (that's without canonical processing or echo!).
2608 * slinput is reasonably fast (usually 40 instructions plus
2609 * call overhead).
2610 */
2611 do {
2612 enable_intr();
2613 incc = com->iptr - buf;
2614 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat
2615 && (com->state & CS_RTS_IFLOW
2616 || tp->t_iflag & IXOFF)
2617 && !(tp->t_state & TS_TBLOCK))
2618 ttyblock(tp);
2619 com->delta_error_counts[CE_TTY_BUF_OVERFLOW]
2620 += b_to_q((char *)buf, incc, &tp->t_rawq);
2621 buf += incc;
2622 tk_nin += incc;
2623 tk_rawcc += incc;
2624 tp->t_rawcc += incc;
2625 ttwakeup(tp);
2626 if (tp->t_state & TS_TTSTOP
2627 && (tp->t_iflag & IXANY
2628 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) {
2629 tp->t_state &= ~TS_TTSTOP;
2630 tp->t_lflag &= ~FLUSHO;
2631 comstart(tp);
2632 }
2633 disable_intr();
2634 } while (buf < com->iptr);
2635 } else {
2636 do {
2637 enable_intr();
2638 line_status = buf[com->ierroff];
2639 recv_data = *buf++;
2640 if (line_status
2641 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) {
2642 if (line_status & LSR_BI)
2643 recv_data |= TTY_BI;
2644 if (line_status & LSR_FE)
2645 recv_data |= TTY_FE;
2646 if (line_status & LSR_OE)
2647 recv_data |= TTY_OE;
2648 if (line_status & LSR_PE)
2649 recv_data |= TTY_PE;
2650 }
2651 (*linesw[tp->t_line].l_rint)(recv_data, tp);
2652 disable_intr();
2653 } while (buf < com->iptr);
2654 }
2655 com_events -= (com->iptr - com->ibuf);
2656 com->iptr = com->ibuf;
2657
2658 /*
2659 * There is now room for another low-level buffer full of input,
2660 * so enable RTS if it is now disabled and there is room in the
2661 * high-level buffer.
2662 */
2663#ifdef PC98
2664 if (IS_8251(com->pc98_if_type)) {
2665 if ((com->state & CS_RTS_IFLOW) &&
2666 !(com_tiocm_get(com) & TIOCM_RTS) &&
2667 !(tp->t_state & TS_TBLOCK))
2668 com_tiocm_bis(com, TIOCM_RTS);
2669 } else {
2670 if ((com->state & CS_RTS_IFLOW) &&
2671 !(com->mcr_image & MCR_RTS) &&
2672 !(tp->t_state & TS_TBLOCK))
2673 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2674 }
2675#else
2676 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) &&
2677 !(tp->t_state & TS_TBLOCK))
2678 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2679#endif
2680}
2681
2682void
2683siointr(arg)
2684 void *arg;
2685{
2686#ifndef COM_MULTIPORT
2687 COM_LOCK();
2688 siointr1((struct com_s *) arg);
2689 COM_UNLOCK();
2690#else /* COM_MULTIPORT */
2691 bool_t possibly_more_intrs;
2692 int unit;
2693 struct com_s *com;
2694#ifdef PC98
2695 u_char rsa_buf_status;
2696#endif
2697
2698 /*
2699 * Loop until there is no activity on any port. This is necessary
2700 * to get an interrupt edge more than to avoid another interrupt.
2701 * If the IRQ signal is just an OR of the IRQ signals from several
2702 * devices, then the edge from one may be lost because another is
2703 * on.
2704 */
2705 COM_LOCK();
2706 do {
2707 possibly_more_intrs = FALSE;
2708 for (unit = 0; unit < sio_numunits; ++unit) {
2709 com = com_addr(unit);
2710 /*
2711 * XXX COM_LOCK();
2712 * would it work here, or be counter-productive?
2713 */
2714#ifdef PC98
2715 if (com != NULL
2716 && !com->gone
2717 && IS_8251(com->pc98_if_type)) {
2718 siointr1(com);
2719 } else if (com != NULL
2720 && !com->gone
2721 && com->pc98_if_type == COM_IF_RSA98III) {
2722 rsa_buf_status =
2723 inb(com->rsabase + rsa_srr) & 0xc9;
2724 if ((rsa_buf_status & 0xc8)
2725 || !(rsa_buf_status & 0x01)) {
2726 siointr1(com);
2727 if (rsa_buf_status !=
2728 (inb(com->rsabase + rsa_srr) & 0xc9))
2729 possibly_more_intrs = TRUE;
2730 }
2731 } else
2732#endif
2733 if (com != NULL
2734 && !com->gone
2735 && (inb(com->int_id_port) & IIR_IMASK)
2736 != IIR_NOPEND) {
2737 siointr1(com);
2738 possibly_more_intrs = TRUE;
2739 }
2740 /* XXX COM_UNLOCK(); */
2741 }
2742 } while (possibly_more_intrs);
2743 COM_UNLOCK();
2744#endif /* COM_MULTIPORT */
2745}
2746
2747static void
2748siointr1(com)
2749 struct com_s *com;
2750{
2751 u_char line_status;
2752 u_char modem_status;
2753 u_char *ioptr;
2754 u_char recv_data;
2755 u_char int_ctl;
2756 u_char int_ctl_new;
2757 struct timecounter *tc;
2758 u_int count;
2759
2760#ifdef PC98
2761 u_char tmp = 0;
2762 u_char rsa_buf_status = 0;
2763 int rsa_tx_fifo_size = 0;
2764#endif /* PC98 */
2765
2766 int_ctl = inb(com->intr_ctl_port);
2767 int_ctl_new = int_ctl;
2768
2769 while (!com->gone) {
2770#ifdef PC98
2771status_read:;
2772 if (IS_8251(com->pc98_if_type)) {
2773 if (com->pc98_8251fifo_enable)
2774 tmp = inb(I8251F_lsr);
2775 else
2776 tmp = inb(com->sts_port);
2777more_intr:
2778 line_status = 0;
2779 if (com->pc98_8251fifo_enable) {
2780 if (tmp & STS8251F_TxRDY) line_status |= LSR_TXRDY;
2781 if (tmp & STS8251F_RxRDY) line_status |= LSR_RXRDY;
2782 if (tmp & STS8251F_TxEMP) line_status |= LSR_TSRE;
2783 if (tmp & STS8251F_PE) line_status |= LSR_PE;
2784 if (tmp & STS8251F_OE) line_status |= LSR_OE;
2785 if (tmp & STS8251F_BD_SD) line_status |= LSR_BI;
2786 } else {
2787 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY;
2788 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY;
2789 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE;
2790 if (tmp & STS8251_PE) line_status |= LSR_PE;
2791 if (tmp & STS8251_OE) line_status |= LSR_OE;
2792 if (tmp & STS8251_FE) line_status |= LSR_FE;
2793 if (tmp & STS8251_BD_SD) line_status |= LSR_BI;
2794 }
2795 } else {
2796#endif /* PC98 */
2797 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) {
2798 modem_status = inb(com->modem_status_port);
2799 if ((modem_status ^ com->last_modem_status) & MSR_DCD) {
2800 tc = timecounter;
2801 count = tc->tc_get_timecount(tc);
2802 pps_event(&com->pps, tc, count,
2803 (modem_status & MSR_DCD) ?
2804 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR);
2805 }
2806 }
2807 line_status = inb(com->line_status_port);
2808#ifdef PC98
2809 }
2810 if (com->pc98_if_type == COM_IF_RSA98III)
2811 rsa_buf_status = inb(com->rsabase + rsa_srr);
2812#endif /* PC98 */
2813
2814 /* input event? (check first to help avoid overruns) */
2815#ifndef PC98
2816 while (line_status & LSR_RCV_MASK) {
2817#else
2818 while ((line_status & LSR_RCV_MASK)
2819 || (com->pc98_if_type == COM_IF_RSA98III
2820 && (rsa_buf_status & 0x08))) {
2821#endif /* PC98 */
2822 /* break/unnattached error bits or real input? */
2823#ifdef PC98
2824 if (IS_8251(com->pc98_if_type)) {
2825 if (com->pc98_8251fifo_enable) {
2826 recv_data = inb(I8251F_data);
2827 if (tmp & (STS8251F_PE | STS8251F_OE |
2828 STS8251F_BD_SD)) {
2829 pc98_i8251_or_cmd(com, CMD8251_ER);
2830 recv_data = 0;
2831 }
2832 } else {
2833 recv_data = inb(com->data_port);
2834 if (tmp & (STS8251_PE | STS8251_OE |
2835 STS8251_FE | STS8251_BD_SD)) {
2836 pc98_i8251_or_cmd(com, CMD8251_ER);
2837 recv_data = 0;
2838 }
2839 }
2840 } else if (com->pc98_if_type == COM_IF_RSA98III) {
2841 if (!(rsa_buf_status & 0x08))
2842 recv_data = 0;
2843 else
2844 recv_data = inb(com->data_port);
2845 } else
2846#endif
2847 if (!(line_status & LSR_RXRDY))
2848 recv_data = 0;
2849 else
2850 recv_data = inb(com->data_port);
2851 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
2852 /*
2853 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
2854 * Otherwise, push the work to a higher level
2855 * (to handle PARMRK) if we're bypassing.
2856 * Otherwise, convert BI/FE and PE+INPCK to 0.
2857 *
2858 * This makes bypassing work right in the
2859 * usual "raw" case (IGNBRK set, and IGNPAR
2860 * and INPCK clear).
2861 *
2862 * Note: BI together with FE/PE means just BI.
2863 */
2864 if (line_status & LSR_BI) {
2865#if defined(DDB) && defined(BREAK_TO_DEBUGGER)
2866 if (com->unit == comconsole) {
2867 breakpoint();
2868 goto cont;
2869 }
2870#endif
2871 if (com->tp == NULL
2872 || com->tp->t_iflag & IGNBRK)
2873 goto cont;
2874 } else {
2875 if (com->tp == NULL
2876 || com->tp->t_iflag & IGNPAR)
2877 goto cont;
2878 }
2879 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT
2880 && (line_status & (LSR_BI | LSR_FE)
2881 || com->tp->t_iflag & INPCK))
2882 recv_data = 0;
2883 }
2884 ++com->bytes_in;
2885 if (com->hotchar != 0 && recv_data == com->hotchar)
2886 setsofttty();
2887 ioptr = com->iptr;
2888 if (ioptr >= com->ibufend)
2889 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW);
2890 else {
2891 if (com->do_timestamp)
2892 microtime(&com->timestamp);
2893 ++com_events;
2894 schedsofttty();
2895#if 0 /* for testing input latency vs efficiency */
2896if (com->iptr - com->ibuf == 8)
2897 setsofttty();
2898#endif
2899 ioptr[0] = recv_data;
2900 ioptr[com->ierroff] = line_status;
2901 com->iptr = ++ioptr;
2902 if (ioptr == com->ihighwater
2903 && com->state & CS_RTS_IFLOW)
2904#ifdef PC98
2905 IS_8251(com->pc98_if_type) ?
2906 com_tiocm_bic(com, TIOCM_RTS) :
2907#endif
2908 outb(com->modem_ctl_port,
2909 com->mcr_image &= ~MCR_RTS);
2910 if (line_status & LSR_OE)
2911 CE_RECORD(com, CE_OVERRUN);
2912 }
2913cont:
2914 /*
2915 * "& 0x7F" is to avoid the gcc-1.40 generating a slow
2916 * jump from the top of the loop to here
2917 */
2918#ifdef PC98
2919 if (IS_8251(com->pc98_if_type))
2920 goto status_read;
2921 else
2922#endif
2923 line_status = inb(com->line_status_port) & 0x7F;
2924#ifdef PC98
2925 if (com->pc98_if_type == COM_IF_RSA98III)
2926 rsa_buf_status = inb(com->rsabase + rsa_srr);
2927#endif /* PC98 */
2928 }
2929
2930 /* modem status change? (always check before doing output) */
2931#ifdef PC98
2932 if (!IS_8251(com->pc98_if_type)) {
2933#endif
2934 modem_status = inb(com->modem_status_port);
2935 if (modem_status != com->last_modem_status) {
2936 if (com->do_dcd_timestamp
2937 && !(com->last_modem_status & MSR_DCD)
2938 && modem_status & MSR_DCD)
2939 microtime(&com->dcd_timestamp);
2940
2941 /*
2942 * Schedule high level to handle DCD changes. Note
2943 * that we don't use the delta bits anywhere. Some
2944 * UARTs mess them up, and it's easy to remember the
2945 * previous bits and calculate the delta.
2946 */
2947 com->last_modem_status = modem_status;
2948 if (!(com->state & CS_CHECKMSR)) {
2949 com_events += LOTS_OF_EVENTS;
2950 com->state |= CS_CHECKMSR;
2951 setsofttty();
2952 }
2953
2954 /* handle CTS change immediately for crisp flow ctl */
2955 if (com->state & CS_CTS_OFLOW) {
2956 if (modem_status & MSR_CTS)
2957 com->state |= CS_ODEVREADY;
2958 else
2959 com->state &= ~CS_ODEVREADY;
2960 }
2961 }
2962#ifdef PC98
2963 }
2964#endif
2965
2966 /* output queued and everything ready? */
2967#ifndef PC98
2968 if (line_status & LSR_TXRDY
2969 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2970#else
2971 if (((com->pc98_if_type == COM_IF_RSA98III)
2972 ? (rsa_buf_status & 0x02)
2973 : (line_status & LSR_TXRDY))
2974 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2975#endif
2976#ifdef PC98
2977 Port_t tmp_data_port;
2978
2979 if (IS_8251(com->pc98_if_type) &&
2980 com->pc98_8251fifo_enable)
2981 tmp_data_port = I8251F_data;
2982 else
2983 tmp_data_port = com->data_port;
2984#endif
2985
2986 ioptr = com->obufq.l_head;
2987 if (com->tx_fifo_size > 1) {
2988 u_int ocount;
2989
2990 ocount = com->obufq.l_tail - ioptr;
2991#ifdef PC98
2992 if (com->pc98_if_type == COM_IF_RSA98III) {
2993 rsa_buf_status = inb(com->rsabase + rsa_srr);
2994 rsa_tx_fifo_size = 1024;
2995 if (!(rsa_buf_status & 0x01))
2996 rsa_tx_fifo_size = 2048;
2997 if (ocount > rsa_tx_fifo_size)
2998 ocount = rsa_tx_fifo_size;
2999 } else
3000#endif
3001 if (ocount > com->tx_fifo_size)
3002 ocount = com->tx_fifo_size;
3003 com->bytes_out += ocount;
3004 do
3005#ifdef PC98
3006 outb(tmp_data_port, *ioptr++);
3007#else
3008 outb(com->data_port, *ioptr++);
3009#endif
3010 while (--ocount != 0);
3011 } else {
3012#ifdef PC98
3013 outb(tmp_data_port, *ioptr++);
3014#else
3015 outb(com->data_port, *ioptr++);
3016#endif
3017 ++com->bytes_out;
3018 }
3019#ifdef PC98
3020 if (IS_8251(com->pc98_if_type))
3021 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG))
3022 com_int_Tx_enable(com);
3023#endif
3024 com->obufq.l_head = ioptr;
3025 if (COM_IIR_TXRDYBUG(com->flags)) {
3026 int_ctl_new = int_ctl | IER_ETXRDY;
3027 }
3028 if (ioptr >= com->obufq.l_tail) {
3029 struct lbq *qp;
3030
3031 qp = com->obufq.l_next;
3032 qp->l_queued = FALSE;
3033 qp = qp->l_next;
3034 if (qp != NULL) {
3035 com->obufq.l_head = qp->l_head;
3036 com->obufq.l_tail = qp->l_tail;
3037 com->obufq.l_next = qp;
3038 } else {
3039 /* output just completed */
3040 if (COM_IIR_TXRDYBUG(com->flags)) {
3041 int_ctl_new = int_ctl & ~IER_ETXRDY;
3042 }
3043 com->state &= ~CS_BUSY;
3044#if defined(PC98)
3045 if (IS_8251(com->pc98_if_type) &&
3046 pc98_check_i8251_interrupt(com) & IEN_TxFLAG)
3047 com_int_Tx_disable(com);
3048#endif
3049 }
3050 if (!(com->state & CS_ODONE)) {
3051 com_events += LOTS_OF_EVENTS;
3052 com->state |= CS_ODONE;
3053 setsofttty(); /* handle at high level ASAP */
3054 }
3055 }
3056 if (COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) {
3057#ifdef PC98
3058 if (com->pc98_if_type == COM_IF_RSA98III) {
3059 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY);
3060 outb(com->intr_ctl_port, int_ctl_new);
3061 outb(com->rsabase + rsa_ier, 0x1d);
3062 } else
3063#endif
3064 outb(com->intr_ctl_port, int_ctl_new);
3065 }
3066 }
3067#ifdef PC98
3068 else if (line_status & LSR_TXRDY) {
3069 if (IS_8251(com->pc98_if_type))
3070 if (pc98_check_i8251_interrupt(com) & IEN_TxFLAG)
3071 com_int_Tx_disable(com);
3072 }
3073 if (IS_8251(com->pc98_if_type)) {
3074 if (com->pc98_8251fifo_enable) {
3075 if ((tmp = inb(I8251F_lsr)) & STS8251F_RxRDY)
3076 goto more_intr;
3077 } else {
3078 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY)
3079 goto more_intr;
3080 }
3081 }
3082#endif
3083
3084 /* finished? */
3085#ifndef COM_MULTIPORT
3086#ifdef PC98
3087 if (IS_8251(com->pc98_if_type))
3088 return;
3089#endif
3090 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND)
3091#endif /* COM_MULTIPORT */
3092 return;
3093 }
3094}
3095
3096static int
3097sioioctl(dev, cmd, data, flag, p)
3098 dev_t dev;
3099 u_long cmd;
3100 caddr_t data;
3101 int flag;
3102 struct proc *p;
3103{
3104 struct com_s *com;
3105 int error;
3106 int mynor;
3107 int s;
3108 struct tty *tp;
3109#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
3110 u_long oldcmd;
3111 struct termios term;
3112#endif
3113
3114 mynor = minor(dev);
3115 com = com_addr(MINOR_TO_UNIT(mynor));
3116 if (com == NULL || com->gone)
3117 return (ENODEV);
3118 if (mynor & CONTROL_MASK) {
3119 struct termios *ct;
3120
3121 switch (mynor & CONTROL_MASK) {
3122 case CONTROL_INIT_STATE:
3123 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in;
3124 break;
3125 case CONTROL_LOCK_STATE:
3126 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in;
3127 break;
3128 default:
3129 return (ENODEV); /* /dev/nodev */
3130 }
3131 switch (cmd) {
3132 case TIOCSETA:
3133 error = suser(p);
3134 if (error != 0)
3135 return (error);
3136 *ct = *(struct termios *)data;
3137 return (0);
3138 case TIOCGETA:
3139 *(struct termios *)data = *ct;
3140 return (0);
3141 case TIOCGETD:
3142 *(int *)data = TTYDISC;
3143 return (0);
3144 case TIOCGWINSZ:
3145 bzero(data, sizeof(struct winsize));
3146 return (0);
3147 default:
3148 return (ENOTTY);
3149 }
3150 }
3151 tp = com->tp;
3152#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
3153 term = tp->t_termios;
3154 oldcmd = cmd;
3155 error = ttsetcompat(tp, &cmd, data, &term);
3156 if (error != 0)
3157 return (error);
3158 if (cmd != oldcmd)
3159 data = (caddr_t)&term;
3160#endif
3161 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) {
3162 int cc;
3163 struct termios *dt = (struct termios *)data;
3164 struct termios *lt = mynor & CALLOUT_MASK
3165 ? &com->lt_out : &com->lt_in;
3166
3167 dt->c_iflag = (tp->t_iflag & lt->c_iflag)
3168 | (dt->c_iflag & ~lt->c_iflag);
3169 dt->c_oflag = (tp->t_oflag & lt->c_oflag)
3170 | (dt->c_oflag & ~lt->c_oflag);
3171 dt->c_cflag = (tp->t_cflag & lt->c_cflag)
3172 | (dt->c_cflag & ~lt->c_cflag);
3173 dt->c_lflag = (tp->t_lflag & lt->c_lflag)
3174 | (dt->c_lflag & ~lt->c_lflag);
3175 for (cc = 0; cc < NCCS; ++cc)
3176 if (lt->c_cc[cc] != 0)
3177 dt->c_cc[cc] = tp->t_cc[cc];
3178 if (lt->c_ispeed != 0)
3179 dt->c_ispeed = tp->t_ispeed;
3180 if (lt->c_ospeed != 0)
3181 dt->c_ospeed = tp->t_ospeed;
3182 }
3183 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
3184 if (error != ENOIOCTL)
3185 return (error);
3186 s = spltty();
3187 error = ttioctl(tp, cmd, data, flag);
3188 disc_optim(tp, &tp->t_termios, com);
3189 if (error != ENOIOCTL) {
3190 splx(s);
3191 return (error);
3192 }
3193#ifdef PC98
3194 if (IS_8251(com->pc98_if_type)) {
3195 switch (cmd) {
3196 case TIOCSBRK:
3197 com_send_break_on(com);
3198 break;
3199 case TIOCCBRK:
3200 com_send_break_off(com);
3201 break;
3202 case TIOCSDTR:
3203 com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS);
3204 break;
3205 case TIOCCDTR:
3206 com_tiocm_bic(com, TIOCM_DTR);
3207 break;
3208 /*
3209 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
3210 * changes get undone on the next call to comparam().
3211 */
3212 case TIOCMSET:
3213 com_tiocm_set(com, *(int *)data);
3214 break;
3215 case TIOCMBIS:
3216 com_tiocm_bis(com, *(int *)data);
3217 break;
3218 case TIOCMBIC:
3219 com_tiocm_bic(com, *(int *)data);
3220 break;
3221 case TIOCMGET:
3222 *(int *)data = com_tiocm_get(com);
3223 break;
3224 case TIOCMSDTRWAIT:
3225 /* must be root since the wait applies to following logins */
3226 error = suser(p);
3227 if (error != 0) {
3228 splx(s);
3229 return (error);
3230 }
3231 com->dtr_wait = *(int *)data * hz / 100;
3232 break;
3233 case TIOCMGDTRWAIT:
3234 *(int *)data = com->dtr_wait * 100 / hz;
3235 break;
3236 case TIOCTIMESTAMP:
3237 com->do_timestamp = TRUE;
3238 *(struct timeval *)data = com->timestamp;
3239 break;
3240 case TIOCDCDTIMESTAMP:
3241 com->do_dcd_timestamp = TRUE;
3242 *(struct timeval *)data = com->dcd_timestamp;
3243 break;
3244 default:
3245 splx(s);
3246 error = pps_ioctl(cmd, data, &com->pps);
3247 if (error == ENODEV)
3248 error = ENOTTY;
3249 return (error);
3250 }
3251 } else {
3252#endif
3253 switch (cmd) {
3254 case TIOCSBRK:
3255 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK);
3256 break;
3257 case TIOCCBRK:
3258 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
3259 break;
3260 case TIOCSDTR:
3261 (void)commctl(com, TIOCM_DTR, DMBIS);
3262 break;
3263 case TIOCCDTR:
3264 (void)commctl(com, TIOCM_DTR, DMBIC);
3265 break;
3266 /*
3267 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
3268 * changes get undone on the next call to comparam().
3269 */
3270 case TIOCMSET:
3271 (void)commctl(com, *(int *)data, DMSET);
3272 break;
3273 case TIOCMBIS:
3274 (void)commctl(com, *(int *)data, DMBIS);
3275 break;
3276 case TIOCMBIC:
3277 (void)commctl(com, *(int *)data, DMBIC);
3278 break;
3279 case TIOCMGET:
3280 *(int *)data = commctl(com, 0, DMGET);
3281 break;
3282 case TIOCMSDTRWAIT:
3283 /* must be root since the wait applies to following logins */
3284 error = suser(p);
3285 if (error != 0) {
3286 splx(s);
3287 return (error);
3288 }
3289 com->dtr_wait = *(int *)data * hz / 100;
3290 break;
3291 case TIOCMGDTRWAIT:
3292 *(int *)data = com->dtr_wait * 100 / hz;
3293 break;
3294 case TIOCTIMESTAMP:
3295 com->do_timestamp = TRUE;
3296 *(struct timeval *)data = com->timestamp;
3297 break;
3298 case TIOCDCDTIMESTAMP:
3299 com->do_dcd_timestamp = TRUE;
3300 *(struct timeval *)data = com->dcd_timestamp;
3301 break;
3302 default:
3303 splx(s);
3304 error = pps_ioctl(cmd, data, &com->pps);
3305 if (error == ENODEV)
3306 error = ENOTTY;
3307 return (error);
3308 }
3309#ifdef PC98
3310 }
3311#endif
3312 splx(s);
3313 return (0);
3314}
3315
3316static void
3317siopoll()
3318{
3319 int unit;
3320
3321 if (com_events == 0)
3322 return;
3323repeat:
3324 for (unit = 0; unit < sio_numunits; ++unit) {
3325 struct com_s *com;
3326 int incc;
3327 struct tty *tp;
3328
3329 com = com_addr(unit);
3330 if (com == NULL)
3331 continue;
3332 tp = com->tp;
3333 if (tp == NULL || com->gone) {
3334 /*
3335 * Discard any events related to never-opened or
3336 * going-away devices.
3337 */
3338 disable_intr();
3339 incc = com->iptr - com->ibuf;
3340 com->iptr = com->ibuf;
3341 if (com->state & CS_CHECKMSR) {
3342 incc += LOTS_OF_EVENTS;
3343 com->state &= ~CS_CHECKMSR;
3344 }
3345 com_events -= incc;
3346 enable_intr();
3347 continue;
3348 }
3349 if (com->iptr != com->ibuf) {
3350 disable_intr();
3351 sioinput(com);
3352 enable_intr();
3353 }
3354 if (com->state & CS_CHECKMSR) {
3355 u_char delta_modem_status;
3356
3357#ifdef PC98
3358 if (!IS_8251(com->pc98_if_type)) {
3359#endif
3360 disable_intr();
3361 delta_modem_status = com->last_modem_status
3362 ^ com->prev_modem_status;
3363 com->prev_modem_status = com->last_modem_status;
3364 com_events -= LOTS_OF_EVENTS;
3365 com->state &= ~CS_CHECKMSR;
3366 enable_intr();
3367 if (delta_modem_status & MSR_DCD)
3368 (*linesw[tp->t_line].l_modem)
3369 (tp, com->prev_modem_status & MSR_DCD);
3370#ifdef PC98
3371 }
3372#endif
3373 }
3374 if (com->state & CS_ODONE) {
3375 disable_intr();
3376 com_events -= LOTS_OF_EVENTS;
3377 com->state &= ~CS_ODONE;
3378 enable_intr();
3379 if (!(com->state & CS_BUSY)
3380 && !(com->extra_state & CSE_BUSYCHECK)) {
3381 timeout(siobusycheck, com, hz / 100);
3382 com->extra_state |= CSE_BUSYCHECK;
3383 }
3384 (*linesw[tp->t_line].l_start)(tp);
3385 }
3386 if (com_events == 0)
3387 break;
3388 }
3389 if (com_events >= LOTS_OF_EVENTS)
3390 goto repeat;
3391}
3392
3393static int
3394comparam(tp, t)
3395 struct tty *tp;
3396 struct termios *t;
3397{
3398 u_int cfcr;
3399 int cflag;
3400 struct com_s *com;
3401 int divisor;
3402 u_char dlbh;
3403 u_char dlbl;
3404 int s;
3405 int unit;
3406#ifdef PC98
3407 u_char param = 0;
3408#endif
3409
3410#ifdef PC98
3411 unit = DEV_TO_UNIT(tp->t_dev);
3412 com = com_addr(unit);
3413
3414 cfcr = 0;
3415 if (IS_8251(com->pc98_if_type)) {
3416 divisor = pc98_ttspeedtab(com, t->c_ospeed);
3417 } else {
3418 /* do historical conversions */
3419 if (t->c_ispeed == 0)
3420 t->c_ispeed = t->c_ospeed;
3421
3422 /* check requested parameters */
3423 divisor = ttspeedtab(t->c_ospeed,
3424 if_16550a_type[com->pc98_if_type & 0x0f].speedtab);
3425 }
3426#else
3427 /* do historical conversions */
3428 if (t->c_ispeed == 0)
3429 t->c_ispeed = t->c_ospeed;
3430
3431 /* check requested parameters */
3432 divisor = ttspeedtab(t->c_ospeed, comspeedtab);
3433#endif
3434 if (divisor < 0 || (divisor > 0 && t->c_ispeed != t->c_ospeed))
3435 return (EINVAL);
3436
3437#ifndef PC98
3438 /* parameters are OK, convert them to the com struct and the device */
3439 unit = DEV_TO_UNIT(tp->t_dev);
3440 com = com_addr(unit);
3441 if (com == NULL)
3442 return (ENODEV);
3443#endif
3444 s = spltty();
3445#ifdef PC98
3446 if (IS_8251(com->pc98_if_type)) {
3447 if (divisor == 0)
3448 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
3449 else
3450 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
3451 } else
3452#endif
3453 if (divisor == 0)
3454 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */
3455 else
3456 (void)commctl(com, TIOCM_DTR, DMBIS);
3457 cflag = t->c_cflag;
3458#ifdef PC98
3459 if (!IS_8251(com->pc98_if_type)) {
3460#endif
3461 switch (cflag & CSIZE) {
3462 case CS5:
3463 cfcr = CFCR_5BITS;
3464 break;
3465 case CS6:
3466 cfcr = CFCR_6BITS;
3467 break;
3468 case CS7:
3469 cfcr = CFCR_7BITS;
3470 break;
3471 default:
3472 cfcr = CFCR_8BITS;
3473 break;
3474 }
3475 if (cflag & PARENB) {
3476 cfcr |= CFCR_PENAB;
3477 if (!(cflag & PARODD))
3478 cfcr |= CFCR_PEVEN;
3479 }
3480 if (cflag & CSTOPB)
3481 cfcr |= CFCR_STOPB;
3482
3483 if (com->hasfifo && divisor != 0) {
3484 /*
3485 * Use a fifo trigger level low enough so that the input
3486 * latency from the fifo is less than about 16 msec and
3487 * the total latency is less than about 30 msec. These
3488 * latencies are reasonable for humans. Serial comms
3489 * protocols shouldn't expect anything better since modem
3490 * latencies are larger.
3491 */
3492 com->fifo_image = t->c_ospeed <= 4800
3493 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH;
3494#ifdef COM_ESP
3495 /*
3496 * The Hayes ESP card needs the fifo DMA mode bit set
3497 * in compatibility mode. If not, it will interrupt
3498 * for each character received.
3499 */
3500 if (com->esp)
3501 com->fifo_image |= FIFO_DMA_MODE;
3502#endif
3503 sio_setreg(com, com_fifo, com->fifo_image);
3504 }
3505#ifdef PC98
3506 }
3507#endif
3508
3509 /*
3510 * This returns with interrupts disabled so that we can complete
3511 * the speed change atomically. Keeping interrupts disabled is
3512 * especially important while com_data is hidden.
3513 */
3514 (void) siosetwater(com, t->c_ispeed);
3515
3516#ifdef PC98
3517 if (IS_8251(com->pc98_if_type))
3518 com_cflag_and_speed_set(com, cflag, t->c_ospeed);
3519 else {
3520#endif
3521 if (divisor != 0) {
3522 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB);
3523 /*
3524 * Only set the divisor registers if they would change,
3525 * since on some 16550 incompatibles (UMC8669F), setting
3526 * them while input is arriving them loses sync until
3527 * data stops arriving.
3528 */
3529 dlbl = divisor & 0xFF;
3530 if (sio_getreg(com, com_dlbl) != dlbl)
3531 sio_setreg(com, com_dlbl, dlbl);
3532 dlbh = (u_int) divisor >> 8;
3533 if (sio_getreg(com, com_dlbh) != dlbh)
3534 sio_setreg(com, com_dlbh, dlbh);
3535 }
3536
3537 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr);
3538#ifdef PC98
3539 }
3540#endif
3541
3542 if (!(tp->t_state & TS_TTSTOP))
3543 com->state |= CS_TTGO;
3544
3545 if (cflag & CRTS_IFLOW) {
3546#ifndef PC98
3547 if (com->st16650a) {
3548 sio_setreg(com, com_cfcr, 0xbf);
3549 sio_setreg(com, com_fifo,
3550 sio_getreg(com, com_fifo) | 0x40);
3551 }
3552#endif
3553 com->state |= CS_RTS_IFLOW;
3554 /*
3555 * If CS_RTS_IFLOW just changed from off to on, the change
3556 * needs to be propagated to MCR_RTS. This isn't urgent,
3557 * so do it later by calling comstart() instead of repeating
3558 * a lot of code from comstart() here.
3559 */
3560 } else if (com->state & CS_RTS_IFLOW) {
3561 com->state &= ~CS_RTS_IFLOW;
3562 /*
3563 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS
3564 * on here, since comstart() won't do it later.
3565 */
3566#ifdef PC98
3567 if (IS_8251(com->pc98_if_type))
3568 com_tiocm_bis(com, TIOCM_RTS);
3569 else
3570 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3571#else
3572 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3573 if (com->st16650a) {
3574 sio_setreg(com, com_cfcr, 0xbf);
3575 sio_setreg(com, com_fifo,
3576 sio_getreg(com, com_fifo) & ~0x40);
3577 }
3578#endif
3579 }
3580
3581
3582 /*
3583 * Set up state to handle output flow control.
3584 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
3585 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
3586 */
3587 com->state |= CS_ODEVREADY;
3588 com->state &= ~CS_CTS_OFLOW;
3589#ifdef PC98
3590 if (com->pc98_if_type == COM_IF_RSA98III) {
3591 param = inb(com->rsabase + rsa_msr);
3592 outb(com->rsabase + rsa_msr, param & 0x14);
3593 }
3594#endif
3595 if (cflag & CCTS_OFLOW) {
3596 com->state |= CS_CTS_OFLOW;
3597#ifdef PC98
3598 if (IS_8251(com->pc98_if_type)) {
3599 if (!(pc98_get_modem_status(com) & TIOCM_CTS))
3600 com->state &= ~CS_ODEVREADY;
3601 } else {
3602 if (com->pc98_if_type == COM_IF_RSA98III) {
3603 /* Set automatic flow control mode */
3604 outb(com->rsabase + rsa_msr, param | 0x08);
3605 } else
3606#endif
3607 if (!(com->last_modem_status & MSR_CTS))
3608 com->state &= ~CS_ODEVREADY;
3609#ifdef PC98
3610 }
3611#else
3612 if (com->st16650a) {
3613 sio_setreg(com, com_cfcr, 0xbf);
3614 sio_setreg(com, com_fifo,
3615 sio_getreg(com, com_fifo) | 0x80);
3616 }
3617 } else {
3618 if (com->st16650a) {
3619 sio_setreg(com, com_cfcr, 0xbf);
3620 sio_setreg(com, com_fifo,
3621 sio_getreg(com, com_fifo) & ~0x80);
3622 }
3623#endif
3624 }
3625
3626#ifdef PC98
3627 if (!IS_8251(com->pc98_if_type))
3628#endif
3629 sio_setreg(com, com_cfcr, com->cfcr_image);
3630
3631 /* XXX shouldn't call functions while intrs are disabled. */
3632 disc_optim(tp, t, com);
3633 /*
3634 * Recover from fiddling with CS_TTGO. We used to call siointr1()
3635 * unconditionally, but that defeated the careful discarding of
3636 * stale input in sioopen().
3637 */
3638 if (com->state >= (CS_BUSY | CS_TTGO))
3639 siointr1(com);
3640
3641 enable_intr();
3642 splx(s);
3643 comstart(tp);
3644 if (com->ibufold != NULL) {
3645 free(com->ibufold, M_DEVBUF);
3646 com->ibufold = NULL;
3647 }
3648 return (0);
3649}
3650
3651static int
3652siosetwater(com, speed)
3653 struct com_s *com;
3654 speed_t speed;
3655{
3656 int cp4ticks;
3657 u_char *ibuf;
3658 int ibufsize;
3659 struct tty *tp;
3660
3661 /*
3662 * Make the buffer size large enough to handle a softtty interrupt
3663 * latency of about 2 ticks without loss of throughput or data
3664 * (about 3 ticks if input flow control is not used or not honoured,
3665 * but a bit less for CS5-CS7 modes).
3666 */
3667 cp4ticks = speed / 10 / hz * 4;
3668 for (ibufsize = 128; ibufsize < cp4ticks;)
3669 ibufsize <<= 1;
3670#ifdef PC98
3671 if (com->pc98_if_type == COM_IF_RSA98III)
3672 ibufsize = 2048;
3673#endif
3674 if (ibufsize == com->ibufsize) {
3675 disable_intr();
3676 return (0);
3677 }
3678
3679 /*
3680 * Allocate input buffer. The extra factor of 2 in the size is
3681 * to allow for an error byte for each input byte.
3682 */
3683 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT);
3684 if (ibuf == NULL) {
3685 disable_intr();
3686 return (ENOMEM);
3687 }
3688
3689 /* Initialize non-critical variables. */
3690 com->ibufold = com->ibuf;
3691 com->ibufsize = ibufsize;
3692 tp = com->tp;
3693 if (tp != NULL) {
3694 tp->t_ififosize = 2 * ibufsize;
3695 tp->t_ispeedwat = (speed_t)-1;
3696 tp->t_ospeedwat = (speed_t)-1;
3697 }
3698
3699 /*
3700 * Read current input buffer, if any. Continue with interrupts
3701 * disabled.
3702 */
3703 disable_intr();
3704 if (com->iptr != com->ibuf)
3705 sioinput(com);
3706
3707 /*-
3708 * Initialize critical variables, including input buffer watermarks.
3709 * The external device is asked to stop sending when the buffer
3710 * exactly reaches high water, or when the high level requests it.
3711 * The high level is notified immediately (rather than at a later
3712 * clock tick) when this watermark is reached.
3713 * The buffer size is chosen so the watermark should almost never
3714 * be reached.
3715 * The low watermark is invisibly 0 since the buffer is always
3716 * emptied all at once.
3717 */
3718 com->iptr = com->ibuf = ibuf;
3719 com->ibufend = ibuf + ibufsize;
3720 com->ierroff = ibufsize;
3721 com->ihighwater = ibuf + 3 * ibufsize / 4;
3722 return (0);
3723}
3724
3725static void
3726comstart(tp)
3727 struct tty *tp;
3728{
3729 struct com_s *com;
3730 int s;
3731 int unit;
3732
3733 unit = DEV_TO_UNIT(tp->t_dev);
3734 com = com_addr(unit);
3735 if (com == NULL)
3736 return;
3737 s = spltty();
3738 disable_intr();
3739 if (tp->t_state & TS_TTSTOP)
3740 com->state &= ~CS_TTGO;
3741 else
3742 com->state |= CS_TTGO;
3743 if (tp->t_state & TS_TBLOCK) {
3744#ifdef PC98
3745 if (IS_8251(com->pc98_if_type)) {
3746 if ((com_tiocm_get(com) & TIOCM_RTS) &&
3747 (com->state & CS_RTS_IFLOW))
3748 com_tiocm_bic(com, TIOCM_RTS);
3749 } else {
3750 if ((com->mcr_image & MCR_RTS) &&
3751 (com->state & CS_RTS_IFLOW))
3752 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
3753 }
3754#else
3755 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW)
3756 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
3757#endif
3758 } else {
3759#ifdef PC98
3760 if (IS_8251(com->pc98_if_type)) {
3761 if (!(com_tiocm_get(com) & TIOCM_RTS) &&
3762 com->iptr < com->ihighwater &&
3763 com->state & CS_RTS_IFLOW)
3764 com_tiocm_bis(com, TIOCM_RTS);
3765 } else {
3766 if (!(com->mcr_image & MCR_RTS) &&
3767 com->iptr < com->ihighwater &&
3768 com->state & CS_RTS_IFLOW)
3769 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3770 }
3771#else
3772 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
3773 && com->state & CS_RTS_IFLOW)
3774 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3775#endif
3776 }
3777 enable_intr();
3778 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
3779 ttwwakeup(tp);
3780 splx(s);
3781 return;
3782 }
3783 if (tp->t_outq.c_cc != 0) {
3784 struct lbq *qp;
3785 struct lbq *next;
3786
3787 if (!com->obufs[0].l_queued) {
3788 com->obufs[0].l_tail
3789 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
3790#ifdef PC98
3791 com->obufsize);
3792#else
3793 sizeof com->obuf1);
3794#endif
3795 com->obufs[0].l_next = NULL;
3796 com->obufs[0].l_queued = TRUE;
3797 disable_intr();
3798 if (com->state & CS_BUSY) {
3799 qp = com->obufq.l_next;
3800 while ((next = qp->l_next) != NULL)
3801 qp = next;
3802 qp->l_next = &com->obufs[0];
3803 } else {
3804 com->obufq.l_head = com->obufs[0].l_head;
3805 com->obufq.l_tail = com->obufs[0].l_tail;
3806 com->obufq.l_next = &com->obufs[0];
3807 com->state |= CS_BUSY;
3808 }
3809 enable_intr();
3810 }
3811 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
3812 com->obufs[1].l_tail
3813 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
3814#ifdef PC98
3815 com->obufsize);
3816#else
3817 sizeof com->obuf2);
3818#endif
3819 com->obufs[1].l_next = NULL;
3820 com->obufs[1].l_queued = TRUE;
3821 disable_intr();
3822 if (com->state & CS_BUSY) {
3823 qp = com->obufq.l_next;
3824 while ((next = qp->l_next) != NULL)
3825 qp = next;
3826 qp->l_next = &com->obufs[1];
3827 } else {
3828 com->obufq.l_head = com->obufs[1].l_head;
3829 com->obufq.l_tail = com->obufs[1].l_tail;
3830 com->obufq.l_next = &com->obufs[1];
3831 com->state |= CS_BUSY;
3832 }
3833 enable_intr();
3834 }
3835 tp->t_state |= TS_BUSY;
3836 }
3837 disable_intr();
3838 if (com->state >= (CS_BUSY | CS_TTGO))
3839 siointr1(com); /* fake interrupt to start output */
3840 enable_intr();
3841 ttwwakeup(tp);
3842 splx(s);
3843}
3844
3845static void
3846comstop(tp, rw)
3847 struct tty *tp;
3848 int rw;
3849{
3850 struct com_s *com;
3851#ifdef PC98
3852 int rsa98_tmp = 0;
3853#endif
3854
3855 com = com_addr(DEV_TO_UNIT(tp->t_dev));
3856 if (com == NULL || com->gone)
3857 return;
3858 disable_intr();
3859 if (rw & FWRITE) {
3860#ifdef PC98
3861 if (!IS_8251(com->pc98_if_type)) {
3862#endif
3863 if (com->hasfifo)
3864#ifdef COM_ESP
3865 /* XXX avoid h/w bug. */
3866 if (!com->esp)
3867#endif
3868 sio_setreg(com, com_fifo,
3869 FIFO_XMT_RST | com->fifo_image);
3870#ifdef PC98
3871 if (com->pc98_if_type == COM_IF_RSA98III)
3872 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3873 sio_setreg(com, com_fifo,
3874 FIFO_XMT_RST | com->fifo_image);
3875 }
3876#endif
3877 com->obufs[0].l_queued = FALSE;
3878 com->obufs[1].l_queued = FALSE;
3879 if (com->state & CS_ODONE)
3880 com_events -= LOTS_OF_EVENTS;
3881 com->state &= ~(CS_ODONE | CS_BUSY);
3882 com->tp->t_state &= ~TS_BUSY;
3883 }
3884 if (rw & FREAD) {
3885#ifdef PC98
3886 if (!IS_8251(com->pc98_if_type)) {
3887 if (com->pc98_if_type == COM_IF_RSA98III)
3888 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3889 sio_getreg(com, com_data);
3890#endif
3891 if (com->hasfifo)
3892#ifdef COM_ESP
3893 /* XXX avoid h/w bug. */
3894 if (!com->esp)
3895#endif
3896 sio_setreg(com, com_fifo,
3897 FIFO_RCV_RST | com->fifo_image);
3898#ifdef PC98
3899 }
3900#endif
3901 com_events -= (com->iptr - com->ibuf);
3902 com->iptr = com->ibuf;
3903 }
3904 enable_intr();
3905 comstart(tp);
3906}
3907
3908static int
3909commctl(com, bits, how)
3910 struct com_s *com;
3911 int bits;
3912 int how;
3913{
3914 int mcr;
3915 int msr;
3916
3917 if (how == DMGET) {
3918 bits = TIOCM_LE; /* XXX - always enabled while open */
3919 mcr = com->mcr_image;
3920 if (mcr & MCR_DTR)
3921 bits |= TIOCM_DTR;
3922 if (mcr & MCR_RTS)
3923 bits |= TIOCM_RTS;
3924 msr = com->prev_modem_status;
3925 if (msr & MSR_CTS)
3926 bits |= TIOCM_CTS;
3927 if (msr & MSR_DCD)
3928 bits |= TIOCM_CD;
3929 if (msr & MSR_DSR)
3930 bits |= TIOCM_DSR;
3931 /*
3932 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI
3933 * more volatile by reading the modem status a lot. Perhaps
3934 * we should latch both bits until the status is read here.
3935 */
3936 if (msr & (MSR_RI | MSR_TERI))
3937 bits |= TIOCM_RI;
3938 return (bits);
3939 }
3940 mcr = 0;
3941 if (bits & TIOCM_DTR)
3942 mcr |= MCR_DTR;
3943 if (bits & TIOCM_RTS)
3944 mcr |= MCR_RTS;
3945 if (com->gone)
3946 return(0);
3947 disable_intr();
3948 switch (how) {
3949 case DMSET:
3950 outb(com->modem_ctl_port,
3951 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE));
3952 break;
3953 case DMBIS:
3954 outb(com->modem_ctl_port, com->mcr_image |= mcr);
3955 break;
3956 case DMBIC:
3957 outb(com->modem_ctl_port, com->mcr_image &= ~mcr);
3958 break;
3959 }
3960 enable_intr();
3961 return (0);
3962}
3963
3964static void
3965siosettimeout()
3966{
3967 struct com_s *com;
3968 bool_t someopen;
3969 int unit;
3970
3971 /*
3972 * Set our timeout period to 1 second if no polled devices are open.
3973 * Otherwise set it to max(1/200, 1/hz).
3974 * Enable timeouts iff some device is open.
3975 */
3976 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3977 sio_timeout = hz;
3978 someopen = FALSE;
3979 for (unit = 0; unit < sio_numunits; ++unit) {
3980 com = com_addr(unit);
3981 if (com != NULL && com->tp != NULL
3982 && com->tp->t_state & TS_ISOPEN && !com->gone) {
3983 someopen = TRUE;
3984 if (com->poll || com->poll_output) {
3985 sio_timeout = hz > 200 ? hz / 200 : 1;
3986 break;
3987 }
3988 }
3989 }
3990 if (someopen) {
3991 sio_timeouts_until_log = hz / sio_timeout;
3992 sio_timeout_handle = timeout(comwakeup, (void *)NULL,
3993 sio_timeout);
3994 } else {
3995 /* Flush error messages, if any. */
3996 sio_timeouts_until_log = 1;
3997 comwakeup((void *)NULL);
3998 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3999 }
4000}
4001
4002static void
4003comwakeup(chan)
4004 void *chan;
4005{
4006 struct com_s *com;
4007 int unit;
4008
4009 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout);
4010
4011 /*
4012 * Recover from lost output interrupts.
4013 * Poll any lines that don't use interrupts.
4014 */
4015 for (unit = 0; unit < sio_numunits; ++unit) {
4016 com = com_addr(unit);
4017 if (com != NULL && !com->gone
4018 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) {
4019 disable_intr();
4020 siointr1(com);
4021 enable_intr();
4022 }
4023 }
4024
4025 /*
4026 * Check for and log errors, but not too often.
4027 */
4028 if (--sio_timeouts_until_log > 0)
4029 return;
4030 sio_timeouts_until_log = hz / sio_timeout;
4031 for (unit = 0; unit < sio_numunits; ++unit) {
4032 int errnum;
4033
4034 com = com_addr(unit);
4035 if (com == NULL)
4036 continue;
4037 if (com->gone)
4038 continue;
4039 for (errnum = 0; errnum < CE_NTYPES; ++errnum) {
4040 u_int delta;
4041 u_long total;
4042
4043 disable_intr();
4044 delta = com->delta_error_counts[errnum];
4045 com->delta_error_counts[errnum] = 0;
4046 enable_intr();
4047 if (delta == 0)
4048 continue;
4049 total = com->error_counts[errnum] += delta;
4050 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n",
4051 unit, delta, error_desc[errnum],
4052 delta == 1 ? "" : "s", total);
4053 }
4054 }
4055}
4056
4057#ifdef PC98
4058/* commint is called when modem control line changes */
4059static void
4060commint(dev_t dev)
4061{
4062 register struct tty *tp;
4063 int stat,delta;
4064 struct com_s *com;
4065 int mynor,unit;
4066
4067 mynor = minor(dev);
4068 unit = MINOR_TO_UNIT(mynor);
4069 com = com_addr(unit);
4070 tp = com->tp;
4071
4072 stat = com_tiocm_get(com);
4073 delta = com_tiocm_get_delta(com);
4074
4075 if (com->state & CS_CTS_OFLOW) {
4076 if (stat & TIOCM_CTS)
4077 com->state |= CS_ODEVREADY;
4078 else
4079 com->state &= ~CS_ODEVREADY;
4080 }
4081 if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) {
4082 if (stat & TIOCM_CAR )
4083 (void)(*linesw[tp->t_line].l_modem)(tp, 1);
4084 else if ((*linesw[tp->t_line].l_modem)(tp, 0) == 0) {
4085 /* negate DTR, RTS */
4086 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ?
4087 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE );
4088 /* disable IENABLE */
4089 com_int_TxRx_disable( com );
4090 }
4091 }
4092}
4093#endif
4094
4095static void
4096disc_optim(tp, t, com)
4097 struct tty *tp;
4098 struct termios *t;
4099 struct com_s *com;
4100{
4101 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
4102 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
4103 && (!(t->c_iflag & PARMRK)
4104 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
4105 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
4106 && linesw[tp->t_line].l_rint == ttyinput)
4107 tp->t_state |= TS_CAN_BYPASS_L_RINT;
4108 else
4109 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
4110 com->hotchar = linesw[tp->t_line].l_hotchar;
4111}
4112
4113/*
4114 * Following are all routines needed for SIO to act as console
4115 */
4116#include <sys/cons.h>
4117
4118struct siocnstate {
4119 u_char dlbl;
4120 u_char dlbh;
4121 u_char ier;
4122 u_char cfcr;
4123 u_char mcr;
4124};
4125
4126static speed_t siocngetspeed __P((Port_t, struct speedtab *));
4127static void siocnclose __P((struct siocnstate *sp, Port_t iobase));
4128static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed));
4129static void siocntxwait __P((Port_t iobase));
4130
4131static cn_probe_t siocnprobe;
4132static cn_init_t siocninit;
4133static cn_checkc_t siocncheckc;
4134static cn_getc_t siocngetc;
4135static cn_putc_t siocnputc;
4136
4137#ifdef __i386__
4138CONS_DRIVER(sio, siocnprobe, siocninit, NULL, siocngetc, siocncheckc,
4139 siocnputc, NULL);
4140#endif
4141
4142/* To get the GDB related variables */
4143#if DDB > 0
4144#include <ddb/ddb.h>
4145#endif
4146
4147static void
4148siocntxwait(iobase)
4149 Port_t iobase;
4150{
4151 int timo;
4152
4153 /*
4154 * Wait for any pending transmission to finish. Required to avoid
4155 * the UART lockup bug when the speed is changed, and for normal
4156 * transmits.
4157 */
4158 timo = 100000;
4159 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
4160 != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
4161 ;
4162}
4163
4164/*
4165 * Read the serial port specified and try to figure out what speed
4166 * it's currently running at. We're assuming the serial port has
4167 * been initialized and is basicly idle. This routine is only intended
4168 * to be run at system startup.
4169 *
4170 * If the value read from the serial port doesn't make sense, return 0.
4171 */
4172
4173static speed_t
4174siocngetspeed(iobase, table)
4175 Port_t iobase;
4176 struct speedtab *table;
4177{
4178 int code;
4179 u_char dlbh;
4180 u_char dlbl;
4181 u_char cfcr;
4182
4183 cfcr = inb(iobase + com_cfcr);
4184 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
4185
4186 dlbl = inb(iobase + com_dlbl);
4187 dlbh = inb(iobase + com_dlbh);
4188
4189 outb(iobase + com_cfcr, cfcr);
4190
4191 code = dlbh << 8 | dlbl;
4192
4193 for (; table->sp_speed != -1; table++)
4194 if (table->sp_code == code)
4195 return (table->sp_speed);
4196
4197 return (0); /* didn't match anything sane */
4198}
4199
4200static void
4201siocnopen(sp, iobase, speed)
4202 struct siocnstate *sp;
4203 Port_t iobase;
4204 int speed;
4205{
4206 int divisor;
4207 u_char dlbh;
4208 u_char dlbl;
4209
4210 /*
4211 * Save all the device control registers except the fifo register
4212 * and set our default ones (cs8 -parenb speed=comdefaultrate).
4213 * We can't save the fifo register since it is read-only.
4214 */
4215 sp->ier = inb(iobase + com_ier);
4216 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */
4217 siocntxwait(iobase);
4218 sp->cfcr = inb(iobase + com_cfcr);
4219 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
4220 sp->dlbl = inb(iobase + com_dlbl);
4221 sp->dlbh = inb(iobase + com_dlbh);
4222 /*
4223 * Only set the divisor registers if they would change, since on
4224 * some 16550 incompatibles (Startech), setting them clears the
4225 * data input register. This also reduces the effects of the
4226 * UMC8669F bug.
4227 */
4228 divisor = ttspeedtab(speed, comspeedtab);
4229 dlbl = divisor & 0xFF;
4230 if (sp->dlbl != dlbl)
4231 outb(iobase + com_dlbl, dlbl);
4232 dlbh = (u_int) divisor >> 8;
4233 if (sp->dlbh != dlbh)
4234 outb(iobase + com_dlbh, dlbh);
4235 outb(iobase + com_cfcr, CFCR_8BITS);
4236 sp->mcr = inb(iobase + com_mcr);
4237 /*
4238 * We don't want interrupts, but must be careful not to "disable"
4239 * them by clearing the MCR_IENABLE bit, since that might cause
4240 * an interrupt by floating the IRQ line.
4241 */
4242 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
4243}
4244
4245static void
4246siocnclose(sp, iobase)
4247 struct siocnstate *sp;
4248 Port_t iobase;
4249{
4250 /*
4251 * Restore the device control registers.
4252 */
4253 siocntxwait(iobase);
4254 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
4255 if (sp->dlbl != inb(iobase + com_dlbl))
4256 outb(iobase + com_dlbl, sp->dlbl);
4257 if (sp->dlbh != inb(iobase + com_dlbh))
4258 outb(iobase + com_dlbh, sp->dlbh);
4259 outb(iobase + com_cfcr, sp->cfcr);
4260 /*
4261 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
4262 */
4263 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
4264 outb(iobase + com_ier, sp->ier);
4265}
4266
4267static void
4268siocnprobe(cp)
4269 struct consdev *cp;
4270{
4271 speed_t boot_speed;
4272 u_char cfcr;
4273 int s, unit;
4274 struct siocnstate sp;
4275
4276 /*
4277 * Find our first enabled console, if any. If it is a high-level
4278 * console device, then initialize it and return successfully.
4279 * If it is a low-level console device, then initialize it and
4280 * return unsuccessfully. It must be initialized in both cases
4281 * for early use by console drivers and debuggers. Initializing
4282 * the hardware is not necessary in all cases, since the i/o
4283 * routines initialize it on the fly, but it is necessary if
4284 * input might arrive while the hardware is switched back to an
4285 * uninitialized state. We can't handle multiple console devices
4286 * yet because our low-level routines don't take a device arg.
4287 * We trust the user to set the console flags properly so that we
4288 * don't need to probe.
4289 */
4290 cp->cn_pri = CN_DEAD;
4291
4292 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */
4293 int flags;
4294 int disabled;
4295 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) {
4296 if (disabled)
4297 continue;
4298 }
4299 if (resource_int_value("sio", unit, "flags", &flags))
4300 continue;
4301 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) {
4302 int port;
4303 Port_t iobase;
4304
4305 if (resource_int_value("sio", unit, "port", &port))
4306 continue;
4307 iobase = port;
4308 s = spltty();
4309 if (boothowto & RB_SERIAL) {
4310 boot_speed = siocngetspeed(iobase, comspeedtab);
4311 if (boot_speed)
4312 comdefaultrate = boot_speed;
4313 }
4314
4315 /*
4316 * Initialize the divisor latch. We can't rely on
4317 * siocnopen() to do this the first time, since it
4318 * avoids writing to the latch if the latch appears
4319 * to have the correct value. Also, if we didn't
4320 * just read the speed from the hardware, then we
4321 * need to set the speed in hardware so that
4322 * switching it later is null.
4323 */
4324 cfcr = inb(iobase + com_cfcr);
4325 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
4326 outb(iobase + com_dlbl,
4327 COMBRD(comdefaultrate) & 0xff);
4328 outb(iobase + com_dlbh,
4329 (u_int) COMBRD(comdefaultrate) >> 8);
4330 outb(iobase + com_cfcr, cfcr);
4331
4332 siocnopen(&sp, iobase, comdefaultrate);
4333
4334 splx(s);
4335 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) {
4336 cp->cn_dev = makedev(CDEV_MAJOR, unit);
4337 cp->cn_pri = COM_FORCECONSOLE(flags)
4338 || boothowto & RB_SERIAL
4339 ? CN_REMOTE : CN_NORMAL;
4340 siocniobase = iobase;
4341 siocnunit = unit;
4342 }
4343 if (COM_DEBUGGER(flags)) {
4344 printf("sio%d: gdb debugging port\n", unit);
4345 siogdbiobase = iobase;
4346 siogdbunit = unit;
4347#if DDB > 0
4348 gdbdev = makedev(CDEV_MAJOR, unit);
4349 gdb_getc = siocngetc;
4350 gdb_putc = siocnputc;
4351#endif
4352 }
4353 }
4354 }
4355#ifdef __i386__
4356#if DDB > 0
4357 /*
4358 * XXX Ugly Compatability.
4359 * If no gdb port has been specified, set it to be the console
4360 * as some configuration files don't specify the gdb port.
4361 */
4362 if (gdbdev == NODEV && (boothowto & RB_GDB)) {
4363 printf("Warning: no GDB port specified. Defaulting to sio%d.\n",
4364 siocnunit);
4365 printf("Set flag 0x80 on desired GDB port in your\n");
4366 printf("configuration file (currently sio only).\n");
4367 siogdbiobase = siocniobase;
4368 siogdbunit = siocnunit;
4369 gdbdev = makedev(CDEV_MAJOR, siocnunit);
4370 gdb_getc = siocngetc;
4371 gdb_putc = siocnputc;
4372 }
4373#endif
4374#endif
4375}
4376
4377#ifdef __alpha__
4378
4379CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL);
4380
4381int
4382siocnattach(port, speed)
4383 int port;
4384 int speed;
4385{
4386 int s;
4387 u_char cfcr;
4388 struct siocnstate sp;
4389
4390 siocniobase = port;
4391 comdefaultrate = speed;
4392 sio_consdev.cn_pri = CN_NORMAL;
4393 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0);
4394
4395 s = spltty();
4396
4397 /*
4398 * Initialize the divisor latch. We can't rely on
4399 * siocnopen() to do this the first time, since it
4400 * avoids writing to the latch if the latch appears
4401 * to have the correct value. Also, if we didn't
4402 * just read the speed from the hardware, then we
4403 * need to set the speed in hardware so that
4404 * switching it later is null.
4405 */
4406 cfcr = inb(siocniobase + com_cfcr);
4407 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr);
4408 outb(siocniobase + com_dlbl,
4409 COMBRD(comdefaultrate) & 0xff);
4410 outb(siocniobase + com_dlbh,
4411 (u_int) COMBRD(comdefaultrate) >> 8);
4412 outb(siocniobase + com_cfcr, cfcr);
4413
4414 siocnopen(&sp, siocniobase, comdefaultrate);
4415 splx(s);
4416
4417 cn_tab = &sio_consdev;
4418 return (0);
4419}
4420
4421int
4422siogdbattach(port, speed)
4423 int port;
4424 int speed;
4425{
4426 int s;
4427 u_char cfcr;
4428 struct siocnstate sp;
4429
4430 siogdbiobase = port;
4431 gdbdefaultrate = speed;
4432
4433 s = spltty();
4434
4435 /*
4436 * Initialize the divisor latch. We can't rely on
4437 * siocnopen() to do this the first time, since it
4438 * avoids writing to the latch if the latch appears
4439 * to have the correct value. Also, if we didn't
4440 * just read the speed from the hardware, then we
4441 * need to set the speed in hardware so that
4442 * switching it later is null.
4443 */
4444 cfcr = inb(siogdbiobase + com_cfcr);
4445 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr);
4446 outb(siogdbiobase + com_dlbl,
4447 COMBRD(gdbdefaultrate) & 0xff);
4448 outb(siogdbiobase + com_dlbh,
4449 (u_int) COMBRD(gdbdefaultrate) >> 8);
4450 outb(siogdbiobase + com_cfcr, cfcr);
4451
4452 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
4453 splx(s);
4454
4455 return (0);
4456}
4457
4458#endif
4459
4460static void
4461siocninit(cp)
4462 struct consdev *cp;
4463{
4464 comconsole = DEV_TO_UNIT(cp->cn_dev);
4465}
4466
4467static int
4468siocncheckc(dev)
4469 dev_t dev;
4470{
4471 int c;
4472 Port_t iobase;
4473 int s;
4474 struct siocnstate sp;
4475
4476 if (minor(dev) == siogdbunit)
4477 iobase = siogdbiobase;
4478 else
4479 iobase = siocniobase;
4480 s = spltty();
4481 siocnopen(&sp, iobase, comdefaultrate);
4482 if (inb(iobase + com_lsr) & LSR_RXRDY)
4483 c = inb(iobase + com_data);
4484 else
4485 c = -1;
4486 siocnclose(&sp, iobase);
4487 splx(s);
4488 return (c);
4489}
4490
4491
4492int
4493siocngetc(dev)
4494 dev_t dev;
4495{
4496 int c;
4497 Port_t iobase;
4498 int s;
4499 struct siocnstate sp;
4500
4501 if (minor(dev) == siogdbunit)
4502 iobase = siogdbiobase;
4503 else
4504 iobase = siocniobase;
4505 s = spltty();
4506 siocnopen(&sp, iobase, comdefaultrate);
4507 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
4508 ;
4509 c = inb(iobase + com_data);
4510 siocnclose(&sp, iobase);
4511 splx(s);
4512 return (c);
4513}
4514
4515void
4516siocnputc(dev, c)
4517 dev_t dev;
4518 int c;
4519{
4520 int s;
4521 struct siocnstate sp;
4522 Port_t iobase;
4523
4524 if (minor(dev) == siogdbunit)
4525 iobase = siogdbiobase;
4526 else
4527 iobase = siocniobase;
4528 s = spltty();
4529 siocnopen(&sp, iobase, comdefaultrate);
4530 siocntxwait(iobase);
4531 outb(iobase + com_data, c);
4532 siocnclose(&sp, iobase);
4533 splx(s);
4534}
4535
4536#ifdef __alpha__
4537int
4538siogdbgetc()
4539{
4540 int c;
4541 Port_t iobase;
4542 int s;
4543 struct siocnstate sp;
4544
4545 iobase = siogdbiobase;
4546 s = spltty();
4547 siocnopen(&sp, iobase, gdbdefaultrate);
4548 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
4549 ;
4550 c = inb(iobase + com_data);
4551 siocnclose(&sp, iobase);
4552 splx(s);
4553 return (c);
4554}
4555
4556void
4557siogdbputc(c)
4558 int c;
4559{
4560 int s;
4561 struct siocnstate sp;
4562
4563 s = spltty();
4564 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
4565 siocntxwait(siogdbiobase);
4566 outb(siogdbiobase + com_data, c);
4567 siocnclose(&sp, siogdbiobase);
4568 splx(s);
4569}
4570#endif
4571
4572DRIVER_MODULE(sio, isa, sio_isa_driver, sio_devclass, 0, 0);
4573#if NCARD > 0
4574DRIVER_MODULE(sio, pccard, sio_pccard_driver, sio_devclass, 0, 0);
4575#endif
4576#if NPCI > 0
4577DRIVER_MODULE(sio, pci, sio_pci_driver, sio_devclass, 0, 0);
4578#endif
4579
4580#ifdef PC98
4581/*
4582 * pc98 local function
4583 */
4584
4585static void
4586com_tiocm_set(struct com_s *com, int msr)
4587{
4588 int s;
4589 int tmp = 0;
4590 int mask = CMD8251_TxEN|CMD8251_RxEN|CMD8251_DTR|CMD8251_RTS;
4591
4592 s=spltty();
4593 com->pc98_prev_modem_status = ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) )
4594 | ( com->pc98_prev_modem_status & ~(TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4595 tmp |= (CMD8251_TxEN|CMD8251_RxEN);
4596 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4597 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4598 pc98_i8251_clear_or_cmd( com, mask, tmp );
4599 splx(s);
4600}
4601
4602static void
4603com_tiocm_bis(struct com_s *com, int msr)
4604{
4605 int s;
4606 int tmp = 0;
4607
4608 s=spltty();
4609 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4610 tmp |= CMD8251_TxEN|CMD8251_RxEN;
4611 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4612 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4613
4614 pc98_i8251_or_cmd( com, tmp );
4615 splx(s);
4616}
4617
4618static void
4619com_tiocm_bic(struct com_s *com, int msr)
4620{
4621 int s;
4622 int tmp = msr;
4623
4624 s=spltty();
4625 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4626 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4627 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4628
4629 pc98_i8251_clear_cmd( com, tmp );
4630 splx(s);
4631}
4632
4633static int
4634com_tiocm_get(struct com_s *com)
4635{
4636 return( com->pc98_prev_modem_status );
4637}
4638
4639static int
4640com_tiocm_get_delta(struct com_s *com)
4641{
4642 int tmp;
4643
4644 tmp = com->pc98_modem_delta;
4645 com->pc98_modem_delta = 0;
4646 return( tmp );
4647}
4648
4649/* convert to TIOCM_?? ( ioctl.h ) */
4650static int
4651pc98_get_modem_status(struct com_s *com)
4652{
4653 register int msr;
4654
4655 msr = com->pc98_prev_modem_status
4656 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
4657 if (com->pc98_8251fifo_enable) {
4658 int stat2;
4659
4660 stat2 = inb(I8251F_msr);
4661 if ( stat2 & CICSCDF_CD ) msr |= TIOCM_CAR;
4662 if ( stat2 & CICSCDF_CI ) msr |= TIOCM_RI;
4663 if ( stat2 & CICSCDF_DR ) msr |= TIOCM_DSR;
4664 if ( stat2 & CICSCDF_CS ) msr |= TIOCM_CTS;
4665#if COM_CARRIER_DETECT_EMULATE
4666 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) {
4667 msr |= TIOCM_CAR;
4668 }
4669#endif
4670 } else {
4671 int stat, stat2;
4672
4673 stat = inb(com->sts_port);
4674 stat2 = inb(com->in_modem_port);
4675 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR;
4676 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI;
4677 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR;
4678 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS;
4679#if COM_CARRIER_DETECT_EMULATE
4680 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) {
4681 msr |= TIOCM_CAR;
4682 }
4683#endif
4684 }
4685 return(msr);
4686}
4687
4688static void
4689pc98_check_msr(void* chan)
4690{
4691 int msr, delta;
4692 int s;
4693 register struct tty *tp;
4694 struct com_s *com;
4695 int mynor;
4696 int unit;
4697 dev_t dev;
4698
4699 dev=(dev_t)chan;
4700 mynor = minor(dev);
4701 unit = MINOR_TO_UNIT(mynor);
4702 com = com_addr(unit);
4703 tp = com->tp;
4704
4705 s = spltty();
4706 msr = pc98_get_modem_status(com);
4707 /* make change flag */
4708 delta = msr ^ com->pc98_prev_modem_status;
4709 if ( delta & TIOCM_CAR ) {
4710 if ( com->modem_car_chg_timer ) {
4711 if ( -- com->modem_car_chg_timer )
4712 msr ^= TIOCM_CAR;
4713 } else {
4714 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ?
4715 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0)
4716 msr ^= TIOCM_CAR;
4717 }
4718 } else
4719 com->modem_car_chg_timer = 0;
4720 delta = ( msr ^ com->pc98_prev_modem_status ) &
4721 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
4722 com->pc98_prev_modem_status = msr;
4723 delta = ( com->pc98_modem_delta |= delta );
4724 splx(s);
4725 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) {
4726 if ( delta ) {
4727 commint(dev);
4728 }
4729 timeout(pc98_check_msr, (caddr_t)dev,
4730 PC98_CHECK_MODEM_INTERVAL);
4731 } else {
4732 com->modem_checking = 0;
4733 }
4734}
4735
4736static void
4737pc98_msrint_start(dev_t dev)
4738{
4739 struct com_s *com;
4740 int mynor;
4741 int unit;
4742 int s = spltty();
4743
4744 mynor = minor(dev);
4745 unit = MINOR_TO_UNIT(mynor);
4746 com = com_addr(unit);
4747 /* modem control line check routine envoke interval is 1/10 sec */
4748 if ( com->modem_checking == 0 ) {
4749 com->pc98_prev_modem_status = pc98_get_modem_status(com);
4750 com->pc98_modem_delta = 0;
4751 timeout(pc98_check_msr, (caddr_t)dev,
4752 PC98_CHECK_MODEM_INTERVAL);
4753 com->modem_checking = 1;
4754 }
4755 splx(s);
4756}
4757
4758static void
4759pc98_disable_i8251_interrupt(struct com_s *com, int mod)
4760{
4761 /* disable interrupt */
4762 register int tmp;
4763
4764 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4765 COM_INT_DISABLE
4766 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4767 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp );
4768 COM_INT_ENABLE
4769}
4770
4771static void
4772pc98_enable_i8251_interrupt(struct com_s *com, int mod)
4773{
4774 register int tmp;
4775
4776 COM_INT_DISABLE
4777 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4778 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp );
4779 COM_INT_ENABLE
4780}
4781
4782static int
4783pc98_check_i8251_interrupt(struct com_s *com)
4784{
4785 return ( com->intr_enable & 0x07 );
4786}
4787
4788static void
4789pc98_i8251_clear_cmd(struct com_s *com, int x)
4790{
4791 int tmp;
4792
4793 COM_INT_DISABLE
4794 tmp = com->pc98_prev_siocmd & ~(x);
4795 if (com->pc98_8251fifo_enable)
4796 outb(I8251F_fcr, 0);
4797 outb(com->cmd_port, tmp);
4798 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4799 if (com->pc98_8251fifo_enable)
4800 outb(I8251F_fcr, CTRL8251F_ENABLE);
4801 COM_INT_ENABLE
4802}
4803
4804static void
4805pc98_i8251_or_cmd(struct com_s *com, int x)
4806{
4807 int tmp;
4808
4809 COM_INT_DISABLE
4810 if (com->pc98_8251fifo_enable)
4811 outb(I8251F_fcr, 0);
4812 tmp = com->pc98_prev_siocmd | (x);
4813 outb(com->cmd_port, tmp);
4814 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4815 if (com->pc98_8251fifo_enable)
4816 outb(I8251F_fcr, CTRL8251F_ENABLE);
4817 COM_INT_ENABLE
4818}
4819
4820static void
4821pc98_i8251_set_cmd(struct com_s *com, int x)
4822{
4823 int tmp;
4824
4825 COM_INT_DISABLE
4826 if (com->pc98_8251fifo_enable)
4827 outb(I8251F_fcr, 0);
4828 tmp = (x);
4829 outb(com->cmd_port, tmp);
4830 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4831 if (com->pc98_8251fifo_enable)
4832 outb(I8251F_fcr, CTRL8251F_ENABLE);
4833 COM_INT_ENABLE
4834}
4835
4836static void
4837pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x)
4838{
4839 int tmp;
4840 COM_INT_DISABLE
4841 if (com->pc98_8251fifo_enable)
4842 outb(I8251F_fcr, 0);
4843 tmp = com->pc98_prev_siocmd & ~(clr);
4844 tmp |= (x);
4845 outb(com->cmd_port, tmp);
4846 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4847 if (com->pc98_8251fifo_enable)
4848 outb(I8251F_fcr, CTRL8251F_ENABLE);
4849 COM_INT_ENABLE
4850}
4851
4852static int
4853pc98_i8251_get_cmd(struct com_s *com)
4854{
4855 return com->pc98_prev_siocmd;
4856}
4857
4858static int
4859pc98_i8251_get_mod(struct com_s *com)
4860{
4861 return com->pc98_prev_siomod;
4862}
4863
4864static void
4865pc98_i8251_reset(struct com_s *com, int mode, int command)
4866{
4867 if (com->pc98_8251fifo_enable)
4868 outb(I8251F_fcr, 0);
4869 outb(com->cmd_port, 0); /* dummy */
4870 DELAY(2);
4871 outb(com->cmd_port, 0); /* dummy */
4872 DELAY(2);
4873 outb(com->cmd_port, 0); /* dummy */
4874 DELAY(2);
4875 outb(com->cmd_port, CMD8251_RESET); /* internal reset */
4876 DELAY(2);
4877 outb(com->cmd_port, mode ); /* mode register */
4878 com->pc98_prev_siomod = mode;
4879 DELAY(2);
4880 pc98_i8251_set_cmd( com, (command|CMD8251_ER) );
4881 DELAY(10);
4882 if (com->pc98_8251fifo_enable)
4883 outb(I8251F_fcr, CTRL8251F_ENABLE |
4884 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST);
4885}
4886
4887static void
4888pc98_check_sysclock(void)
4889{
4890 /* get system clock from port */
4891 if ( pc98_machine_type & M_8M ) {
4892 /* 8 MHz system & H98 */
4893 sysclock = 8;
4894 } else {
4895 /* 5 MHz system */
4896 sysclock = 5;
4897 }
4898}
4899
4900static void
4901com_cflag_and_speed_set( struct com_s *com, int cflag, int speed)
4902{
4903 int cfcr=0, count;
4904 int previnterrupt;
4905
4906 count = pc98_ttspeedtab( com, speed );
4907 if ( count < 0 ) return;
4908
4909 previnterrupt = pc98_check_i8251_interrupt(com);
4910 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx );
4911
4912 switch ( cflag&CSIZE ) {
4913 case CS5:
4914 cfcr = MOD8251_5BITS; break;
4915 case CS6:
4916 cfcr = MOD8251_6BITS; break;
4917 case CS7:
4918 cfcr = MOD8251_7BITS; break;
4919 case CS8:
4920 cfcr = MOD8251_8BITS; break;
4921 }
4922 if ( cflag&PARENB ) {
4923 if ( cflag&PARODD )
4924 cfcr |= MOD8251_PODD;
4925 else
4926 cfcr |= MOD8251_PEVEN;
4927 } else
4928 cfcr |= MOD8251_PDISAB;
4929
4930 if ( cflag&CSTOPB )
4931 cfcr |= MOD8251_STOP2;
4932 else
4933 cfcr |= MOD8251_STOP1;
4934
4935 if ( count & 0x10000 )
4936 cfcr |= MOD8251_CLKX1;
4937 else
4938 cfcr |= MOD8251_CLKX16;
4939
4940 if (epson_machine_id != 0x20) { /* XXX */
4941 int tmp;
4942 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP))
4943 ;
4944 }
4945 /* set baud rate from ospeed */
4946 pc98_set_baud_rate( com, count );
4947
4948 if ( cfcr != pc98_i8251_get_mod(com) )
4949 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) );
4950
4951 pc98_enable_i8251_interrupt( com, previnterrupt );
4952}
4953
4954static int
4955pc98_ttspeedtab(struct com_s *com, int speed)
4956{
4957 int if_type, effect_sp, count = -1, mod;
4958
4959 if_type = com->pc98_if_type & 0x0f;
4960
4961 switch (com->pc98_if_type) {
4962 case COM_IF_INTERNAL:
4963 if (PC98SIO_baud_rate_port(if_type) != -1) {
4964 count = ttspeedtab(speed, if_8251_type[if_type].speedtab);
4965 if (count > 0) {
4966 count |= COM1_EXT_CLOCK;
4967 break;
4968 }
4969 }
4970
4971 /* for *1CLK asynchronous! mode, TEFUTEFU */
4972 mod = (sysclock == 5) ? 2457600 : 1996800;
4973 effect_sp = ttspeedtab( speed, pc98speedtab );
4974 if ( effect_sp < 0 ) /* XXX */
4975 effect_sp = ttspeedtab( (speed - 1), pc98speedtab );
4976 if ( effect_sp <= 0 )
4977 return effect_sp;
4978 if ( effect_sp == speed )
4979 mod /= 16;
4980 if ( mod % effect_sp )
4981 return(-1);
4982 count = mod / effect_sp;
4983 if ( count > 65535 )
4984 return(-1);
4985 if ( effect_sp != speed )
4986 count |= 0x10000;
4987 break;
4988 case COM_IF_PC9861K_1:
4989 case COM_IF_PC9861K_2:
4990 count = 1;
4991 break;
4992 case COM_IF_IND_SS_1:
4993 case COM_IF_IND_SS_2:
4994 case COM_IF_PIO9032B_1:
4995 case COM_IF_PIO9032B_2:
4996 if ( speed == 0 ) return 0;
4997 count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
4998 break;
4999 case COM_IF_B98_01_1:
5000 case COM_IF_B98_01_2:
5001 if ( speed == 0 ) return 0;
5002 count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
5003#ifdef B98_01_OLD
5004 if (count == 0 || count == 1) {
5005 count += 4;
5006 count |= 0x20000; /* x1 mode for 76800 and 153600 */
5007 }
5008#endif
5009 break;
5010 }
5011
5012 return count;
5013}
5014
5015static void
5016pc98_set_baud_rate( struct com_s *com, int count )
5017{
5018 int if_type, io, s;
5019
5020 if_type = com->pc98_if_type & 0x0f;
5021 io = rman_get_start(com->ioportres) & 0xff00;
5022
5023 switch (com->pc98_if_type) {
5024 case COM_IF_INTERNAL:
5025 if (PC98SIO_baud_rate_port(if_type) != -1) {
5026 if (count & COM1_EXT_CLOCK) {
5027 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff);
5028 break;
5029 } else {
5030 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09);
5031 }
5032 }
5033
5034 if ( count < 0 ) {
5035 printf( "[ Illegal count : %d ]", count );
5036 return;
5037 } else if ( count == 0 )
5038 return;
5039 /* set i8253 */
5040 s = splclock();
5041 if (count != 3)
5042 outb( 0x77, 0xb6 );
5043 else
5044 outb( 0x77, 0xb4 );
5045 outb( 0x5f, 0);
5046 outb( 0x75, count & 0xff );
5047 outb( 0x5f, 0);
5048 outb( 0x75, (count >> 8) & 0xff );
5049 splx(s);
5050 break;
5051 case COM_IF_IND_SS_1:
5052 case COM_IF_IND_SS_2:
5053 outb(io | PC98SIO_intr_ctrl_port(if_type), 0);
5054 outb(io | PC98SIO_baud_rate_port(if_type), 0);
5055 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0);
5056 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80);
5057 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff);
5058 break;
5059 case COM_IF_PIO9032B_1:
5060 case COM_IF_PIO9032B_2:
5061 outb(io | PC98SIO_baud_rate_port(if_type), count);
5062 break;
5063 case COM_IF_B98_01_1:
5064 case COM_IF_B98_01_2:
5065 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f);
5066#ifdef B98_01_OLD
5067 /*
5068 * Some old B98_01 board should be controlled
5069 * in different way, but this hasn't been tested yet.
5070 */
5071 outb(io | PC98SIO_func_port(if_type),
5072 (count & 0x20000) ? 0xf0 : 0xf2);
5073#endif
5074 break;
5075 }
5076}
5077static int
5078pc98_check_if_type(device_t dev, struct siodev *iod)
5079{
5080 int irr, io, if_type, tmp;
5081 static short irq_tab[2][8] = {
5082 { 3, 5, 6, 9, 10, 12, 13, -1},
5083 { 3, 10, 12, 13, 5, 6, 9, -1}
5084 };
5085
5086 if_type = iod->if_type & 0x0f;
5087 iod->irq = 0;
5088 io = isa_get_port(dev) & 0xff00;
5089
5090 if (IS_8251(iod->if_type)) {
5091 if (PC98SIO_func_port(if_type) != -1) {
5092 outb(io | PC98SIO_func_port(if_type), 0xf2);
5093 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab);
5094 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1)
5095 outb(io | PC98SIO_baud_rate_port(if_type), tmp);
5096 }
5097
5098 iod->cmd = io | PC98SIO_cmd_port(if_type);
5099 iod->sts = io | PC98SIO_sts_port(if_type);
5100 iod->mod = io | PC98SIO_in_modem_port(if_type);
5101 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type);
5102
5103 if (iod->if_type == COM_IF_INTERNAL) {
5104 iod->irq = 4;
5105
5106 if (pc98_check_8251vfast()) {
5107 PC98SIO_baud_rate_port(if_type) = I8251F_div;
5108 if_8251_type[if_type].speedtab = pc98fast_speedtab;
5109 }
5110 } else {
5111 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask;
5112 if ((isa_get_port(dev) & 0xff) == IO_COM2)
5113 iod->irq = irq_tab[0][tmp];
5114 else
5115 iod->irq = irq_tab[1][tmp];
5116 }
5117 } else {
5118 irr = if_16550a_type[if_type].irr_read;
5119#ifdef COM_MULTIPORT
5120 if (!COM_ISMULTIPORT(device_get_flags(dev)) ||
5121 device_get_unit(dev) == COM_MPMASTER(device_get_flags(dev)))
5122#endif
5123 if (irr != -1) {
5124 tmp = inb(io | irr);
5125 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */
5126 iod->irq = irq_tab[1][tmp >> 3];
5127 else
5128 iod->irq = irq_tab[0][tmp & 0x07];
5129 }
5130 }
5131 if ( iod->irq == -1 ) return -1;
5132
5133 return 0;
5134}
5135static void
5136pc98_set_ioport(struct com_s *com)
5137{
5138 int if_type = com->pc98_if_type & 0x0f;
5139 Port_t io = rman_get_start(com->ioportres) & 0xff00;
5140
5141 pc98_check_sysclock();
5142 com->data_port = io | PC98SIO_data_port(if_type);
5143 com->cmd_port = io | PC98SIO_cmd_port(if_type);
5144 com->sts_port = io | PC98SIO_sts_port(if_type);
5145 com->in_modem_port = io | PC98SIO_in_modem_port(if_type);
5146 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type);
5147}
5148static int
5149pc98_check_8251vfast(void)
5150{
5151 int i;
5152
5153 outb(I8251F_div, 0x8c);
5154 DELAY(10);
5155 for (i = 0; i < 100; i++) {
5156 if ((inb(I8251F_div) & 0x80) != 0) {
5157 i = 0;
5158 break;
5159 }
5160 DELAY(1);
5161 }
5162 outb(I8251F_div, 0);
5163 DELAY(10);
5164 for (; i < 100; i++) {
5165 if ((inb(I8251F_div) & 0x80) == 0)
5166 return 1;
5167 DELAY(1);
5168 }
5169
5170 return 0;
5171}
5172static int
5173pc98_check_8251fifo(void)
5174{
5175 u_char tmp1, tmp2;
5176
5177 tmp1 = inb(I8251F_iir);
5178 DELAY(10);
5179 tmp2 = inb(I8251F_iir);
5180 if (((tmp1 ^ tmp2) & 0x40) != 0 && ((tmp1 | tmp2) & 0x20) == 0)
5181 return 1;
5182
5183 return 0;
5184}
5185#endif /* PC98 defined */
| 882{
883 int error, s;
884 speed_t newspeed;
885 struct com_s *com;
886 struct tty *tp;
887
888 newspeed = comdefaultrate;
889
890 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req);
891 if (error || !req->newptr)
892 return (error);
893
894 comdefaultrate = newspeed;
895
896 if (comconsole < 0) /* serial console not selected? */
897 return (0);
898
899 com = com_addr(comconsole);
900 if (com == NULL)
901 return (ENXIO);
902
903 /*
904 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX
905 * (note, the lock rates really are boolean -- if non-zero, disallow
906 * speed changes)
907 */
908 com->it_in.c_ispeed = com->it_in.c_ospeed =
909 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
910 com->it_out.c_ispeed = com->it_out.c_ospeed =
911 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate;
912
913 /*
914 * if we're open, change the running rate too
915 */
916 tp = com->tp;
917 if (tp && (tp->t_state & TS_ISOPEN)) {
918 tp->t_termios.c_ispeed =
919 tp->t_termios.c_ospeed = comdefaultrate;
920 s = spltty();
921 error = comparam(tp, &tp->t_termios);
922 splx(s);
923 }
924 return error;
925}
926
927SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW,
928 0, 0, sysctl_machdep_comdefaultrate, "I", "");
929
930#define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit))
931#define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit))
932
933#if NCARD > 0
934static int
935sio_pccard_probe(dev)
936 device_t dev;
937{
938 /* Do not probe IRQ - pccard doesn't turn on the interrupt line */
939 /* until bus_setup_intr */
940 SET_FLAG(dev, COM_C_NOPROBE);
941
942 return (sioprobe(dev, 0));
943}
944
945static int
946sio_pccard_attach(dev)
947 device_t dev;
948{
949 return (sioattach(dev, 0));
950}
951
952/*
953 * sio_detach - unload the driver and clear the table.
954 * XXX TODO:
955 * This is usually called when the card is ejected, but
956 * can be caused by a modunload of a controller driver.
957 * The idea is to reset the driver's view of the device
958 * and ensure that any driver entry points such as
959 * read and write do not hang.
960 */
961static int
962sio_pccard_detach(dev)
963 device_t dev;
964{
965 struct com_s *com;
966
967 com = (struct com_s *) device_get_softc(dev);
968 if (com == NULL) {
969 device_printf(dev, "NULL com in siounload\n");
970 return (0);
971 }
972 com->gone = 1;
973 if (com->irqres) {
974 bus_teardown_intr(dev, com->irqres, com->cookie);
975 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres);
976 }
977 if (com->ioportres)
978 bus_release_resource(dev, SYS_RES_IOPORT, 0, com->ioportres);
979 if (com->tp && (com->tp->t_state & TS_ISOPEN)) {
980 device_printf(dev, "still open, forcing close\n");
981 com->tp->t_gen++;
982 ttyclose(com->tp);
983 ttwakeup(com->tp);
984 ttwwakeup(com->tp);
985 } else {
986 if (com->ibuf != NULL)
987 free(com->ibuf, M_DEVBUF);
988 }
989 device_printf(dev, "unloaded\n");
990 return (0);
991}
992#endif /* NCARD > 0 */
993
994#if NPCI > 0
995struct pci_ids {
996 u_int32_t type;
997 const char *desc;
998 int rid;
999};
1000
1001static struct pci_ids pci_ids[] = {
1002 { 0x100812b9, "3COM PCI FaxModem", 0x10 },
1003 { 0x048011c1, "ActionTec 56k FAX PCI Modem", 0x14 },
1004 { 0x00000000, NULL, 0 }
1005};
1006
1007static int
1008sio_pci_attach(dev)
1009 device_t dev;
1010{
1011 u_int32_t type;
1012 struct pci_ids *id;
1013
1014 type = pci_get_devid(dev);
1015 id = pci_ids;
1016 while (id->type && id->type != type)
1017 id++;
1018 if (id->desc == NULL)
1019 return (ENXIO);
1020 sio_pci_kludge_unit(dev);
1021 return (sioattach(dev, id->rid));
1022}
1023
1024/*
1025 * Don't cut and paste this to other drivers. It is a horrible kludge
1026 * which will fail to work and also be unnecessary in future versions.
1027 */
1028static void
1029sio_pci_kludge_unit(dev)
1030 device_t dev;
1031{
1032 devclass_t dc;
1033 int err;
1034 int start;
1035 int unit;
1036
1037 unit = 0;
1038 start = 0;
1039 while (resource_int_value("sio", unit, "port", &start) == 0 &&
1040 start > 0)
1041 unit++;
1042 if (device_get_unit(dev) < unit) {
1043 dc = device_get_devclass(dev);
1044 while (devclass_get_device(dc, unit))
1045 unit++;
1046 device_printf(dev, "moving to sio%d\n", unit);
1047 err = device_set_unit(dev, unit); /* EVIL DO NOT COPY */
1048 if (err)
1049 device_printf(dev, "error moving device %d\n", err);
1050 }
1051}
1052
1053static int
1054sio_pci_probe(dev)
1055 device_t dev;
1056{
1057 u_int32_t type;
1058 struct pci_ids *id;
1059
1060 type = pci_get_devid(dev);
1061 id = pci_ids;
1062 while (id->type && id->type != type)
1063 id++;
1064 if (id->desc == NULL)
1065 return (ENXIO);
1066 device_set_desc(dev, id->desc);
1067 return (sioprobe(dev, id->rid));
1068}
1069#endif /* NPCI > 0 */
1070
1071static struct isa_pnp_id sio_ids[] = {
1072 {0x0005d041, "Standard PC COM port"}, /* PNP0500 */
1073 {0x0105d041, "16550A-compatible COM port"}, /* PNP0501 */
1074 {0x0205d041, "Multiport serial device (non-intelligent 16550)"}, /* PNP0502 */
1075 {0x1005d041, "Generic IRDA-compatible device"}, /* PNP0510 */
1076 {0x1105d041, "Generic IRDA-compatible device"}, /* PNP0511 */
1077 /* Devices that do not have a compatid */
1078 {0x7602a904, NULL}, /* AEI0276 - 56K v.90 Fax Modem (LKT) */
1079 {0x00007905, NULL}, /* AKY0000 - 56K Plug&Play Modem */
1080 {0x01405407, NULL}, /* AZT4001 - AZT3000 PnP SOUND DEVICE, MODEM */
1081 {0x56039008, NULL}, /* BDP0356 - Best Data 56x2 */
1082 {0x36339008, NULL}, /* BDP3336 - Best Data Prods. 336F */
1083 {0x0014490a, NULL}, /* BRI1400 - Boca 33.6 PnP */
1084 {0x0015490a, NULL}, /* BRI1500 - Internal Fax Data */
1085 {0x0034490a, NULL}, /* BRI3400 - Internal ACF Modem */
1086 {0x00b4490a, NULL}, /* BRIB400 - Boca 56k PnP */
1087 {0x0030320d, NULL}, /* CIR3000 - Cirrus Logic V43 */
1088 {0x0100440e, NULL}, /* CRD0001 - Cardinal MVP288IV ? */
1089 {0x1200c31e, NULL}, /* GVC0012 - VF1128HV-R9 (win modem?) */
1090 {0x0303c31e, NULL}, /* GVC0303 - MaxTech 33.6 PnP D/F/V */
1091 {0x0505c31e, NULL}, /* GVC0505 - GVC 56k Faxmodem */
1092 {0x0050c31e, NULL}, /* GVC5000 - some GVC modem */
1093 {0x3800f91e, NULL}, /* GWY0038 - Telepath with v.90 */
1094 {0x9062f91e, NULL}, /* GWY6290 - Telepath with x2 Technology */
1095 {0x0000f435, NULL}, /* MOT0000 - Motorola ModemSURFR 33.6 Intern */
1096 {0x5015f435, NULL}, /* MOT1550 - Motorola ModemSURFR 56K Modem */
1097 {0xf015f435, NULL}, /* MOT15F0 - Motorola VoiceSURFR 56K Modem */
1098 {0x6045f435, NULL}, /* MOT4560 - Motorola ? */
1099 {0x61e7a338, NULL}, /* NECE761 - 33.6Modem */
1100 {0x39804f3f, NULL}, /* OZO8039 - Zoom 56k flex */
1101 {0x3024a341, NULL}, /* PMC2430 - Pace 56 Voice Internal Modem */
1102 {0x1000eb49, NULL}, /* ROK0010 - Rockwell ? */
1103 {0x5002734a, NULL}, /* RSS0250 - 5614Jx3(G) Internal Modem */
1104 {0xc100ad4d, NULL}, /* SMM00C1 - Leopard 56k PnP */
1105 {0x9012b04e, NULL}, /* SUP1290 - Supra ? */
1106 {0x1013b04e, NULL}, /* SUP1310 - SupraExpress 336i PnP */
1107 {0x8013b04e, NULL}, /* SUP1380 - SupraExpress 288i PnP Voice */
1108 {0x8113b04e, NULL}, /* SUP1381 - SupraExpress 336i PnP Voice */
1109 {0x5016b04e, NULL}, /* SUP1650 - Supra 336i Sp Intl */
1110 {0x7420b04e, NULL}, /* SUP2070 - Supra ? */
1111 {0x8020b04e, NULL}, /* SUP2080 - Supra ? */
1112 {0x8420b04e, NULL}, /* SUP2084 - SupraExpress 56i PnP */
1113 {0x7121b04e, NULL}, /* SUP2171 - SupraExpress 56i Sp? */
1114 {0x8024b04e, NULL}, /* SUP2480 - Supra ? */
1115 {0x01007256, NULL}, /* USR0001 - U.S. Robotics Inc., Sportster W */
1116 {0x02007256, NULL}, /* USR0002 - U.S. Robotics Inc. Sportster 33. */
1117 {0x04007256, NULL}, /* USR0004 - USR Sportster 14.4k */
1118 {0x06007256, NULL}, /* USR0006 - USR Sportster 33.6k */
1119 {0x11007256, NULL}, /* USR0011 - USR ? */
1120 {0x01017256, NULL}, /* USR0101 - USR ? */
1121 {0x30207256, NULL}, /* USR2030 - U.S.Robotics Inc. Sportster 560 */
1122 {0x50207256, NULL}, /* USR2050 - U.S.Robotics Inc. Sportster 33. */
1123 {0x70207256, NULL}, /* USR2070 - U.S.Robotics Inc. Sportster 560 */
1124 {0x30307256, NULL}, /* USR3030 - U.S. Robotics 56K FAX INT */
1125 {0x31307256, NULL}, /* USR3031 - U.S. Robotics 56K FAX INT */
1126 {0x50307256, NULL}, /* USR3050 - U.S. Robotics 56K FAX INT */
1127 {0x70307256, NULL}, /* USR3070 - U.S. Robotics 56K Voice INT */
1128 {0x90307256, NULL}, /* USR3090 - USR ? */
1129 {0x90917256, NULL}, /* USR9190 - USR 56k Voice INT */
1130 {0x0300695c, NULL}, /* WCI0003 - Fax/Voice/Modem/Speakphone/Asvd */
1131 {0x61f7896a, NULL}, /* ZTIF761 - Zoom ComStar 33.6 */
1132#ifdef PC98
1133 {0x0100e4a5, "RSA-98III"},
1134#endif
1135 {0}
1136};
1137
1138
1139
1140static int
1141sio_isa_probe(dev)
1142 device_t dev;
1143{
1144#ifdef PC98
1145 int logical_id;
1146#endif
1147 /* Check isapnp ids */
1148 if (ISA_PNP_PROBE(device_get_parent(dev), dev, sio_ids) == ENXIO)
1149 return (ENXIO);
1150#ifdef PC98
1151 logical_id = isa_get_logicalid(dev);
1152 if (logical_id == 0x0100e4a5) /* RSA-98III */
1153 device_set_flags(dev, SET_IFTYPE(COM_IF_RSA98III));
1154#endif
1155 return (sioprobe(dev, 0));
1156}
1157
1158static int
1159sioprobe(dev, xrid)
1160 device_t dev;
1161 int xrid;
1162{
1163#if 0
1164 static bool_t already_init;
1165 device_t xdev;
1166#endif
1167 struct com_s *com;
1168 bool_t failures[10];
1169 int fn;
1170 device_t idev;
1171 Port_t iobase;
1172 intrmask_t irqmap[4];
1173 intrmask_t irqs;
1174 u_char mcr_image;
1175 int result;
1176 u_long xirq;
1177 u_int flags = device_get_flags(dev);
1178 int rid;
1179 struct resource *port;
1180#ifdef PC98
1181 int tmp;
1182 struct siodev iod;
1183#endif
1184
1185#ifdef PC98
1186 iod.if_type = GET_IFTYPE(flags);
1187 if ((iod.if_type < 0 || iod.if_type > COM_IF_END1) &&
1188 (iod.if_type < 0x10 || iod.if_type > COM_IF_END2))
1189 return ENXIO;
1190#endif
1191
1192 rid = xrid;
1193#ifdef PC98
1194 if (IS_8251(iod.if_type)) {
1195 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1196 0, ~0, 1, RF_ACTIVE);
1197 } else if (iod.if_type == COM_IF_RSA98III ||
1198 isa_get_vendorid(dev)) {
1199 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0,
1200 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE);
1201 } else {
1202 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid,
1203 if_16550a_type[iod.if_type & 0x0f].iat,
1204 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE);
1205 }
1206#else
1207 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1208 0, ~0, IO_COMSIZE, RF_ACTIVE);
1209#endif
1210 if (!port)
1211 return (ENXIO);
1212#ifdef PC98
1213 if (!IS_8251(iod.if_type)) {
1214 if (isa_load_resourcev(port,
1215 if_16550a_type[iod.if_type & 0x0f].iat,
1216 if_16550a_type[iod.if_type & 0x0f].iatsz) != 0) {
1217 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1218 return ENXIO;
1219 }
1220 }
1221#endif
1222
1223 com = device_get_softc(dev);
1224 com->bst = rman_get_bustag(port);
1225 com->bsh = rman_get_bushandle(port);
1226
1227#if 0
1228 /*
1229 * XXX this is broken - when we are first called, there are no
1230 * previously configured IO ports. We could hard code
1231 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse.
1232 * This code has been doing nothing since the conversion since
1233 * "count" is zero the first time around.
1234 */
1235 if (!already_init) {
1236 /*
1237 * Turn off MCR_IENABLE for all likely serial ports. An unused
1238 * port with its MCR_IENABLE gate open will inhibit interrupts
1239 * from any used port that shares the interrupt vector.
1240 * XXX the gate enable is elsewhere for some multiports.
1241 */
1242 device_t *devs;
1243 int count, i, xioport;
1244#ifdef PC98
1245 int xiftype;
1246#endif
1247
1248 devclass_get_devices(sio_devclass, &devs, &count);
1249#ifdef PC98
1250 for (i = 0; i < count; i++) {
1251 xdev = devs[i];
1252 xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0);
1253 xiftype = GET_IFTYPE(device_get_flags(xdev));
1254 if (device_is_enabled(xdev) && xioport > 0) {
1255 if (IS_8251(xiftype))
1256 outb((xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2);
1257 else
1258 outb(xioport + if_16550a_type[xiftype & 0x0f].iat[com_mcr], 0);
1259 }
1260 }
1261#else
1262 for (i = 0; i < count; i++) {
1263 xdev = devs[i];
1264 if (device_is_enabled(xdev) &&
1265 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport,
1266 NULL) == 0)
1267 outb(xioport + com_mcr, 0);
1268 }
1269#endif
1270 free(devs, M_TEMP);
1271 already_init = TRUE;
1272 }
1273#endif
1274
1275 if (COM_LLCONSOLE(flags)) {
1276 printf("sio%d: reserved for low-level i/o\n",
1277 device_get_unit(dev));
1278 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1279 return (ENXIO);
1280 }
1281
1282#ifdef PC98
1283 DELAY(10);
1284
1285 /*
1286 * If the port is i8251 UART (internal, B98_01)
1287 */
1288 if (pc98_check_if_type(dev, &iod) == -1) {
1289 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1290 return (ENXIO);
1291 }
1292 if (iod.irq > 0)
1293 bus_set_resource(dev, SYS_RES_IRQ, 0, iod.irq, 1);
1294 if (IS_8251(iod.if_type)) {
1295 outb(iod.cmd, 0);
1296 DELAY(10);
1297 outb(iod.cmd, 0);
1298 DELAY(10);
1299 outb(iod.cmd, 0);
1300 DELAY(10);
1301 outb(iod.cmd, CMD8251_RESET);
1302 DELAY(1000); /* for a while...*/
1303 outb(iod.cmd, 0xf2); /* MODE (dummy) */
1304 DELAY(10);
1305 outb(iod.cmd, 0x01); /* CMD (dummy) */
1306 DELAY(1000); /* for a while...*/
1307 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) {
1308 result = (ENXIO);
1309 }
1310 if (if_8251_type[iod.if_type & 0x0f].check_irq) {
1311 COM_INT_DISABLE
1312 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx));
1313 outb( iod.ctrl, tmp|IEN_TxEMP );
1314 DELAY(10);
1315 result = isa_irq_pending() ? 0 : ENXIO;
1316 outb( iod.ctrl, tmp );
1317 COM_INT_ENABLE
1318 } else {
1319 /*
1320 * B98_01 doesn't activate TxEMP interrupt line
1321 * when being reset, so we can't check irq pending.
1322 */
1323 result = 0;
1324 }
1325 if (epson_machine_id==0x20) { /* XXX */
1326 result = 0;
1327 }
1328 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1329 return result;
1330 }
1331#endif /* PC98 */
1332 /*
1333 * If the device is on a multiport card and has an AST/4
1334 * compatible interrupt control register, initialize this
1335 * register and prepare to leave MCR_IENABLE clear in the mcr.
1336 * Otherwise, prepare to set MCR_IENABLE in the mcr.
1337 * Point idev to the device struct giving the correct id_irq.
1338 * This is the struct for the master device if there is one.
1339 */
1340 idev = dev;
1341 mcr_image = MCR_IENABLE;
1342#ifdef COM_MULTIPORT
1343 if (COM_ISMULTIPORT(flags)) {
1344#ifndef PC98
1345 Port_t xiobase;
1346 u_long io;
1347#endif
1348
1349 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
1350 if (idev == NULL) {
1351 printf("sio%d: master device %d not configured\n",
1352 device_get_unit(dev), COM_MPMASTER(flags));
1353 idev = dev;
1354 }
1355#ifndef PC98
1356 if (!COM_NOTAST4(flags)) {
1357 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io,
1358 NULL) == 0) {
1359 xiobase = io;
1360 if (bus_get_resource(idev, SYS_RES_IRQ, 0,
1361 NULL, NULL) == 0)
1362 outb(xiobase + com_scr, 0x80);
1363 else
1364 outb(xiobase + com_scr, 0);
1365 }
1366 mcr_image = 0;
1367 }
1368#endif
1369 }
1370#endif /* COM_MULTIPORT */
1371 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0)
1372 mcr_image = 0;
1373
1374 bzero(failures, sizeof failures);
1375 iobase = rman_get_start(port);
1376
1377#ifdef PC98
1378 if (iod.if_type == COM_IF_RSA98III) {
1379 mcr_image = 0;
1380
1381 outb(iobase + rsa_msr, 0x04);
1382 outb(iobase + rsa_frr, 0x00);
1383 if ((inb(iobase + rsa_srr) & 0x36) != 0x36) {
1384 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1385 return (ENXIO);
1386 }
1387 outb(iobase + rsa_ier, 0x00);
1388 outb(iobase + rsa_frr, 0x00);
1389 outb(iobase + rsa_tivsr, 0x00);
1390 outb(iobase + rsa_tcr, 0x00);
1391 }
1392
1393 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write;
1394 if (tmp != -1) {
1395 /* MC16550II */
1396 int irqout;
1397 switch (isa_get_irq(idev)) {
1398 case 3: irqout = 4; break;
1399 case 5: irqout = 5; break;
1400 case 6: irqout = 6; break;
1401 case 12: irqout = 7; break;
1402 default:
1403 printf("sio%d: irq configuration error\n",
1404 device_get_unit(dev));
1405 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1406 return (ENXIO);
1407 }
1408 outb((iobase & 0x00ff) | tmp, irqout);
1409 }
1410#endif
1411
1412 /*
1413 * We don't want to get actual interrupts, just masked ones.
1414 * Interrupts from this line should already be masked in the ICU,
1415 * but mask them in the processor as well in case there are some
1416 * (misconfigured) shared interrupts.
1417 */
1418 disable_intr();
1419/* EXTRA DELAY? */
1420
1421 /*
1422 * Initialize the speed and the word size and wait long enough to
1423 * drain the maximum of 16 bytes of junk in device output queues.
1424 * The speed is undefined after a master reset and must be set
1425 * before relying on anything related to output. There may be
1426 * junk after a (very fast) soft reboot and (apparently) after
1427 * master reset.
1428 * XXX what about the UART bug avoided by waiting in comparam()?
1429 * We don't want to to wait long enough to drain at 2 bps.
1430 */
1431 if (iobase == siocniobase)
1432 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
1433 else {
1434#ifdef PC98
1435 tmp = ttspeedtab(SIO_TEST_SPEED,
1436 if_16550a_type[iod.if_type & 0x0f].speedtab);
1437 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS);
1438 sio_setreg(com, com_dlbl, tmp & 0xff);
1439 sio_setreg(com, com_dlbh, (tmp >> 8) & 0xff);
1440 sio_setreg(com, com_cfcr, CFCR_8BITS);
1441#else
1442 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS);
1443 sio_setreg(com, com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff);
1444 sio_setreg(com, com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8);
1445 sio_setreg(com, com_cfcr, CFCR_8BITS);
1446#endif
1447 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
1448 }
1449
1450 /*
1451 * Enable the interrupt gate and disable device interupts. This
1452 * should leave the device driving the interrupt line low and
1453 * guarantee an edge trigger if an interrupt can be generated.
1454 */
1455/* EXTRA DELAY? */
1456 sio_setreg(com, com_mcr, mcr_image);
1457 sio_setreg(com, com_ier, 0);
1458 DELAY(1000); /* XXX */
1459 irqmap[0] = isa_irq_pending();
1460
1461 /*
1462 * Attempt to set loopback mode so that we can send a null byte
1463 * without annoying any external device.
1464 */
1465/* EXTRA DELAY? */
1466 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK);
1467
1468 /*
1469 * Attempt to generate an output interrupt. On 8250's, setting
1470 * IER_ETXRDY generates an interrupt independent of the current
1471 * setting and independent of whether the THR is empty. On 16450's,
1472 * setting IER_ETXRDY generates an interrupt independent of the
1473 * current setting. On 16550A's, setting IER_ETXRDY only
1474 * generates an interrupt when IER_ETXRDY is not already set.
1475 */
1476 sio_setreg(com, com_ier, IER_ETXRDY);
1477#ifdef PC98
1478 if (iod.if_type == COM_IF_RSA98III)
1479 outb(iobase + rsa_ier, 0x04);
1480#endif
1481
1482 /*
1483 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
1484 * an interrupt. They'd better generate one for actually doing
1485 * output. Loopback may be broken on the same incompatibles but
1486 * it's unlikely to do more than allow the null byte out.
1487 */
1488 sio_setreg(com, com_data, 0);
1489 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
1490
1491 /*
1492 * Turn off loopback mode so that the interrupt gate works again
1493 * (MCR_IENABLE was hidden). This should leave the device driving
1494 * an interrupt line high. It doesn't matter if the interrupt
1495 * line oscillates while we are not looking at it, since interrupts
1496 * are disabled.
1497 */
1498/* EXTRA DELAY? */
1499 sio_setreg(com, com_mcr, mcr_image);
1500
1501 /*
1502 * Some pcmcia cards have the "TXRDY bug", so we check everyone
1503 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... )
1504 */
1505 if (COM_NOPROBE(flags)) {
1506 /* Reading IIR register twice */
1507 for (fn = 0; fn < 2; fn ++) {
1508 DELAY(10000);
1509 failures[6] = sio_getreg(com, com_iir);
1510 }
1511 /* Check IIR_TXRDY clear ? */
1512 result = 0;
1513 if (failures[6] & IIR_TXRDY) {
1514 /* Nop, Double check with clearing IER */
1515 sio_setreg(com, com_ier, 0);
1516 if (sio_getreg(com, com_iir) & IIR_NOPEND) {
1517 /* Ok. we're familia this gang */
1518 SET_FLAG(dev, COM_C_IIR_TXRDYBUG);
1519 } else {
1520 /* Unknown, Just omit this chip.. XXX */
1521 result = ENXIO;
1522 }
1523 } else {
1524 /* OK. this is well-known guys */
1525 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG);
1526 }
1527 sio_setreg(com, com_cfcr, CFCR_8BITS);
1528 enable_intr();
1529 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1530 return (iobase == siocniobase ? 0 : result);
1531 }
1532
1533 /*
1534 * Check that
1535 * o the CFCR, IER and MCR in UART hold the values written to them
1536 * (the values happen to be all distinct - this is good for
1537 * avoiding false positive tests from bus echoes).
1538 * o an output interrupt is generated and its vector is correct.
1539 * o the interrupt goes away when the IIR in the UART is read.
1540 */
1541/* EXTRA DELAY? */
1542 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS;
1543 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY;
1544 failures[2] = sio_getreg(com, com_mcr) - mcr_image;
1545 DELAY(10000); /* Some internal modems need this time */
1546 irqmap[1] = isa_irq_pending();
1547 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY;
1548#ifdef PC98
1549 if (iod.if_type == COM_IF_RSA98III)
1550 inb(iobase + rsa_srr);
1551#endif
1552 DELAY(1000); /* XXX */
1553 irqmap[2] = isa_irq_pending();
1554 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
1555#ifdef PC98
1556 if (iod.if_type == COM_IF_RSA98III)
1557 inb(iobase + rsa_srr);
1558#endif
1559
1560 /*
1561 * Turn off all device interrupts and check that they go off properly.
1562 * Leave MCR_IENABLE alone. For ports without a master port, it gates
1563 * the OUT2 output of the UART to
1564 * the ICU input. Closing the gate would give a floating ICU input
1565 * (unless there is another device driving it) and spurious interrupts.
1566 * (On the system that this was first tested on, the input floats high
1567 * and gives a (masked) interrupt as soon as the gate is closed.)
1568 */
1569 sio_setreg(com, com_ier, 0);
1570 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
1571 failures[7] = sio_getreg(com, com_ier);
1572#ifdef PC98
1573 if (iod.if_type == COM_IF_RSA98III)
1574 outb(iobase + rsa_ier, 0x00);
1575#endif
1576 DELAY(1000); /* XXX */
1577 irqmap[3] = isa_irq_pending();
1578 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
1579#ifdef PC98
1580 if (iod.if_type == COM_IF_RSA98III) {
1581 inb(iobase + rsa_srr);
1582 outb(iobase + rsa_frr, 0x00);
1583 }
1584#endif
1585
1586 enable_intr();
1587
1588 irqs = irqmap[1] & ~irqmap[0];
1589 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 &&
1590 ((1 << xirq) & irqs) == 0)
1591 printf(
1592 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n",
1593 device_get_unit(dev), xirq, irqs);
1594 if (bootverbose)
1595 printf("sio%d: irq maps: %#x %#x %#x %#x\n",
1596 device_get_unit(dev),
1597 irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
1598
1599 result = 0;
1600 for (fn = 0; fn < sizeof failures; ++fn)
1601 if (failures[fn]) {
1602 sio_setreg(com, com_mcr, 0);
1603 result = ENXIO;
1604 if (bootverbose) {
1605 printf("sio%d: probe failed test(s):",
1606 device_get_unit(dev));
1607 for (fn = 0; fn < sizeof failures; ++fn)
1608 if (failures[fn])
1609 printf(" %d", fn);
1610 printf("\n");
1611 }
1612 break;
1613 }
1614 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1615 return (iobase == siocniobase ? 0 : result);
1616}
1617
1618#ifdef COM_ESP
1619static int
1620espattach(com, esp_port)
1621 struct com_s *com;
1622 Port_t esp_port;
1623{
1624 u_char dips;
1625 u_char val;
1626
1627 /*
1628 * Check the ESP-specific I/O port to see if we're an ESP
1629 * card. If not, return failure immediately.
1630 */
1631 if ((inb(esp_port) & 0xf3) == 0) {
1632 printf(" port 0x%x is not an ESP board?\n", esp_port);
1633 return (0);
1634 }
1635
1636 /*
1637 * We've got something that claims to be a Hayes ESP card.
1638 * Let's hope so.
1639 */
1640
1641 /* Get the dip-switch configuration */
1642#ifdef PC98
1643 outb(esp_port + ESP98_CMD1, ESP_GETDIPS);
1644 dips = inb(esp_port + ESP98_STATUS1);
1645#else
1646 outb(esp_port + ESP_CMD1, ESP_GETDIPS);
1647 dips = inb(esp_port + ESP_STATUS1);
1648#endif
1649
1650 /*
1651 * Bits 0,1 of dips say which COM port we are.
1652 */
1653#ifdef PC98
1654 if ((rman_get_start(com->ioportres) & 0xff) ==
1655 likely_com_ports[dips & 0x03])
1656#else
1657 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03])
1658#endif
1659 printf(" : ESP");
1660 else {
1661 printf(" esp_port has com %d\n", dips & 0x03);
1662 return (0);
1663 }
1664
1665 /*
1666 * Check for ESP version 2.0 or later: bits 4,5,6 = 010.
1667 */
1668#ifdef PC98
1669 outb(esp_port + ESP98_CMD1, ESP_GETTEST);
1670 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */
1671 val = inb(esp_port + ESP98_STATUS2);
1672#else
1673 outb(esp_port + ESP_CMD1, ESP_GETTEST);
1674 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */
1675 val = inb(esp_port + ESP_STATUS2);
1676#endif
1677 if ((val & 0x70) < 0x20) {
1678 printf("-old (%o)", val & 0x70);
1679 return (0);
1680 }
1681
1682 /*
1683 * Check for ability to emulate 16550: bit 7 == 1
1684 */
1685 if ((dips & 0x80) == 0) {
1686 printf(" slave");
1687 return (0);
1688 }
1689
1690 /*
1691 * Okay, we seem to be a Hayes ESP card. Whee.
1692 */
1693 com->esp = TRUE;
1694 com->esp_port = esp_port;
1695 return (1);
1696}
1697#endif /* COM_ESP */
1698
1699static int
1700sio_isa_attach(dev)
1701 device_t dev;
1702{
1703 return (sioattach(dev, 0));
1704}
1705
1706static int
1707sioattach(dev, xrid)
1708 device_t dev;
1709 int xrid;
1710{
1711 struct com_s *com;
1712#ifdef COM_ESP
1713 Port_t *espp;
1714#endif
1715 Port_t iobase;
1716 int unit;
1717 u_int flags;
1718 int rid;
1719 struct resource *port;
1720 int ret;
1721#ifdef PC98
1722 u_char *obuf;
1723 u_long obufsize;
1724 int if_type = GET_IFTYPE(device_get_flags(dev));
1725#endif
1726
1727 rid = xrid;
1728#ifdef PC98
1729 if (IS_8251(if_type)) {
1730 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1731 0, ~0, 1, RF_ACTIVE);
1732 } else if (if_type == COM_IF_RSA98III ||
1733 isa_get_vendorid(dev)) {
1734 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0,
1735 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE);
1736 } else {
1737 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid,
1738 if_16550a_type[if_type & 0x0f].iat,
1739 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE);
1740 }
1741#else
1742 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1743 0, ~0, IO_COMSIZE, RF_ACTIVE);
1744#endif
1745 if (!port)
1746 return (ENXIO);
1747#ifdef PC98
1748 if (!IS_8251(if_type)) {
1749 if (isa_load_resourcev(port,
1750 if_16550a_type[if_type & 0x0f].iat,
1751 if_16550a_type[if_type & 0x0f].iatsz) != 0) {
1752 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1753 return ENXIO;
1754 }
1755 }
1756#endif
1757
1758 iobase = rman_get_start(port);
1759 unit = device_get_unit(dev);
1760 com = device_get_softc(dev);
1761 flags = device_get_flags(dev);
1762
1763 if (unit >= sio_numunits)
1764 sio_numunits = unit + 1;
1765
1766#ifdef PC98
1767 obufsize = 256;
1768 if (if_type == COM_IF_RSA98III)
1769 obufsize = 2048;
1770 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) {
1771 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1772 return ENXIO;
1773 }
1774 bzero(obuf, obufsize * 2);
1775#endif
1776
1777 /*
1778 * sioprobe() has initialized the device registers as follows:
1779 * o cfcr = CFCR_8BITS.
1780 * It is most important that CFCR_DLAB is off, so that the
1781 * data port is not hidden when we enable interrupts.
1782 * o ier = 0.
1783 * Interrupts are only enabled when the line is open.
1784 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
1785 * interrupt control register or the config specifies no irq.
1786 * Keeping MCR_DTR and MCR_RTS off might stop the external
1787 * device from sending before we are ready.
1788 */
1789 bzero(com, sizeof *com);
1790 com->unit = unit;
1791 com->ioportres = port;
1792 com->bst = rman_get_bustag(port);
1793 com->bsh = rman_get_bushandle(port);
1794 com->cfcr_image = CFCR_8BITS;
1795 com->dtr_wait = 3 * hz;
1796 com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
1797 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0;
1798 com->tx_fifo_size = 1;
1799#ifdef PC98
1800 com->obufsize = obufsize;
1801 com->obuf1 = obuf;
1802 com->obuf2 = obuf + obufsize;
1803#endif
1804 com->obufs[0].l_head = com->obuf1;
1805 com->obufs[1].l_head = com->obuf2;
1806
1807#ifdef PC98
1808 com->pc98_if_type = if_type;
1809
1810 if (IS_8251(if_type)) {
1811 pc98_set_ioport(com);
1812
1813 if (if_type == COM_IF_INTERNAL && pc98_check_8251fifo()) {
1814 com->pc98_8251fifo = 1;
1815 com->pc98_8251fifo_enable = 0;
1816 }
1817 } else {
1818 bus_addr_t *iat = if_16550a_type[if_type & 0x0f].iat;
1819
1820 com->data_port = iobase + iat[com_data];
1821 com->int_id_port = iobase + iat[com_iir];
1822 com->modem_ctl_port = iobase + iat[com_mcr];
1823 com->mcr_image = inb(com->modem_ctl_port);
1824 com->line_status_port = iobase + iat[com_lsr];
1825 com->modem_status_port = iobase + iat[com_msr];
1826 com->intr_ctl_port = iobase + iat[com_ier];
1827 }
1828#else /* not PC98 */
1829 com->data_port = iobase + com_data;
1830 com->int_id_port = iobase + com_iir;
1831 com->modem_ctl_port = iobase + com_mcr;
1832 com->mcr_image = inb(com->modem_ctl_port);
1833 com->line_status_port = iobase + com_lsr;
1834 com->modem_status_port = iobase + com_msr;
1835 com->intr_ctl_port = iobase + com_ier;
1836#endif
1837
1838 /*
1839 * We don't use all the flags from <sys/ttydefaults.h> since they
1840 * are only relevant for logins. It's important to have echo off
1841 * initially so that the line doesn't start blathering before the
1842 * echo flag can be turned off.
1843 */
1844 com->it_in.c_iflag = 0;
1845 com->it_in.c_oflag = 0;
1846 com->it_in.c_cflag = TTYDEF_CFLAG;
1847 com->it_in.c_lflag = 0;
1848 if (unit == comconsole) {
1849#ifdef PC98
1850 if (IS_8251(com->pc98_if_type))
1851 DELAY(100000);
1852#endif
1853 com->it_in.c_iflag = TTYDEF_IFLAG;
1854 com->it_in.c_oflag = TTYDEF_OFLAG;
1855 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL;
1856 com->it_in.c_lflag = TTYDEF_LFLAG;
1857 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL;
1858 com->lt_out.c_ispeed = com->lt_out.c_ospeed =
1859 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
1860 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate;
1861 } else
1862 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED;
1863 if (siosetwater(com, com->it_in.c_ispeed) != 0) {
1864 enable_intr();
1865 /*
1866 * Leave i/o resources allocated if this is a `cn'-level
1867 * console, so that other devices can't snarf them.
1868 */
1869 if (iobase != siocniobase)
1870 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1871 return (ENOMEM);
1872 }
1873 enable_intr();
1874 termioschars(&com->it_in);
1875 com->it_out = com->it_in;
1876
1877 /* attempt to determine UART type */
1878 printf("sio%d: type", unit);
1879
1880
1881#ifndef PC98
1882#ifdef COM_MULTIPORT
1883 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags))
1884#else
1885 if (!COM_IIR_TXRDYBUG(flags))
1886#endif
1887 {
1888 u_char scr;
1889 u_char scr1;
1890 u_char scr2;
1891
1892 scr = sio_getreg(com, com_scr);
1893 sio_setreg(com, com_scr, 0xa5);
1894 scr1 = sio_getreg(com, com_scr);
1895 sio_setreg(com, com_scr, 0x5a);
1896 scr2 = sio_getreg(com, com_scr);
1897 sio_setreg(com, com_scr, scr);
1898 if (scr1 != 0xa5 || scr2 != 0x5a) {
1899 printf(" 8250");
1900 goto determined_type;
1901 }
1902 }
1903#endif /* !PC98 */
1904#ifdef PC98
1905 if (IS_8251(com->pc98_if_type)) {
1906 if (com->pc98_8251fifo && !COM_NOFIFO(flags))
1907 com->tx_fifo_size = 16;
1908 com_int_TxRx_disable( com );
1909 com_cflag_and_speed_set( com, com->it_in.c_cflag, comdefaultrate );
1910 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
1911 com_send_break_off( com );
1912
1913 if (com->pc98_if_type == COM_IF_INTERNAL) {
1914 printf(" (internal%s%s)",
1915 com->pc98_8251fifo ? " fifo" : "",
1916 PC98SIO_baud_rate_port(com->pc98_if_type) != -1 ?
1917 " v-fast" : "");
1918 } else {
1919 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name);
1920 }
1921 } else {
1922#endif /* PC98 */
1923 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
1924 DELAY(100);
1925 com->st16650a = 0;
1926 switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
1927 case FIFO_RX_LOW:
1928 printf(" 16450");
1929 break;
1930 case FIFO_RX_MEDL:
1931 printf(" 16450?");
1932 break;
1933 case FIFO_RX_MEDH:
1934 printf(" 16550?");
1935 break;
1936 case FIFO_RX_HIGH:
1937 if (COM_NOFIFO(flags)) {
1938 printf(" 16550A fifo disabled");
1939 } else {
1940 com->hasfifo = TRUE;
1941#ifdef PC98
1942 com->tx_fifo_size = 0; /* XXX flag conflicts. */
1943 printf(" 16550A");
1944#else
1945 if (COM_ST16650A(flags)) {
1946 com->st16650a = 1;
1947 com->tx_fifo_size = 32;
1948 printf(" ST16650A");
1949 } else {
1950 com->tx_fifo_size = COM_FIFOSIZE(flags);
1951 printf(" 16550A");
1952 }
1953#endif
1954 }
1955#ifdef PC98
1956 if (com->pc98_if_type == COM_IF_RSA98III) {
1957 com->tx_fifo_size = 2048;
1958 com->rsabase = iobase;
1959 outb(com->rsabase + rsa_ier, 0x00);
1960 outb(com->rsabase + rsa_frr, 0x00);
1961 }
1962#endif
1963
1964#ifdef COM_ESP
1965#ifdef PC98
1966 if (com->pc98_if_type == COM_IF_ESP98)
1967#endif
1968 for (espp = likely_esp_ports; *espp != 0; espp++)
1969 if (espattach(com, *espp)) {
1970 com->tx_fifo_size = 1024;
1971 break;
1972 }
1973#endif
1974 if (!com->st16650a) {
1975 if (!com->tx_fifo_size)
1976 com->tx_fifo_size = 16;
1977 else
1978 printf(" lookalike with %d bytes FIFO",
1979 com->tx_fifo_size);
1980 }
1981
1982 break;
1983 }
1984
1985#ifdef PC98
1986 if (com->pc98_if_type == COM_IF_RSB3000) {
1987 /* Set RSB-2000/3000 Extended Buffer mode. */
1988 u_char lcr;
1989 lcr = sio_getreg(com, com_cfcr);
1990 sio_setreg(com, com_cfcr, lcr | CFCR_DLAB);
1991 sio_setreg(com, com_emr, EMR_EXBUFF | EMR_EFMODE);
1992 sio_setreg(com, com_cfcr, lcr);
1993 }
1994#endif
1995
1996#ifdef COM_ESP
1997 if (com->esp) {
1998 /*
1999 * Set 16550 compatibility mode.
2000 * We don't use the ESP_MODE_SCALE bit to increase the
2001 * fifo trigger levels because we can't handle large
2002 * bursts of input.
2003 * XXX flow control should be set in comparam(), not here.
2004 */
2005#ifdef PC98
2006 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE);
2007 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
2008#else
2009 outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
2010 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
2011#endif
2012
2013 /* Set RTS/CTS flow control. */
2014#ifdef PC98
2015 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE);
2016 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS);
2017 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS);
2018#else
2019 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
2020 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
2021 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
2022#endif
2023
2024 /* Set flow-control levels. */
2025#ifdef PC98
2026 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW);
2027 outb(com->esp_port + ESP98_CMD2, HIBYTE(768));
2028 outb(com->esp_port + ESP98_CMD2, LOBYTE(768));
2029 outb(com->esp_port + ESP98_CMD2, HIBYTE(512));
2030 outb(com->esp_port + ESP98_CMD2, LOBYTE(512));
2031#else
2032 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
2033 outb(com->esp_port + ESP_CMD2, HIBYTE(768));
2034 outb(com->esp_port + ESP_CMD2, LOBYTE(768));
2035 outb(com->esp_port + ESP_CMD2, HIBYTE(512));
2036 outb(com->esp_port + ESP_CMD2, LOBYTE(512));
2037#endif
2038
2039#ifdef PC98
2040 /* Set UART clock prescaler. */
2041 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK);
2042 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */
2043#endif
2044 }
2045#endif /* COM_ESP */
2046 sio_setreg(com, com_fifo, 0);
2047#ifdef PC98
2048 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name);
2049#else
2050determined_type: ;
2051#endif
2052
2053#ifdef COM_MULTIPORT
2054 if (COM_ISMULTIPORT(flags)) {
2055 device_t masterdev;
2056
2057 com->multiport = TRUE;
2058 printf(" (multiport");
2059 if (unit == COM_MPMASTER(flags))
2060 printf(" master");
2061 printf(")");
2062 masterdev = devclass_get_device(sio_devclass,
2063 COM_MPMASTER(flags));
2064 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev,
2065 SYS_RES_IRQ, 0, NULL, NULL) != 0);
2066 }
2067#endif /* COM_MULTIPORT */
2068#ifdef PC98
2069 }
2070#endif
2071 if (unit == comconsole)
2072 printf(", console");
2073 if (COM_IIR_TXRDYBUG(flags))
2074 printf(" with a bogus IIR_TXRDY register");
2075 printf("\n");
2076
2077 if (!sio_registered) {
2078 register_swi(SWI_TTY, siopoll);
2079 sio_registered = TRUE;
2080 }
2081 make_dev(&sio_cdevsw, unit,
2082 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit);
2083 make_dev(&sio_cdevsw, unit | CONTROL_INIT_STATE,
2084 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit);
2085 make_dev(&sio_cdevsw, unit | CONTROL_LOCK_STATE,
2086 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit);
2087 make_dev(&sio_cdevsw, unit | CALLOUT_MASK,
2088 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit);
2089 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_INIT_STATE,
2090 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit);
2091 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_LOCK_STATE,
2092 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit);
2093 com->flags = flags;
2094 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
2095 pps_init(&com->pps);
2096
2097 rid = 0;
2098 com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1,
2099 RF_ACTIVE);
2100 if (com->irqres) {
2101 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres,
2102 INTR_TYPE_TTY | INTR_TYPE_FAST,
2103 siointr, com, &com->cookie);
2104 if (ret) {
2105 ret = BUS_SETUP_INTR(device_get_parent(dev), dev,
2106 com->irqres, INTR_TYPE_TTY,
2107 siointr, com, &com->cookie);
2108 if (ret == 0)
2109 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode");
2110 }
2111 if (ret)
2112 device_printf(dev, "could not activate interrupt\n");
2113 }
2114
2115 return (0);
2116}
2117
2118static int
2119sioopen(dev, flag, mode, p)
2120 dev_t dev;
2121 int flag;
2122 int mode;
2123 struct proc *p;
2124{
2125 struct com_s *com;
2126 int error;
2127 int mynor;
2128 int s;
2129 struct tty *tp;
2130 int unit;
2131
2132 mynor = minor(dev);
2133 unit = MINOR_TO_UNIT(mynor);
2134 com = com_addr(unit);
2135 if (com == NULL)
2136 return (ENXIO);
2137 if (com->gone)
2138 return (ENXIO);
2139 if (mynor & CONTROL_MASK)
2140 return (0);
2141 tp = dev->si_tty = com->tp = ttymalloc(com->tp);
2142 s = spltty();
2143 /*
2144 * We jump to this label after all non-interrupted sleeps to pick
2145 * up any changes of the device state.
2146 */
2147open_top:
2148 while (com->state & CS_DTR_OFF) {
2149 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0);
2150 if (com_addr(unit) == NULL)
2151 return (ENXIO);
2152 if (error != 0 || com->gone)
2153 goto out;
2154 }
2155 if (tp->t_state & TS_ISOPEN) {
2156 /*
2157 * The device is open, so everything has been initialized.
2158 * Handle conflicts.
2159 */
2160 if (mynor & CALLOUT_MASK) {
2161 if (!com->active_out) {
2162 error = EBUSY;
2163 goto out;
2164 }
2165 } else {
2166 if (com->active_out) {
2167 if (flag & O_NONBLOCK) {
2168 error = EBUSY;
2169 goto out;
2170 }
2171 error = tsleep(&com->active_out,
2172 TTIPRI | PCATCH, "siobi", 0);
2173 if (com_addr(unit) == NULL)
2174 return (ENXIO);
2175 if (error != 0 || com->gone)
2176 goto out;
2177 goto open_top;
2178 }
2179 }
2180 if (tp->t_state & TS_XCLUDE &&
2181 suser(p)) {
2182 error = EBUSY;
2183 goto out;
2184 }
2185 } else {
2186 /*
2187 * The device isn't open, so there are no conflicts.
2188 * Initialize it. Initialization is done twice in many
2189 * cases: to preempt sleeping callin opens if we are
2190 * callout, and to complete a callin open after DCD rises.
2191 */
2192 tp->t_oproc = comstart;
2193 tp->t_param = comparam;
2194 tp->t_stop = comstop;
2195 tp->t_dev = dev;
2196 tp->t_termios = mynor & CALLOUT_MASK
2197 ? com->it_out : com->it_in;
2198#ifdef PC98
2199 if (!IS_8251(com->pc98_if_type))
2200#endif
2201 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
2202 com->poll = com->no_irq;
2203 com->poll_output = com->loses_outints;
2204 ++com->wopeners;
2205 error = comparam(tp, &tp->t_termios);
2206 --com->wopeners;
2207 if (error != 0)
2208 goto out;
2209#ifdef PC98
2210 if (IS_8251(com->pc98_if_type)) {
2211 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS);
2212 pc98_msrint_start(dev);
2213 if (com->pc98_8251fifo) {
2214 com->pc98_8251fifo_enable = 1;
2215 outb(I8251F_fcr, CTRL8251F_ENABLE |
2216 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST);
2217 }
2218 }
2219#endif
2220 /*
2221 * XXX we should goto open_top if comparam() slept.
2222 */
2223 if (com->hasfifo) {
2224 /*
2225 * (Re)enable and drain fifos.
2226 *
2227 * Certain SMC chips cause problems if the fifos
2228 * are enabled while input is ready. Turn off the
2229 * fifo if necessary to clear the input. We test
2230 * the input ready bit after enabling the fifos
2231 * since we've already enabled them in comparam()
2232 * and to handle races between enabling and fresh
2233 * input.
2234 */
2235 while (TRUE) {
2236 sio_setreg(com, com_fifo,
2237 FIFO_RCV_RST | FIFO_XMT_RST
2238 | com->fifo_image);
2239#ifdef PC98
2240 if (com->pc98_if_type == COM_IF_RSA98III)
2241 outb(com->rsabase + rsa_frr , 0x00);
2242#endif
2243 /*
2244 * XXX the delays are for superstitious
2245 * historical reasons. It must be less than
2246 * the character time at the maximum
2247 * supported speed (87 usec at 115200 bps
2248 * 8N1). Otherwise we might loop endlessly
2249 * if data is streaming in. We used to use
2250 * delays of 100. That usually worked
2251 * because DELAY(100) used to usually delay
2252 * for about 85 usec instead of 100.
2253 */
2254 DELAY(50);
2255#ifdef PC98
2256 if (com->pc98_if_type == COM_IF_RSA98III ?
2257 !(inb(com->rsabase + rsa_srr) & 0x08) :
2258 !(inb(com->line_status_port) & LSR_RXRDY))
2259 break;
2260#else
2261 if (!(inb(com->line_status_port) & LSR_RXRDY))
2262 break;
2263#endif
2264 sio_setreg(com, com_fifo, 0);
2265 DELAY(50);
2266 (void) inb(com->data_port);
2267 }
2268 }
2269
2270 disable_intr();
2271#ifdef PC98
2272 if (IS_8251(com->pc98_if_type)) {
2273 com_tiocm_bis(com, TIOCM_LE);
2274 com->pc98_prev_modem_status = pc98_get_modem_status(com);
2275 com_int_Rx_enable(com);
2276 } else {
2277#endif
2278 (void) inb(com->line_status_port);
2279 (void) inb(com->data_port);
2280 com->prev_modem_status = com->last_modem_status
2281 = inb(com->modem_status_port);
2282 if (COM_IIR_TXRDYBUG(com->flags)) {
2283 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS
2284 | IER_EMSC);
2285 } else {
2286 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY
2287 | IER_ERLS | IER_EMSC);
2288 }
2289#ifdef PC98
2290 if (com->pc98_if_type == COM_IF_RSA98III) {
2291 outb(com->rsabase + rsa_ier, 0x1d);
2292 outb(com->intr_ctl_port, IER_ERLS | IER_EMSC);
2293 }
2294#endif
2295#ifdef PC98
2296 }
2297#endif
2298 enable_intr();
2299 /*
2300 * Handle initial DCD. Callout devices get a fake initial
2301 * DCD (trapdoor DCD). If we are callout, then any sleeping
2302 * callin opens get woken up and resume sleeping on "siobi"
2303 * instead of "siodcd".
2304 */
2305 /*
2306 * XXX `mynor & CALLOUT_MASK' should be
2307 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where
2308 * TRAPDOOR_CARRIER is the default initial state for callout
2309 * devices and SOFT_CARRIER is like CLOCAL except it hides
2310 * the true carrier.
2311 */
2312#ifdef PC98
2313 if ((IS_8251(com->pc98_if_type) &&
2314 (pc98_get_modem_status(com) & TIOCM_CAR)) ||
2315 (!IS_8251(com->pc98_if_type) &&
2316 (com->prev_modem_status & MSR_DCD)) ||
2317 mynor & CALLOUT_MASK)
2318 (*linesw[tp->t_line].l_modem)(tp, 1);
2319#else
2320 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK)
2321 (*linesw[tp->t_line].l_modem)(tp, 1);
2322#endif
2323 }
2324 /*
2325 * Wait for DCD if necessary.
2326 */
2327 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK)
2328 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
2329 ++com->wopeners;
2330 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0);
2331 if (com_addr(unit) == NULL)
2332 return (ENXIO);
2333 --com->wopeners;
2334 if (error != 0 || com->gone)
2335 goto out;
2336 goto open_top;
2337 }
2338 error = (*linesw[tp->t_line].l_open)(dev, tp);
2339 disc_optim(tp, &tp->t_termios, com);
2340 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK)
2341 com->active_out = TRUE;
2342 siosettimeout();
2343out:
2344 splx(s);
2345 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0)
2346 comhardclose(com);
2347 return (error);
2348}
2349
2350static int
2351sioclose(dev, flag, mode, p)
2352 dev_t dev;
2353 int flag;
2354 int mode;
2355 struct proc *p;
2356{
2357 struct com_s *com;
2358 int mynor;
2359 int s;
2360 struct tty *tp;
2361
2362 mynor = minor(dev);
2363 if (mynor & CONTROL_MASK)
2364 return (0);
2365 com = com_addr(MINOR_TO_UNIT(mynor));
2366 if (com == NULL)
2367 return (ENODEV);
2368 tp = com->tp;
2369 s = spltty();
2370 (*linesw[tp->t_line].l_close)(tp, flag);
2371#ifdef PC98
2372 com->modem_checking = 0;
2373#endif
2374 disc_optim(tp, &tp->t_termios, com);
2375 comstop(tp, FREAD | FWRITE);
2376 comhardclose(com);
2377 ttyclose(tp);
2378 siosettimeout();
2379 splx(s);
2380 if (com->gone) {
2381 printf("sio%d: gone\n", com->unit);
2382 s = spltty();
2383 if (com->ibuf != NULL)
2384 free(com->ibuf, M_DEVBUF);
2385 bzero(tp, sizeof *tp);
2386 splx(s);
2387 }
2388 return (0);
2389}
2390
2391static void
2392comhardclose(com)
2393 struct com_s *com;
2394{
2395 int s;
2396 struct tty *tp;
2397 int unit;
2398
2399 unit = com->unit;
2400 s = spltty();
2401 com->poll = FALSE;
2402 com->poll_output = FALSE;
2403 com->do_timestamp = FALSE;
2404 com->do_dcd_timestamp = FALSE;
2405 com->pps.ppsparam.mode = 0;
2406#ifdef PC98
2407 if (IS_8251(com->pc98_if_type))
2408 com_send_break_off(com);
2409 else
2410#endif
2411 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2412 {
2413#ifdef PC98
2414 int tmp;
2415 if (IS_8251(com->pc98_if_type))
2416 com_int_TxRx_disable(com);
2417 else
2418 sio_setreg(com, com_ier, 0);
2419 if (com->pc98_if_type == COM_IF_RSA98III)
2420 outb(com->rsabase + rsa_ier, 0x00);
2421#else
2422 sio_setreg(com, com_ier, 0);
2423#endif
2424 tp = com->tp;
2425#ifdef PC98
2426 if (IS_8251(com->pc98_if_type))
2427 tmp = pc98_get_modem_status(com) & TIOCM_CAR;
2428 else
2429 tmp = com->prev_modem_status & MSR_DCD;
2430#endif
2431 if (tp->t_cflag & HUPCL
2432 /*
2433 * XXX we will miss any carrier drop between here and the
2434 * next open. Perhaps we should watch DCD even when the
2435 * port is closed; it is not sufficient to check it at
2436 * the next open because it might go up and down while
2437 * we're not watching.
2438 */
2439 || (!com->active_out
2440#ifdef PC98
2441 && !(tmp)
2442#else
2443 && !(com->prev_modem_status & MSR_DCD)
2444#endif
2445 && !(com->it_in.c_cflag & CLOCAL))
2446 || !(tp->t_state & TS_ISOPEN)) {
2447#ifdef PC98
2448 if (IS_8251(com->pc98_if_type))
2449 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
2450 else
2451#endif
2452 (void)commctl(com, TIOCM_DTR, DMBIC);
2453 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) {
2454 timeout(siodtrwakeup, com, com->dtr_wait);
2455 com->state |= CS_DTR_OFF;
2456 }
2457 }
2458#ifdef PC98
2459 else {
2460 if (IS_8251(com->pc98_if_type))
2461 com_tiocm_bic(com, TIOCM_LE);
2462 }
2463#endif
2464 }
2465#ifdef PC98
2466 if (com->pc98_8251fifo) {
2467 if (com->pc98_8251fifo_enable)
2468 outb(I8251F_fcr, CTRL8251F_XMT_RST | CTRL8251F_RCV_RST);
2469 com->pc98_8251fifo_enable = 0;
2470 }
2471#endif
2472 if (com->hasfifo) {
2473 /*
2474 * Disable fifos so that they are off after controlled
2475 * reboots. Some BIOSes fail to detect 16550s when the
2476 * fifos are enabled.
2477 */
2478 sio_setreg(com, com_fifo, 0);
2479 }
2480 com->active_out = FALSE;
2481 wakeup(&com->active_out);
2482 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */
2483 splx(s);
2484}
2485
2486static int
2487sioread(dev, uio, flag)
2488 dev_t dev;
2489 struct uio *uio;
2490 int flag;
2491{
2492 int mynor;
2493 struct com_s *com;
2494
2495 mynor = minor(dev);
2496 if (mynor & CONTROL_MASK)
2497 return (ENODEV);
2498 com = com_addr(MINOR_TO_UNIT(mynor));
2499 if (com == NULL || com->gone)
2500 return (ENODEV);
2501 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag));
2502}
2503
2504static int
2505siowrite(dev, uio, flag)
2506 dev_t dev;
2507 struct uio *uio;
2508 int flag;
2509{
2510 int mynor;
2511 struct com_s *com;
2512 int unit;
2513
2514 mynor = minor(dev);
2515 if (mynor & CONTROL_MASK)
2516 return (ENODEV);
2517
2518 unit = MINOR_TO_UNIT(mynor);
2519 com = com_addr(unit);
2520 if (com == NULL || com->gone)
2521 return (ENODEV);
2522 /*
2523 * (XXX) We disallow virtual consoles if the physical console is
2524 * a serial port. This is in case there is a display attached that
2525 * is not the console. In that situation we don't need/want the X
2526 * server taking over the console.
2527 */
2528 if (constty != NULL && unit == comconsole)
2529 constty = NULL;
2530 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag));
2531}
2532
2533static void
2534siobusycheck(chan)
2535 void *chan;
2536{
2537 struct com_s *com;
2538 int s;
2539
2540 com = (struct com_s *)chan;
2541
2542 /*
2543 * Clear TS_BUSY if low-level output is complete.
2544 * spl locking is sufficient because siointr1() does not set CS_BUSY.
2545 * If siointr1() clears CS_BUSY after we look at it, then we'll get
2546 * called again. Reading the line status port outside of siointr1()
2547 * is safe because CS_BUSY is clear so there are no output interrupts
2548 * to lose.
2549 */
2550 s = spltty();
2551 if (com->state & CS_BUSY)
2552 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */
2553#ifdef PC98
2554 else if ((IS_8251(com->pc98_if_type) &&
2555 ((com->pc98_8251fifo_enable &&
2556 (inb(I8251F_lsr) & (STS8251F_TxRDY | STS8251F_TxEMP))
2557 == (STS8251F_TxRDY | STS8251F_TxEMP)) ||
2558 (!com->pc98_8251fifo_enable &&
2559 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP))
2560 == (STS8251_TxRDY | STS8251_TxEMP)))) ||
2561 ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2562 == (LSR_TSRE | LSR_TXRDY))) {
2563#else
2564 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2565 == (LSR_TSRE | LSR_TXRDY)) {
2566#endif
2567 com->tp->t_state &= ~TS_BUSY;
2568 ttwwakeup(com->tp);
2569 com->extra_state &= ~CSE_BUSYCHECK;
2570 } else
2571 timeout(siobusycheck, com, hz / 100);
2572 splx(s);
2573}
2574
2575static void
2576siodtrwakeup(chan)
2577 void *chan;
2578{
2579 struct com_s *com;
2580
2581 com = (struct com_s *)chan;
2582 com->state &= ~CS_DTR_OFF;
2583 wakeup(&com->dtr_wait);
2584}
2585
2586static void
2587sioinput(com)
2588 struct com_s *com;
2589{
2590 u_char *buf;
2591 int incc;
2592 u_char line_status;
2593 int recv_data;
2594 struct tty *tp;
2595
2596 buf = com->ibuf;
2597 tp = com->tp;
2598 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) {
2599 com_events -= (com->iptr - com->ibuf);
2600 com->iptr = com->ibuf;
2601 return;
2602 }
2603 if (tp->t_state & TS_CAN_BYPASS_L_RINT) {
2604 /*
2605 * Avoid the grotesquely inefficient lineswitch routine
2606 * (ttyinput) in "raw" mode. It usually takes about 450
2607 * instructions (that's without canonical processing or echo!).
2608 * slinput is reasonably fast (usually 40 instructions plus
2609 * call overhead).
2610 */
2611 do {
2612 enable_intr();
2613 incc = com->iptr - buf;
2614 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat
2615 && (com->state & CS_RTS_IFLOW
2616 || tp->t_iflag & IXOFF)
2617 && !(tp->t_state & TS_TBLOCK))
2618 ttyblock(tp);
2619 com->delta_error_counts[CE_TTY_BUF_OVERFLOW]
2620 += b_to_q((char *)buf, incc, &tp->t_rawq);
2621 buf += incc;
2622 tk_nin += incc;
2623 tk_rawcc += incc;
2624 tp->t_rawcc += incc;
2625 ttwakeup(tp);
2626 if (tp->t_state & TS_TTSTOP
2627 && (tp->t_iflag & IXANY
2628 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) {
2629 tp->t_state &= ~TS_TTSTOP;
2630 tp->t_lflag &= ~FLUSHO;
2631 comstart(tp);
2632 }
2633 disable_intr();
2634 } while (buf < com->iptr);
2635 } else {
2636 do {
2637 enable_intr();
2638 line_status = buf[com->ierroff];
2639 recv_data = *buf++;
2640 if (line_status
2641 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) {
2642 if (line_status & LSR_BI)
2643 recv_data |= TTY_BI;
2644 if (line_status & LSR_FE)
2645 recv_data |= TTY_FE;
2646 if (line_status & LSR_OE)
2647 recv_data |= TTY_OE;
2648 if (line_status & LSR_PE)
2649 recv_data |= TTY_PE;
2650 }
2651 (*linesw[tp->t_line].l_rint)(recv_data, tp);
2652 disable_intr();
2653 } while (buf < com->iptr);
2654 }
2655 com_events -= (com->iptr - com->ibuf);
2656 com->iptr = com->ibuf;
2657
2658 /*
2659 * There is now room for another low-level buffer full of input,
2660 * so enable RTS if it is now disabled and there is room in the
2661 * high-level buffer.
2662 */
2663#ifdef PC98
2664 if (IS_8251(com->pc98_if_type)) {
2665 if ((com->state & CS_RTS_IFLOW) &&
2666 !(com_tiocm_get(com) & TIOCM_RTS) &&
2667 !(tp->t_state & TS_TBLOCK))
2668 com_tiocm_bis(com, TIOCM_RTS);
2669 } else {
2670 if ((com->state & CS_RTS_IFLOW) &&
2671 !(com->mcr_image & MCR_RTS) &&
2672 !(tp->t_state & TS_TBLOCK))
2673 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2674 }
2675#else
2676 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) &&
2677 !(tp->t_state & TS_TBLOCK))
2678 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2679#endif
2680}
2681
2682void
2683siointr(arg)
2684 void *arg;
2685{
2686#ifndef COM_MULTIPORT
2687 COM_LOCK();
2688 siointr1((struct com_s *) arg);
2689 COM_UNLOCK();
2690#else /* COM_MULTIPORT */
2691 bool_t possibly_more_intrs;
2692 int unit;
2693 struct com_s *com;
2694#ifdef PC98
2695 u_char rsa_buf_status;
2696#endif
2697
2698 /*
2699 * Loop until there is no activity on any port. This is necessary
2700 * to get an interrupt edge more than to avoid another interrupt.
2701 * If the IRQ signal is just an OR of the IRQ signals from several
2702 * devices, then the edge from one may be lost because another is
2703 * on.
2704 */
2705 COM_LOCK();
2706 do {
2707 possibly_more_intrs = FALSE;
2708 for (unit = 0; unit < sio_numunits; ++unit) {
2709 com = com_addr(unit);
2710 /*
2711 * XXX COM_LOCK();
2712 * would it work here, or be counter-productive?
2713 */
2714#ifdef PC98
2715 if (com != NULL
2716 && !com->gone
2717 && IS_8251(com->pc98_if_type)) {
2718 siointr1(com);
2719 } else if (com != NULL
2720 && !com->gone
2721 && com->pc98_if_type == COM_IF_RSA98III) {
2722 rsa_buf_status =
2723 inb(com->rsabase + rsa_srr) & 0xc9;
2724 if ((rsa_buf_status & 0xc8)
2725 || !(rsa_buf_status & 0x01)) {
2726 siointr1(com);
2727 if (rsa_buf_status !=
2728 (inb(com->rsabase + rsa_srr) & 0xc9))
2729 possibly_more_intrs = TRUE;
2730 }
2731 } else
2732#endif
2733 if (com != NULL
2734 && !com->gone
2735 && (inb(com->int_id_port) & IIR_IMASK)
2736 != IIR_NOPEND) {
2737 siointr1(com);
2738 possibly_more_intrs = TRUE;
2739 }
2740 /* XXX COM_UNLOCK(); */
2741 }
2742 } while (possibly_more_intrs);
2743 COM_UNLOCK();
2744#endif /* COM_MULTIPORT */
2745}
2746
2747static void
2748siointr1(com)
2749 struct com_s *com;
2750{
2751 u_char line_status;
2752 u_char modem_status;
2753 u_char *ioptr;
2754 u_char recv_data;
2755 u_char int_ctl;
2756 u_char int_ctl_new;
2757 struct timecounter *tc;
2758 u_int count;
2759
2760#ifdef PC98
2761 u_char tmp = 0;
2762 u_char rsa_buf_status = 0;
2763 int rsa_tx_fifo_size = 0;
2764#endif /* PC98 */
2765
2766 int_ctl = inb(com->intr_ctl_port);
2767 int_ctl_new = int_ctl;
2768
2769 while (!com->gone) {
2770#ifdef PC98
2771status_read:;
2772 if (IS_8251(com->pc98_if_type)) {
2773 if (com->pc98_8251fifo_enable)
2774 tmp = inb(I8251F_lsr);
2775 else
2776 tmp = inb(com->sts_port);
2777more_intr:
2778 line_status = 0;
2779 if (com->pc98_8251fifo_enable) {
2780 if (tmp & STS8251F_TxRDY) line_status |= LSR_TXRDY;
2781 if (tmp & STS8251F_RxRDY) line_status |= LSR_RXRDY;
2782 if (tmp & STS8251F_TxEMP) line_status |= LSR_TSRE;
2783 if (tmp & STS8251F_PE) line_status |= LSR_PE;
2784 if (tmp & STS8251F_OE) line_status |= LSR_OE;
2785 if (tmp & STS8251F_BD_SD) line_status |= LSR_BI;
2786 } else {
2787 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY;
2788 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY;
2789 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE;
2790 if (tmp & STS8251_PE) line_status |= LSR_PE;
2791 if (tmp & STS8251_OE) line_status |= LSR_OE;
2792 if (tmp & STS8251_FE) line_status |= LSR_FE;
2793 if (tmp & STS8251_BD_SD) line_status |= LSR_BI;
2794 }
2795 } else {
2796#endif /* PC98 */
2797 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) {
2798 modem_status = inb(com->modem_status_port);
2799 if ((modem_status ^ com->last_modem_status) & MSR_DCD) {
2800 tc = timecounter;
2801 count = tc->tc_get_timecount(tc);
2802 pps_event(&com->pps, tc, count,
2803 (modem_status & MSR_DCD) ?
2804 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR);
2805 }
2806 }
2807 line_status = inb(com->line_status_port);
2808#ifdef PC98
2809 }
2810 if (com->pc98_if_type == COM_IF_RSA98III)
2811 rsa_buf_status = inb(com->rsabase + rsa_srr);
2812#endif /* PC98 */
2813
2814 /* input event? (check first to help avoid overruns) */
2815#ifndef PC98
2816 while (line_status & LSR_RCV_MASK) {
2817#else
2818 while ((line_status & LSR_RCV_MASK)
2819 || (com->pc98_if_type == COM_IF_RSA98III
2820 && (rsa_buf_status & 0x08))) {
2821#endif /* PC98 */
2822 /* break/unnattached error bits or real input? */
2823#ifdef PC98
2824 if (IS_8251(com->pc98_if_type)) {
2825 if (com->pc98_8251fifo_enable) {
2826 recv_data = inb(I8251F_data);
2827 if (tmp & (STS8251F_PE | STS8251F_OE |
2828 STS8251F_BD_SD)) {
2829 pc98_i8251_or_cmd(com, CMD8251_ER);
2830 recv_data = 0;
2831 }
2832 } else {
2833 recv_data = inb(com->data_port);
2834 if (tmp & (STS8251_PE | STS8251_OE |
2835 STS8251_FE | STS8251_BD_SD)) {
2836 pc98_i8251_or_cmd(com, CMD8251_ER);
2837 recv_data = 0;
2838 }
2839 }
2840 } else if (com->pc98_if_type == COM_IF_RSA98III) {
2841 if (!(rsa_buf_status & 0x08))
2842 recv_data = 0;
2843 else
2844 recv_data = inb(com->data_port);
2845 } else
2846#endif
2847 if (!(line_status & LSR_RXRDY))
2848 recv_data = 0;
2849 else
2850 recv_data = inb(com->data_port);
2851 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
2852 /*
2853 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
2854 * Otherwise, push the work to a higher level
2855 * (to handle PARMRK) if we're bypassing.
2856 * Otherwise, convert BI/FE and PE+INPCK to 0.
2857 *
2858 * This makes bypassing work right in the
2859 * usual "raw" case (IGNBRK set, and IGNPAR
2860 * and INPCK clear).
2861 *
2862 * Note: BI together with FE/PE means just BI.
2863 */
2864 if (line_status & LSR_BI) {
2865#if defined(DDB) && defined(BREAK_TO_DEBUGGER)
2866 if (com->unit == comconsole) {
2867 breakpoint();
2868 goto cont;
2869 }
2870#endif
2871 if (com->tp == NULL
2872 || com->tp->t_iflag & IGNBRK)
2873 goto cont;
2874 } else {
2875 if (com->tp == NULL
2876 || com->tp->t_iflag & IGNPAR)
2877 goto cont;
2878 }
2879 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT
2880 && (line_status & (LSR_BI | LSR_FE)
2881 || com->tp->t_iflag & INPCK))
2882 recv_data = 0;
2883 }
2884 ++com->bytes_in;
2885 if (com->hotchar != 0 && recv_data == com->hotchar)
2886 setsofttty();
2887 ioptr = com->iptr;
2888 if (ioptr >= com->ibufend)
2889 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW);
2890 else {
2891 if (com->do_timestamp)
2892 microtime(&com->timestamp);
2893 ++com_events;
2894 schedsofttty();
2895#if 0 /* for testing input latency vs efficiency */
2896if (com->iptr - com->ibuf == 8)
2897 setsofttty();
2898#endif
2899 ioptr[0] = recv_data;
2900 ioptr[com->ierroff] = line_status;
2901 com->iptr = ++ioptr;
2902 if (ioptr == com->ihighwater
2903 && com->state & CS_RTS_IFLOW)
2904#ifdef PC98
2905 IS_8251(com->pc98_if_type) ?
2906 com_tiocm_bic(com, TIOCM_RTS) :
2907#endif
2908 outb(com->modem_ctl_port,
2909 com->mcr_image &= ~MCR_RTS);
2910 if (line_status & LSR_OE)
2911 CE_RECORD(com, CE_OVERRUN);
2912 }
2913cont:
2914 /*
2915 * "& 0x7F" is to avoid the gcc-1.40 generating a slow
2916 * jump from the top of the loop to here
2917 */
2918#ifdef PC98
2919 if (IS_8251(com->pc98_if_type))
2920 goto status_read;
2921 else
2922#endif
2923 line_status = inb(com->line_status_port) & 0x7F;
2924#ifdef PC98
2925 if (com->pc98_if_type == COM_IF_RSA98III)
2926 rsa_buf_status = inb(com->rsabase + rsa_srr);
2927#endif /* PC98 */
2928 }
2929
2930 /* modem status change? (always check before doing output) */
2931#ifdef PC98
2932 if (!IS_8251(com->pc98_if_type)) {
2933#endif
2934 modem_status = inb(com->modem_status_port);
2935 if (modem_status != com->last_modem_status) {
2936 if (com->do_dcd_timestamp
2937 && !(com->last_modem_status & MSR_DCD)
2938 && modem_status & MSR_DCD)
2939 microtime(&com->dcd_timestamp);
2940
2941 /*
2942 * Schedule high level to handle DCD changes. Note
2943 * that we don't use the delta bits anywhere. Some
2944 * UARTs mess them up, and it's easy to remember the
2945 * previous bits and calculate the delta.
2946 */
2947 com->last_modem_status = modem_status;
2948 if (!(com->state & CS_CHECKMSR)) {
2949 com_events += LOTS_OF_EVENTS;
2950 com->state |= CS_CHECKMSR;
2951 setsofttty();
2952 }
2953
2954 /* handle CTS change immediately for crisp flow ctl */
2955 if (com->state & CS_CTS_OFLOW) {
2956 if (modem_status & MSR_CTS)
2957 com->state |= CS_ODEVREADY;
2958 else
2959 com->state &= ~CS_ODEVREADY;
2960 }
2961 }
2962#ifdef PC98
2963 }
2964#endif
2965
2966 /* output queued and everything ready? */
2967#ifndef PC98
2968 if (line_status & LSR_TXRDY
2969 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2970#else
2971 if (((com->pc98_if_type == COM_IF_RSA98III)
2972 ? (rsa_buf_status & 0x02)
2973 : (line_status & LSR_TXRDY))
2974 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2975#endif
2976#ifdef PC98
2977 Port_t tmp_data_port;
2978
2979 if (IS_8251(com->pc98_if_type) &&
2980 com->pc98_8251fifo_enable)
2981 tmp_data_port = I8251F_data;
2982 else
2983 tmp_data_port = com->data_port;
2984#endif
2985
2986 ioptr = com->obufq.l_head;
2987 if (com->tx_fifo_size > 1) {
2988 u_int ocount;
2989
2990 ocount = com->obufq.l_tail - ioptr;
2991#ifdef PC98
2992 if (com->pc98_if_type == COM_IF_RSA98III) {
2993 rsa_buf_status = inb(com->rsabase + rsa_srr);
2994 rsa_tx_fifo_size = 1024;
2995 if (!(rsa_buf_status & 0x01))
2996 rsa_tx_fifo_size = 2048;
2997 if (ocount > rsa_tx_fifo_size)
2998 ocount = rsa_tx_fifo_size;
2999 } else
3000#endif
3001 if (ocount > com->tx_fifo_size)
3002 ocount = com->tx_fifo_size;
3003 com->bytes_out += ocount;
3004 do
3005#ifdef PC98
3006 outb(tmp_data_port, *ioptr++);
3007#else
3008 outb(com->data_port, *ioptr++);
3009#endif
3010 while (--ocount != 0);
3011 } else {
3012#ifdef PC98
3013 outb(tmp_data_port, *ioptr++);
3014#else
3015 outb(com->data_port, *ioptr++);
3016#endif
3017 ++com->bytes_out;
3018 }
3019#ifdef PC98
3020 if (IS_8251(com->pc98_if_type))
3021 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG))
3022 com_int_Tx_enable(com);
3023#endif
3024 com->obufq.l_head = ioptr;
3025 if (COM_IIR_TXRDYBUG(com->flags)) {
3026 int_ctl_new = int_ctl | IER_ETXRDY;
3027 }
3028 if (ioptr >= com->obufq.l_tail) {
3029 struct lbq *qp;
3030
3031 qp = com->obufq.l_next;
3032 qp->l_queued = FALSE;
3033 qp = qp->l_next;
3034 if (qp != NULL) {
3035 com->obufq.l_head = qp->l_head;
3036 com->obufq.l_tail = qp->l_tail;
3037 com->obufq.l_next = qp;
3038 } else {
3039 /* output just completed */
3040 if (COM_IIR_TXRDYBUG(com->flags)) {
3041 int_ctl_new = int_ctl & ~IER_ETXRDY;
3042 }
3043 com->state &= ~CS_BUSY;
3044#if defined(PC98)
3045 if (IS_8251(com->pc98_if_type) &&
3046 pc98_check_i8251_interrupt(com) & IEN_TxFLAG)
3047 com_int_Tx_disable(com);
3048#endif
3049 }
3050 if (!(com->state & CS_ODONE)) {
3051 com_events += LOTS_OF_EVENTS;
3052 com->state |= CS_ODONE;
3053 setsofttty(); /* handle at high level ASAP */
3054 }
3055 }
3056 if (COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) {
3057#ifdef PC98
3058 if (com->pc98_if_type == COM_IF_RSA98III) {
3059 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY);
3060 outb(com->intr_ctl_port, int_ctl_new);
3061 outb(com->rsabase + rsa_ier, 0x1d);
3062 } else
3063#endif
3064 outb(com->intr_ctl_port, int_ctl_new);
3065 }
3066 }
3067#ifdef PC98
3068 else if (line_status & LSR_TXRDY) {
3069 if (IS_8251(com->pc98_if_type))
3070 if (pc98_check_i8251_interrupt(com) & IEN_TxFLAG)
3071 com_int_Tx_disable(com);
3072 }
3073 if (IS_8251(com->pc98_if_type)) {
3074 if (com->pc98_8251fifo_enable) {
3075 if ((tmp = inb(I8251F_lsr)) & STS8251F_RxRDY)
3076 goto more_intr;
3077 } else {
3078 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY)
3079 goto more_intr;
3080 }
3081 }
3082#endif
3083
3084 /* finished? */
3085#ifndef COM_MULTIPORT
3086#ifdef PC98
3087 if (IS_8251(com->pc98_if_type))
3088 return;
3089#endif
3090 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND)
3091#endif /* COM_MULTIPORT */
3092 return;
3093 }
3094}
3095
3096static int
3097sioioctl(dev, cmd, data, flag, p)
3098 dev_t dev;
3099 u_long cmd;
3100 caddr_t data;
3101 int flag;
3102 struct proc *p;
3103{
3104 struct com_s *com;
3105 int error;
3106 int mynor;
3107 int s;
3108 struct tty *tp;
3109#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
3110 u_long oldcmd;
3111 struct termios term;
3112#endif
3113
3114 mynor = minor(dev);
3115 com = com_addr(MINOR_TO_UNIT(mynor));
3116 if (com == NULL || com->gone)
3117 return (ENODEV);
3118 if (mynor & CONTROL_MASK) {
3119 struct termios *ct;
3120
3121 switch (mynor & CONTROL_MASK) {
3122 case CONTROL_INIT_STATE:
3123 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in;
3124 break;
3125 case CONTROL_LOCK_STATE:
3126 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in;
3127 break;
3128 default:
3129 return (ENODEV); /* /dev/nodev */
3130 }
3131 switch (cmd) {
3132 case TIOCSETA:
3133 error = suser(p);
3134 if (error != 0)
3135 return (error);
3136 *ct = *(struct termios *)data;
3137 return (0);
3138 case TIOCGETA:
3139 *(struct termios *)data = *ct;
3140 return (0);
3141 case TIOCGETD:
3142 *(int *)data = TTYDISC;
3143 return (0);
3144 case TIOCGWINSZ:
3145 bzero(data, sizeof(struct winsize));
3146 return (0);
3147 default:
3148 return (ENOTTY);
3149 }
3150 }
3151 tp = com->tp;
3152#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
3153 term = tp->t_termios;
3154 oldcmd = cmd;
3155 error = ttsetcompat(tp, &cmd, data, &term);
3156 if (error != 0)
3157 return (error);
3158 if (cmd != oldcmd)
3159 data = (caddr_t)&term;
3160#endif
3161 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) {
3162 int cc;
3163 struct termios *dt = (struct termios *)data;
3164 struct termios *lt = mynor & CALLOUT_MASK
3165 ? &com->lt_out : &com->lt_in;
3166
3167 dt->c_iflag = (tp->t_iflag & lt->c_iflag)
3168 | (dt->c_iflag & ~lt->c_iflag);
3169 dt->c_oflag = (tp->t_oflag & lt->c_oflag)
3170 | (dt->c_oflag & ~lt->c_oflag);
3171 dt->c_cflag = (tp->t_cflag & lt->c_cflag)
3172 | (dt->c_cflag & ~lt->c_cflag);
3173 dt->c_lflag = (tp->t_lflag & lt->c_lflag)
3174 | (dt->c_lflag & ~lt->c_lflag);
3175 for (cc = 0; cc < NCCS; ++cc)
3176 if (lt->c_cc[cc] != 0)
3177 dt->c_cc[cc] = tp->t_cc[cc];
3178 if (lt->c_ispeed != 0)
3179 dt->c_ispeed = tp->t_ispeed;
3180 if (lt->c_ospeed != 0)
3181 dt->c_ospeed = tp->t_ospeed;
3182 }
3183 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
3184 if (error != ENOIOCTL)
3185 return (error);
3186 s = spltty();
3187 error = ttioctl(tp, cmd, data, flag);
3188 disc_optim(tp, &tp->t_termios, com);
3189 if (error != ENOIOCTL) {
3190 splx(s);
3191 return (error);
3192 }
3193#ifdef PC98
3194 if (IS_8251(com->pc98_if_type)) {
3195 switch (cmd) {
3196 case TIOCSBRK:
3197 com_send_break_on(com);
3198 break;
3199 case TIOCCBRK:
3200 com_send_break_off(com);
3201 break;
3202 case TIOCSDTR:
3203 com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS);
3204 break;
3205 case TIOCCDTR:
3206 com_tiocm_bic(com, TIOCM_DTR);
3207 break;
3208 /*
3209 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
3210 * changes get undone on the next call to comparam().
3211 */
3212 case TIOCMSET:
3213 com_tiocm_set(com, *(int *)data);
3214 break;
3215 case TIOCMBIS:
3216 com_tiocm_bis(com, *(int *)data);
3217 break;
3218 case TIOCMBIC:
3219 com_tiocm_bic(com, *(int *)data);
3220 break;
3221 case TIOCMGET:
3222 *(int *)data = com_tiocm_get(com);
3223 break;
3224 case TIOCMSDTRWAIT:
3225 /* must be root since the wait applies to following logins */
3226 error = suser(p);
3227 if (error != 0) {
3228 splx(s);
3229 return (error);
3230 }
3231 com->dtr_wait = *(int *)data * hz / 100;
3232 break;
3233 case TIOCMGDTRWAIT:
3234 *(int *)data = com->dtr_wait * 100 / hz;
3235 break;
3236 case TIOCTIMESTAMP:
3237 com->do_timestamp = TRUE;
3238 *(struct timeval *)data = com->timestamp;
3239 break;
3240 case TIOCDCDTIMESTAMP:
3241 com->do_dcd_timestamp = TRUE;
3242 *(struct timeval *)data = com->dcd_timestamp;
3243 break;
3244 default:
3245 splx(s);
3246 error = pps_ioctl(cmd, data, &com->pps);
3247 if (error == ENODEV)
3248 error = ENOTTY;
3249 return (error);
3250 }
3251 } else {
3252#endif
3253 switch (cmd) {
3254 case TIOCSBRK:
3255 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK);
3256 break;
3257 case TIOCCBRK:
3258 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
3259 break;
3260 case TIOCSDTR:
3261 (void)commctl(com, TIOCM_DTR, DMBIS);
3262 break;
3263 case TIOCCDTR:
3264 (void)commctl(com, TIOCM_DTR, DMBIC);
3265 break;
3266 /*
3267 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
3268 * changes get undone on the next call to comparam().
3269 */
3270 case TIOCMSET:
3271 (void)commctl(com, *(int *)data, DMSET);
3272 break;
3273 case TIOCMBIS:
3274 (void)commctl(com, *(int *)data, DMBIS);
3275 break;
3276 case TIOCMBIC:
3277 (void)commctl(com, *(int *)data, DMBIC);
3278 break;
3279 case TIOCMGET:
3280 *(int *)data = commctl(com, 0, DMGET);
3281 break;
3282 case TIOCMSDTRWAIT:
3283 /* must be root since the wait applies to following logins */
3284 error = suser(p);
3285 if (error != 0) {
3286 splx(s);
3287 return (error);
3288 }
3289 com->dtr_wait = *(int *)data * hz / 100;
3290 break;
3291 case TIOCMGDTRWAIT:
3292 *(int *)data = com->dtr_wait * 100 / hz;
3293 break;
3294 case TIOCTIMESTAMP:
3295 com->do_timestamp = TRUE;
3296 *(struct timeval *)data = com->timestamp;
3297 break;
3298 case TIOCDCDTIMESTAMP:
3299 com->do_dcd_timestamp = TRUE;
3300 *(struct timeval *)data = com->dcd_timestamp;
3301 break;
3302 default:
3303 splx(s);
3304 error = pps_ioctl(cmd, data, &com->pps);
3305 if (error == ENODEV)
3306 error = ENOTTY;
3307 return (error);
3308 }
3309#ifdef PC98
3310 }
3311#endif
3312 splx(s);
3313 return (0);
3314}
3315
3316static void
3317siopoll()
3318{
3319 int unit;
3320
3321 if (com_events == 0)
3322 return;
3323repeat:
3324 for (unit = 0; unit < sio_numunits; ++unit) {
3325 struct com_s *com;
3326 int incc;
3327 struct tty *tp;
3328
3329 com = com_addr(unit);
3330 if (com == NULL)
3331 continue;
3332 tp = com->tp;
3333 if (tp == NULL || com->gone) {
3334 /*
3335 * Discard any events related to never-opened or
3336 * going-away devices.
3337 */
3338 disable_intr();
3339 incc = com->iptr - com->ibuf;
3340 com->iptr = com->ibuf;
3341 if (com->state & CS_CHECKMSR) {
3342 incc += LOTS_OF_EVENTS;
3343 com->state &= ~CS_CHECKMSR;
3344 }
3345 com_events -= incc;
3346 enable_intr();
3347 continue;
3348 }
3349 if (com->iptr != com->ibuf) {
3350 disable_intr();
3351 sioinput(com);
3352 enable_intr();
3353 }
3354 if (com->state & CS_CHECKMSR) {
3355 u_char delta_modem_status;
3356
3357#ifdef PC98
3358 if (!IS_8251(com->pc98_if_type)) {
3359#endif
3360 disable_intr();
3361 delta_modem_status = com->last_modem_status
3362 ^ com->prev_modem_status;
3363 com->prev_modem_status = com->last_modem_status;
3364 com_events -= LOTS_OF_EVENTS;
3365 com->state &= ~CS_CHECKMSR;
3366 enable_intr();
3367 if (delta_modem_status & MSR_DCD)
3368 (*linesw[tp->t_line].l_modem)
3369 (tp, com->prev_modem_status & MSR_DCD);
3370#ifdef PC98
3371 }
3372#endif
3373 }
3374 if (com->state & CS_ODONE) {
3375 disable_intr();
3376 com_events -= LOTS_OF_EVENTS;
3377 com->state &= ~CS_ODONE;
3378 enable_intr();
3379 if (!(com->state & CS_BUSY)
3380 && !(com->extra_state & CSE_BUSYCHECK)) {
3381 timeout(siobusycheck, com, hz / 100);
3382 com->extra_state |= CSE_BUSYCHECK;
3383 }
3384 (*linesw[tp->t_line].l_start)(tp);
3385 }
3386 if (com_events == 0)
3387 break;
3388 }
3389 if (com_events >= LOTS_OF_EVENTS)
3390 goto repeat;
3391}
3392
3393static int
3394comparam(tp, t)
3395 struct tty *tp;
3396 struct termios *t;
3397{
3398 u_int cfcr;
3399 int cflag;
3400 struct com_s *com;
3401 int divisor;
3402 u_char dlbh;
3403 u_char dlbl;
3404 int s;
3405 int unit;
3406#ifdef PC98
3407 u_char param = 0;
3408#endif
3409
3410#ifdef PC98
3411 unit = DEV_TO_UNIT(tp->t_dev);
3412 com = com_addr(unit);
3413
3414 cfcr = 0;
3415 if (IS_8251(com->pc98_if_type)) {
3416 divisor = pc98_ttspeedtab(com, t->c_ospeed);
3417 } else {
3418 /* do historical conversions */
3419 if (t->c_ispeed == 0)
3420 t->c_ispeed = t->c_ospeed;
3421
3422 /* check requested parameters */
3423 divisor = ttspeedtab(t->c_ospeed,
3424 if_16550a_type[com->pc98_if_type & 0x0f].speedtab);
3425 }
3426#else
3427 /* do historical conversions */
3428 if (t->c_ispeed == 0)
3429 t->c_ispeed = t->c_ospeed;
3430
3431 /* check requested parameters */
3432 divisor = ttspeedtab(t->c_ospeed, comspeedtab);
3433#endif
3434 if (divisor < 0 || (divisor > 0 && t->c_ispeed != t->c_ospeed))
3435 return (EINVAL);
3436
3437#ifndef PC98
3438 /* parameters are OK, convert them to the com struct and the device */
3439 unit = DEV_TO_UNIT(tp->t_dev);
3440 com = com_addr(unit);
3441 if (com == NULL)
3442 return (ENODEV);
3443#endif
3444 s = spltty();
3445#ifdef PC98
3446 if (IS_8251(com->pc98_if_type)) {
3447 if (divisor == 0)
3448 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
3449 else
3450 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
3451 } else
3452#endif
3453 if (divisor == 0)
3454 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */
3455 else
3456 (void)commctl(com, TIOCM_DTR, DMBIS);
3457 cflag = t->c_cflag;
3458#ifdef PC98
3459 if (!IS_8251(com->pc98_if_type)) {
3460#endif
3461 switch (cflag & CSIZE) {
3462 case CS5:
3463 cfcr = CFCR_5BITS;
3464 break;
3465 case CS6:
3466 cfcr = CFCR_6BITS;
3467 break;
3468 case CS7:
3469 cfcr = CFCR_7BITS;
3470 break;
3471 default:
3472 cfcr = CFCR_8BITS;
3473 break;
3474 }
3475 if (cflag & PARENB) {
3476 cfcr |= CFCR_PENAB;
3477 if (!(cflag & PARODD))
3478 cfcr |= CFCR_PEVEN;
3479 }
3480 if (cflag & CSTOPB)
3481 cfcr |= CFCR_STOPB;
3482
3483 if (com->hasfifo && divisor != 0) {
3484 /*
3485 * Use a fifo trigger level low enough so that the input
3486 * latency from the fifo is less than about 16 msec and
3487 * the total latency is less than about 30 msec. These
3488 * latencies are reasonable for humans. Serial comms
3489 * protocols shouldn't expect anything better since modem
3490 * latencies are larger.
3491 */
3492 com->fifo_image = t->c_ospeed <= 4800
3493 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH;
3494#ifdef COM_ESP
3495 /*
3496 * The Hayes ESP card needs the fifo DMA mode bit set
3497 * in compatibility mode. If not, it will interrupt
3498 * for each character received.
3499 */
3500 if (com->esp)
3501 com->fifo_image |= FIFO_DMA_MODE;
3502#endif
3503 sio_setreg(com, com_fifo, com->fifo_image);
3504 }
3505#ifdef PC98
3506 }
3507#endif
3508
3509 /*
3510 * This returns with interrupts disabled so that we can complete
3511 * the speed change atomically. Keeping interrupts disabled is
3512 * especially important while com_data is hidden.
3513 */
3514 (void) siosetwater(com, t->c_ispeed);
3515
3516#ifdef PC98
3517 if (IS_8251(com->pc98_if_type))
3518 com_cflag_and_speed_set(com, cflag, t->c_ospeed);
3519 else {
3520#endif
3521 if (divisor != 0) {
3522 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB);
3523 /*
3524 * Only set the divisor registers if they would change,
3525 * since on some 16550 incompatibles (UMC8669F), setting
3526 * them while input is arriving them loses sync until
3527 * data stops arriving.
3528 */
3529 dlbl = divisor & 0xFF;
3530 if (sio_getreg(com, com_dlbl) != dlbl)
3531 sio_setreg(com, com_dlbl, dlbl);
3532 dlbh = (u_int) divisor >> 8;
3533 if (sio_getreg(com, com_dlbh) != dlbh)
3534 sio_setreg(com, com_dlbh, dlbh);
3535 }
3536
3537 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr);
3538#ifdef PC98
3539 }
3540#endif
3541
3542 if (!(tp->t_state & TS_TTSTOP))
3543 com->state |= CS_TTGO;
3544
3545 if (cflag & CRTS_IFLOW) {
3546#ifndef PC98
3547 if (com->st16650a) {
3548 sio_setreg(com, com_cfcr, 0xbf);
3549 sio_setreg(com, com_fifo,
3550 sio_getreg(com, com_fifo) | 0x40);
3551 }
3552#endif
3553 com->state |= CS_RTS_IFLOW;
3554 /*
3555 * If CS_RTS_IFLOW just changed from off to on, the change
3556 * needs to be propagated to MCR_RTS. This isn't urgent,
3557 * so do it later by calling comstart() instead of repeating
3558 * a lot of code from comstart() here.
3559 */
3560 } else if (com->state & CS_RTS_IFLOW) {
3561 com->state &= ~CS_RTS_IFLOW;
3562 /*
3563 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS
3564 * on here, since comstart() won't do it later.
3565 */
3566#ifdef PC98
3567 if (IS_8251(com->pc98_if_type))
3568 com_tiocm_bis(com, TIOCM_RTS);
3569 else
3570 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3571#else
3572 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3573 if (com->st16650a) {
3574 sio_setreg(com, com_cfcr, 0xbf);
3575 sio_setreg(com, com_fifo,
3576 sio_getreg(com, com_fifo) & ~0x40);
3577 }
3578#endif
3579 }
3580
3581
3582 /*
3583 * Set up state to handle output flow control.
3584 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
3585 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
3586 */
3587 com->state |= CS_ODEVREADY;
3588 com->state &= ~CS_CTS_OFLOW;
3589#ifdef PC98
3590 if (com->pc98_if_type == COM_IF_RSA98III) {
3591 param = inb(com->rsabase + rsa_msr);
3592 outb(com->rsabase + rsa_msr, param & 0x14);
3593 }
3594#endif
3595 if (cflag & CCTS_OFLOW) {
3596 com->state |= CS_CTS_OFLOW;
3597#ifdef PC98
3598 if (IS_8251(com->pc98_if_type)) {
3599 if (!(pc98_get_modem_status(com) & TIOCM_CTS))
3600 com->state &= ~CS_ODEVREADY;
3601 } else {
3602 if (com->pc98_if_type == COM_IF_RSA98III) {
3603 /* Set automatic flow control mode */
3604 outb(com->rsabase + rsa_msr, param | 0x08);
3605 } else
3606#endif
3607 if (!(com->last_modem_status & MSR_CTS))
3608 com->state &= ~CS_ODEVREADY;
3609#ifdef PC98
3610 }
3611#else
3612 if (com->st16650a) {
3613 sio_setreg(com, com_cfcr, 0xbf);
3614 sio_setreg(com, com_fifo,
3615 sio_getreg(com, com_fifo) | 0x80);
3616 }
3617 } else {
3618 if (com->st16650a) {
3619 sio_setreg(com, com_cfcr, 0xbf);
3620 sio_setreg(com, com_fifo,
3621 sio_getreg(com, com_fifo) & ~0x80);
3622 }
3623#endif
3624 }
3625
3626#ifdef PC98
3627 if (!IS_8251(com->pc98_if_type))
3628#endif
3629 sio_setreg(com, com_cfcr, com->cfcr_image);
3630
3631 /* XXX shouldn't call functions while intrs are disabled. */
3632 disc_optim(tp, t, com);
3633 /*
3634 * Recover from fiddling with CS_TTGO. We used to call siointr1()
3635 * unconditionally, but that defeated the careful discarding of
3636 * stale input in sioopen().
3637 */
3638 if (com->state >= (CS_BUSY | CS_TTGO))
3639 siointr1(com);
3640
3641 enable_intr();
3642 splx(s);
3643 comstart(tp);
3644 if (com->ibufold != NULL) {
3645 free(com->ibufold, M_DEVBUF);
3646 com->ibufold = NULL;
3647 }
3648 return (0);
3649}
3650
3651static int
3652siosetwater(com, speed)
3653 struct com_s *com;
3654 speed_t speed;
3655{
3656 int cp4ticks;
3657 u_char *ibuf;
3658 int ibufsize;
3659 struct tty *tp;
3660
3661 /*
3662 * Make the buffer size large enough to handle a softtty interrupt
3663 * latency of about 2 ticks without loss of throughput or data
3664 * (about 3 ticks if input flow control is not used or not honoured,
3665 * but a bit less for CS5-CS7 modes).
3666 */
3667 cp4ticks = speed / 10 / hz * 4;
3668 for (ibufsize = 128; ibufsize < cp4ticks;)
3669 ibufsize <<= 1;
3670#ifdef PC98
3671 if (com->pc98_if_type == COM_IF_RSA98III)
3672 ibufsize = 2048;
3673#endif
3674 if (ibufsize == com->ibufsize) {
3675 disable_intr();
3676 return (0);
3677 }
3678
3679 /*
3680 * Allocate input buffer. The extra factor of 2 in the size is
3681 * to allow for an error byte for each input byte.
3682 */
3683 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT);
3684 if (ibuf == NULL) {
3685 disable_intr();
3686 return (ENOMEM);
3687 }
3688
3689 /* Initialize non-critical variables. */
3690 com->ibufold = com->ibuf;
3691 com->ibufsize = ibufsize;
3692 tp = com->tp;
3693 if (tp != NULL) {
3694 tp->t_ififosize = 2 * ibufsize;
3695 tp->t_ispeedwat = (speed_t)-1;
3696 tp->t_ospeedwat = (speed_t)-1;
3697 }
3698
3699 /*
3700 * Read current input buffer, if any. Continue with interrupts
3701 * disabled.
3702 */
3703 disable_intr();
3704 if (com->iptr != com->ibuf)
3705 sioinput(com);
3706
3707 /*-
3708 * Initialize critical variables, including input buffer watermarks.
3709 * The external device is asked to stop sending when the buffer
3710 * exactly reaches high water, or when the high level requests it.
3711 * The high level is notified immediately (rather than at a later
3712 * clock tick) when this watermark is reached.
3713 * The buffer size is chosen so the watermark should almost never
3714 * be reached.
3715 * The low watermark is invisibly 0 since the buffer is always
3716 * emptied all at once.
3717 */
3718 com->iptr = com->ibuf = ibuf;
3719 com->ibufend = ibuf + ibufsize;
3720 com->ierroff = ibufsize;
3721 com->ihighwater = ibuf + 3 * ibufsize / 4;
3722 return (0);
3723}
3724
3725static void
3726comstart(tp)
3727 struct tty *tp;
3728{
3729 struct com_s *com;
3730 int s;
3731 int unit;
3732
3733 unit = DEV_TO_UNIT(tp->t_dev);
3734 com = com_addr(unit);
3735 if (com == NULL)
3736 return;
3737 s = spltty();
3738 disable_intr();
3739 if (tp->t_state & TS_TTSTOP)
3740 com->state &= ~CS_TTGO;
3741 else
3742 com->state |= CS_TTGO;
3743 if (tp->t_state & TS_TBLOCK) {
3744#ifdef PC98
3745 if (IS_8251(com->pc98_if_type)) {
3746 if ((com_tiocm_get(com) & TIOCM_RTS) &&
3747 (com->state & CS_RTS_IFLOW))
3748 com_tiocm_bic(com, TIOCM_RTS);
3749 } else {
3750 if ((com->mcr_image & MCR_RTS) &&
3751 (com->state & CS_RTS_IFLOW))
3752 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
3753 }
3754#else
3755 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW)
3756 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
3757#endif
3758 } else {
3759#ifdef PC98
3760 if (IS_8251(com->pc98_if_type)) {
3761 if (!(com_tiocm_get(com) & TIOCM_RTS) &&
3762 com->iptr < com->ihighwater &&
3763 com->state & CS_RTS_IFLOW)
3764 com_tiocm_bis(com, TIOCM_RTS);
3765 } else {
3766 if (!(com->mcr_image & MCR_RTS) &&
3767 com->iptr < com->ihighwater &&
3768 com->state & CS_RTS_IFLOW)
3769 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3770 }
3771#else
3772 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
3773 && com->state & CS_RTS_IFLOW)
3774 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3775#endif
3776 }
3777 enable_intr();
3778 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
3779 ttwwakeup(tp);
3780 splx(s);
3781 return;
3782 }
3783 if (tp->t_outq.c_cc != 0) {
3784 struct lbq *qp;
3785 struct lbq *next;
3786
3787 if (!com->obufs[0].l_queued) {
3788 com->obufs[0].l_tail
3789 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
3790#ifdef PC98
3791 com->obufsize);
3792#else
3793 sizeof com->obuf1);
3794#endif
3795 com->obufs[0].l_next = NULL;
3796 com->obufs[0].l_queued = TRUE;
3797 disable_intr();
3798 if (com->state & CS_BUSY) {
3799 qp = com->obufq.l_next;
3800 while ((next = qp->l_next) != NULL)
3801 qp = next;
3802 qp->l_next = &com->obufs[0];
3803 } else {
3804 com->obufq.l_head = com->obufs[0].l_head;
3805 com->obufq.l_tail = com->obufs[0].l_tail;
3806 com->obufq.l_next = &com->obufs[0];
3807 com->state |= CS_BUSY;
3808 }
3809 enable_intr();
3810 }
3811 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
3812 com->obufs[1].l_tail
3813 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
3814#ifdef PC98
3815 com->obufsize);
3816#else
3817 sizeof com->obuf2);
3818#endif
3819 com->obufs[1].l_next = NULL;
3820 com->obufs[1].l_queued = TRUE;
3821 disable_intr();
3822 if (com->state & CS_BUSY) {
3823 qp = com->obufq.l_next;
3824 while ((next = qp->l_next) != NULL)
3825 qp = next;
3826 qp->l_next = &com->obufs[1];
3827 } else {
3828 com->obufq.l_head = com->obufs[1].l_head;
3829 com->obufq.l_tail = com->obufs[1].l_tail;
3830 com->obufq.l_next = &com->obufs[1];
3831 com->state |= CS_BUSY;
3832 }
3833 enable_intr();
3834 }
3835 tp->t_state |= TS_BUSY;
3836 }
3837 disable_intr();
3838 if (com->state >= (CS_BUSY | CS_TTGO))
3839 siointr1(com); /* fake interrupt to start output */
3840 enable_intr();
3841 ttwwakeup(tp);
3842 splx(s);
3843}
3844
3845static void
3846comstop(tp, rw)
3847 struct tty *tp;
3848 int rw;
3849{
3850 struct com_s *com;
3851#ifdef PC98
3852 int rsa98_tmp = 0;
3853#endif
3854
3855 com = com_addr(DEV_TO_UNIT(tp->t_dev));
3856 if (com == NULL || com->gone)
3857 return;
3858 disable_intr();
3859 if (rw & FWRITE) {
3860#ifdef PC98
3861 if (!IS_8251(com->pc98_if_type)) {
3862#endif
3863 if (com->hasfifo)
3864#ifdef COM_ESP
3865 /* XXX avoid h/w bug. */
3866 if (!com->esp)
3867#endif
3868 sio_setreg(com, com_fifo,
3869 FIFO_XMT_RST | com->fifo_image);
3870#ifdef PC98
3871 if (com->pc98_if_type == COM_IF_RSA98III)
3872 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3873 sio_setreg(com, com_fifo,
3874 FIFO_XMT_RST | com->fifo_image);
3875 }
3876#endif
3877 com->obufs[0].l_queued = FALSE;
3878 com->obufs[1].l_queued = FALSE;
3879 if (com->state & CS_ODONE)
3880 com_events -= LOTS_OF_EVENTS;
3881 com->state &= ~(CS_ODONE | CS_BUSY);
3882 com->tp->t_state &= ~TS_BUSY;
3883 }
3884 if (rw & FREAD) {
3885#ifdef PC98
3886 if (!IS_8251(com->pc98_if_type)) {
3887 if (com->pc98_if_type == COM_IF_RSA98III)
3888 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3889 sio_getreg(com, com_data);
3890#endif
3891 if (com->hasfifo)
3892#ifdef COM_ESP
3893 /* XXX avoid h/w bug. */
3894 if (!com->esp)
3895#endif
3896 sio_setreg(com, com_fifo,
3897 FIFO_RCV_RST | com->fifo_image);
3898#ifdef PC98
3899 }
3900#endif
3901 com_events -= (com->iptr - com->ibuf);
3902 com->iptr = com->ibuf;
3903 }
3904 enable_intr();
3905 comstart(tp);
3906}
3907
3908static int
3909commctl(com, bits, how)
3910 struct com_s *com;
3911 int bits;
3912 int how;
3913{
3914 int mcr;
3915 int msr;
3916
3917 if (how == DMGET) {
3918 bits = TIOCM_LE; /* XXX - always enabled while open */
3919 mcr = com->mcr_image;
3920 if (mcr & MCR_DTR)
3921 bits |= TIOCM_DTR;
3922 if (mcr & MCR_RTS)
3923 bits |= TIOCM_RTS;
3924 msr = com->prev_modem_status;
3925 if (msr & MSR_CTS)
3926 bits |= TIOCM_CTS;
3927 if (msr & MSR_DCD)
3928 bits |= TIOCM_CD;
3929 if (msr & MSR_DSR)
3930 bits |= TIOCM_DSR;
3931 /*
3932 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI
3933 * more volatile by reading the modem status a lot. Perhaps
3934 * we should latch both bits until the status is read here.
3935 */
3936 if (msr & (MSR_RI | MSR_TERI))
3937 bits |= TIOCM_RI;
3938 return (bits);
3939 }
3940 mcr = 0;
3941 if (bits & TIOCM_DTR)
3942 mcr |= MCR_DTR;
3943 if (bits & TIOCM_RTS)
3944 mcr |= MCR_RTS;
3945 if (com->gone)
3946 return(0);
3947 disable_intr();
3948 switch (how) {
3949 case DMSET:
3950 outb(com->modem_ctl_port,
3951 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE));
3952 break;
3953 case DMBIS:
3954 outb(com->modem_ctl_port, com->mcr_image |= mcr);
3955 break;
3956 case DMBIC:
3957 outb(com->modem_ctl_port, com->mcr_image &= ~mcr);
3958 break;
3959 }
3960 enable_intr();
3961 return (0);
3962}
3963
3964static void
3965siosettimeout()
3966{
3967 struct com_s *com;
3968 bool_t someopen;
3969 int unit;
3970
3971 /*
3972 * Set our timeout period to 1 second if no polled devices are open.
3973 * Otherwise set it to max(1/200, 1/hz).
3974 * Enable timeouts iff some device is open.
3975 */
3976 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3977 sio_timeout = hz;
3978 someopen = FALSE;
3979 for (unit = 0; unit < sio_numunits; ++unit) {
3980 com = com_addr(unit);
3981 if (com != NULL && com->tp != NULL
3982 && com->tp->t_state & TS_ISOPEN && !com->gone) {
3983 someopen = TRUE;
3984 if (com->poll || com->poll_output) {
3985 sio_timeout = hz > 200 ? hz / 200 : 1;
3986 break;
3987 }
3988 }
3989 }
3990 if (someopen) {
3991 sio_timeouts_until_log = hz / sio_timeout;
3992 sio_timeout_handle = timeout(comwakeup, (void *)NULL,
3993 sio_timeout);
3994 } else {
3995 /* Flush error messages, if any. */
3996 sio_timeouts_until_log = 1;
3997 comwakeup((void *)NULL);
3998 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3999 }
4000}
4001
4002static void
4003comwakeup(chan)
4004 void *chan;
4005{
4006 struct com_s *com;
4007 int unit;
4008
4009 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout);
4010
4011 /*
4012 * Recover from lost output interrupts.
4013 * Poll any lines that don't use interrupts.
4014 */
4015 for (unit = 0; unit < sio_numunits; ++unit) {
4016 com = com_addr(unit);
4017 if (com != NULL && !com->gone
4018 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) {
4019 disable_intr();
4020 siointr1(com);
4021 enable_intr();
4022 }
4023 }
4024
4025 /*
4026 * Check for and log errors, but not too often.
4027 */
4028 if (--sio_timeouts_until_log > 0)
4029 return;
4030 sio_timeouts_until_log = hz / sio_timeout;
4031 for (unit = 0; unit < sio_numunits; ++unit) {
4032 int errnum;
4033
4034 com = com_addr(unit);
4035 if (com == NULL)
4036 continue;
4037 if (com->gone)
4038 continue;
4039 for (errnum = 0; errnum < CE_NTYPES; ++errnum) {
4040 u_int delta;
4041 u_long total;
4042
4043 disable_intr();
4044 delta = com->delta_error_counts[errnum];
4045 com->delta_error_counts[errnum] = 0;
4046 enable_intr();
4047 if (delta == 0)
4048 continue;
4049 total = com->error_counts[errnum] += delta;
4050 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n",
4051 unit, delta, error_desc[errnum],
4052 delta == 1 ? "" : "s", total);
4053 }
4054 }
4055}
4056
4057#ifdef PC98
4058/* commint is called when modem control line changes */
4059static void
4060commint(dev_t dev)
4061{
4062 register struct tty *tp;
4063 int stat,delta;
4064 struct com_s *com;
4065 int mynor,unit;
4066
4067 mynor = minor(dev);
4068 unit = MINOR_TO_UNIT(mynor);
4069 com = com_addr(unit);
4070 tp = com->tp;
4071
4072 stat = com_tiocm_get(com);
4073 delta = com_tiocm_get_delta(com);
4074
4075 if (com->state & CS_CTS_OFLOW) {
4076 if (stat & TIOCM_CTS)
4077 com->state |= CS_ODEVREADY;
4078 else
4079 com->state &= ~CS_ODEVREADY;
4080 }
4081 if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) {
4082 if (stat & TIOCM_CAR )
4083 (void)(*linesw[tp->t_line].l_modem)(tp, 1);
4084 else if ((*linesw[tp->t_line].l_modem)(tp, 0) == 0) {
4085 /* negate DTR, RTS */
4086 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ?
4087 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE );
4088 /* disable IENABLE */
4089 com_int_TxRx_disable( com );
4090 }
4091 }
4092}
4093#endif
4094
4095static void
4096disc_optim(tp, t, com)
4097 struct tty *tp;
4098 struct termios *t;
4099 struct com_s *com;
4100{
4101 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
4102 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
4103 && (!(t->c_iflag & PARMRK)
4104 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
4105 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
4106 && linesw[tp->t_line].l_rint == ttyinput)
4107 tp->t_state |= TS_CAN_BYPASS_L_RINT;
4108 else
4109 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
4110 com->hotchar = linesw[tp->t_line].l_hotchar;
4111}
4112
4113/*
4114 * Following are all routines needed for SIO to act as console
4115 */
4116#include <sys/cons.h>
4117
4118struct siocnstate {
4119 u_char dlbl;
4120 u_char dlbh;
4121 u_char ier;
4122 u_char cfcr;
4123 u_char mcr;
4124};
4125
4126static speed_t siocngetspeed __P((Port_t, struct speedtab *));
4127static void siocnclose __P((struct siocnstate *sp, Port_t iobase));
4128static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed));
4129static void siocntxwait __P((Port_t iobase));
4130
4131static cn_probe_t siocnprobe;
4132static cn_init_t siocninit;
4133static cn_checkc_t siocncheckc;
4134static cn_getc_t siocngetc;
4135static cn_putc_t siocnputc;
4136
4137#ifdef __i386__
4138CONS_DRIVER(sio, siocnprobe, siocninit, NULL, siocngetc, siocncheckc,
4139 siocnputc, NULL);
4140#endif
4141
4142/* To get the GDB related variables */
4143#if DDB > 0
4144#include <ddb/ddb.h>
4145#endif
4146
4147static void
4148siocntxwait(iobase)
4149 Port_t iobase;
4150{
4151 int timo;
4152
4153 /*
4154 * Wait for any pending transmission to finish. Required to avoid
4155 * the UART lockup bug when the speed is changed, and for normal
4156 * transmits.
4157 */
4158 timo = 100000;
4159 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
4160 != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
4161 ;
4162}
4163
4164/*
4165 * Read the serial port specified and try to figure out what speed
4166 * it's currently running at. We're assuming the serial port has
4167 * been initialized and is basicly idle. This routine is only intended
4168 * to be run at system startup.
4169 *
4170 * If the value read from the serial port doesn't make sense, return 0.
4171 */
4172
4173static speed_t
4174siocngetspeed(iobase, table)
4175 Port_t iobase;
4176 struct speedtab *table;
4177{
4178 int code;
4179 u_char dlbh;
4180 u_char dlbl;
4181 u_char cfcr;
4182
4183 cfcr = inb(iobase + com_cfcr);
4184 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
4185
4186 dlbl = inb(iobase + com_dlbl);
4187 dlbh = inb(iobase + com_dlbh);
4188
4189 outb(iobase + com_cfcr, cfcr);
4190
4191 code = dlbh << 8 | dlbl;
4192
4193 for (; table->sp_speed != -1; table++)
4194 if (table->sp_code == code)
4195 return (table->sp_speed);
4196
4197 return (0); /* didn't match anything sane */
4198}
4199
4200static void
4201siocnopen(sp, iobase, speed)
4202 struct siocnstate *sp;
4203 Port_t iobase;
4204 int speed;
4205{
4206 int divisor;
4207 u_char dlbh;
4208 u_char dlbl;
4209
4210 /*
4211 * Save all the device control registers except the fifo register
4212 * and set our default ones (cs8 -parenb speed=comdefaultrate).
4213 * We can't save the fifo register since it is read-only.
4214 */
4215 sp->ier = inb(iobase + com_ier);
4216 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */
4217 siocntxwait(iobase);
4218 sp->cfcr = inb(iobase + com_cfcr);
4219 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
4220 sp->dlbl = inb(iobase + com_dlbl);
4221 sp->dlbh = inb(iobase + com_dlbh);
4222 /*
4223 * Only set the divisor registers if they would change, since on
4224 * some 16550 incompatibles (Startech), setting them clears the
4225 * data input register. This also reduces the effects of the
4226 * UMC8669F bug.
4227 */
4228 divisor = ttspeedtab(speed, comspeedtab);
4229 dlbl = divisor & 0xFF;
4230 if (sp->dlbl != dlbl)
4231 outb(iobase + com_dlbl, dlbl);
4232 dlbh = (u_int) divisor >> 8;
4233 if (sp->dlbh != dlbh)
4234 outb(iobase + com_dlbh, dlbh);
4235 outb(iobase + com_cfcr, CFCR_8BITS);
4236 sp->mcr = inb(iobase + com_mcr);
4237 /*
4238 * We don't want interrupts, but must be careful not to "disable"
4239 * them by clearing the MCR_IENABLE bit, since that might cause
4240 * an interrupt by floating the IRQ line.
4241 */
4242 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
4243}
4244
4245static void
4246siocnclose(sp, iobase)
4247 struct siocnstate *sp;
4248 Port_t iobase;
4249{
4250 /*
4251 * Restore the device control registers.
4252 */
4253 siocntxwait(iobase);
4254 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
4255 if (sp->dlbl != inb(iobase + com_dlbl))
4256 outb(iobase + com_dlbl, sp->dlbl);
4257 if (sp->dlbh != inb(iobase + com_dlbh))
4258 outb(iobase + com_dlbh, sp->dlbh);
4259 outb(iobase + com_cfcr, sp->cfcr);
4260 /*
4261 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
4262 */
4263 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
4264 outb(iobase + com_ier, sp->ier);
4265}
4266
4267static void
4268siocnprobe(cp)
4269 struct consdev *cp;
4270{
4271 speed_t boot_speed;
4272 u_char cfcr;
4273 int s, unit;
4274 struct siocnstate sp;
4275
4276 /*
4277 * Find our first enabled console, if any. If it is a high-level
4278 * console device, then initialize it and return successfully.
4279 * If it is a low-level console device, then initialize it and
4280 * return unsuccessfully. It must be initialized in both cases
4281 * for early use by console drivers and debuggers. Initializing
4282 * the hardware is not necessary in all cases, since the i/o
4283 * routines initialize it on the fly, but it is necessary if
4284 * input might arrive while the hardware is switched back to an
4285 * uninitialized state. We can't handle multiple console devices
4286 * yet because our low-level routines don't take a device arg.
4287 * We trust the user to set the console flags properly so that we
4288 * don't need to probe.
4289 */
4290 cp->cn_pri = CN_DEAD;
4291
4292 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */
4293 int flags;
4294 int disabled;
4295 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) {
4296 if (disabled)
4297 continue;
4298 }
4299 if (resource_int_value("sio", unit, "flags", &flags))
4300 continue;
4301 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) {
4302 int port;
4303 Port_t iobase;
4304
4305 if (resource_int_value("sio", unit, "port", &port))
4306 continue;
4307 iobase = port;
4308 s = spltty();
4309 if (boothowto & RB_SERIAL) {
4310 boot_speed = siocngetspeed(iobase, comspeedtab);
4311 if (boot_speed)
4312 comdefaultrate = boot_speed;
4313 }
4314
4315 /*
4316 * Initialize the divisor latch. We can't rely on
4317 * siocnopen() to do this the first time, since it
4318 * avoids writing to the latch if the latch appears
4319 * to have the correct value. Also, if we didn't
4320 * just read the speed from the hardware, then we
4321 * need to set the speed in hardware so that
4322 * switching it later is null.
4323 */
4324 cfcr = inb(iobase + com_cfcr);
4325 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
4326 outb(iobase + com_dlbl,
4327 COMBRD(comdefaultrate) & 0xff);
4328 outb(iobase + com_dlbh,
4329 (u_int) COMBRD(comdefaultrate) >> 8);
4330 outb(iobase + com_cfcr, cfcr);
4331
4332 siocnopen(&sp, iobase, comdefaultrate);
4333
4334 splx(s);
4335 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) {
4336 cp->cn_dev = makedev(CDEV_MAJOR, unit);
4337 cp->cn_pri = COM_FORCECONSOLE(flags)
4338 || boothowto & RB_SERIAL
4339 ? CN_REMOTE : CN_NORMAL;
4340 siocniobase = iobase;
4341 siocnunit = unit;
4342 }
4343 if (COM_DEBUGGER(flags)) {
4344 printf("sio%d: gdb debugging port\n", unit);
4345 siogdbiobase = iobase;
4346 siogdbunit = unit;
4347#if DDB > 0
4348 gdbdev = makedev(CDEV_MAJOR, unit);
4349 gdb_getc = siocngetc;
4350 gdb_putc = siocnputc;
4351#endif
4352 }
4353 }
4354 }
4355#ifdef __i386__
4356#if DDB > 0
4357 /*
4358 * XXX Ugly Compatability.
4359 * If no gdb port has been specified, set it to be the console
4360 * as some configuration files don't specify the gdb port.
4361 */
4362 if (gdbdev == NODEV && (boothowto & RB_GDB)) {
4363 printf("Warning: no GDB port specified. Defaulting to sio%d.\n",
4364 siocnunit);
4365 printf("Set flag 0x80 on desired GDB port in your\n");
4366 printf("configuration file (currently sio only).\n");
4367 siogdbiobase = siocniobase;
4368 siogdbunit = siocnunit;
4369 gdbdev = makedev(CDEV_MAJOR, siocnunit);
4370 gdb_getc = siocngetc;
4371 gdb_putc = siocnputc;
4372 }
4373#endif
4374#endif
4375}
4376
4377#ifdef __alpha__
4378
4379CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL);
4380
4381int
4382siocnattach(port, speed)
4383 int port;
4384 int speed;
4385{
4386 int s;
4387 u_char cfcr;
4388 struct siocnstate sp;
4389
4390 siocniobase = port;
4391 comdefaultrate = speed;
4392 sio_consdev.cn_pri = CN_NORMAL;
4393 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0);
4394
4395 s = spltty();
4396
4397 /*
4398 * Initialize the divisor latch. We can't rely on
4399 * siocnopen() to do this the first time, since it
4400 * avoids writing to the latch if the latch appears
4401 * to have the correct value. Also, if we didn't
4402 * just read the speed from the hardware, then we
4403 * need to set the speed in hardware so that
4404 * switching it later is null.
4405 */
4406 cfcr = inb(siocniobase + com_cfcr);
4407 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr);
4408 outb(siocniobase + com_dlbl,
4409 COMBRD(comdefaultrate) & 0xff);
4410 outb(siocniobase + com_dlbh,
4411 (u_int) COMBRD(comdefaultrate) >> 8);
4412 outb(siocniobase + com_cfcr, cfcr);
4413
4414 siocnopen(&sp, siocniobase, comdefaultrate);
4415 splx(s);
4416
4417 cn_tab = &sio_consdev;
4418 return (0);
4419}
4420
4421int
4422siogdbattach(port, speed)
4423 int port;
4424 int speed;
4425{
4426 int s;
4427 u_char cfcr;
4428 struct siocnstate sp;
4429
4430 siogdbiobase = port;
4431 gdbdefaultrate = speed;
4432
4433 s = spltty();
4434
4435 /*
4436 * Initialize the divisor latch. We can't rely on
4437 * siocnopen() to do this the first time, since it
4438 * avoids writing to the latch if the latch appears
4439 * to have the correct value. Also, if we didn't
4440 * just read the speed from the hardware, then we
4441 * need to set the speed in hardware so that
4442 * switching it later is null.
4443 */
4444 cfcr = inb(siogdbiobase + com_cfcr);
4445 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr);
4446 outb(siogdbiobase + com_dlbl,
4447 COMBRD(gdbdefaultrate) & 0xff);
4448 outb(siogdbiobase + com_dlbh,
4449 (u_int) COMBRD(gdbdefaultrate) >> 8);
4450 outb(siogdbiobase + com_cfcr, cfcr);
4451
4452 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
4453 splx(s);
4454
4455 return (0);
4456}
4457
4458#endif
4459
4460static void
4461siocninit(cp)
4462 struct consdev *cp;
4463{
4464 comconsole = DEV_TO_UNIT(cp->cn_dev);
4465}
4466
4467static int
4468siocncheckc(dev)
4469 dev_t dev;
4470{
4471 int c;
4472 Port_t iobase;
4473 int s;
4474 struct siocnstate sp;
4475
4476 if (minor(dev) == siogdbunit)
4477 iobase = siogdbiobase;
4478 else
4479 iobase = siocniobase;
4480 s = spltty();
4481 siocnopen(&sp, iobase, comdefaultrate);
4482 if (inb(iobase + com_lsr) & LSR_RXRDY)
4483 c = inb(iobase + com_data);
4484 else
4485 c = -1;
4486 siocnclose(&sp, iobase);
4487 splx(s);
4488 return (c);
4489}
4490
4491
4492int
4493siocngetc(dev)
4494 dev_t dev;
4495{
4496 int c;
4497 Port_t iobase;
4498 int s;
4499 struct siocnstate sp;
4500
4501 if (minor(dev) == siogdbunit)
4502 iobase = siogdbiobase;
4503 else
4504 iobase = siocniobase;
4505 s = spltty();
4506 siocnopen(&sp, iobase, comdefaultrate);
4507 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
4508 ;
4509 c = inb(iobase + com_data);
4510 siocnclose(&sp, iobase);
4511 splx(s);
4512 return (c);
4513}
4514
4515void
4516siocnputc(dev, c)
4517 dev_t dev;
4518 int c;
4519{
4520 int s;
4521 struct siocnstate sp;
4522 Port_t iobase;
4523
4524 if (minor(dev) == siogdbunit)
4525 iobase = siogdbiobase;
4526 else
4527 iobase = siocniobase;
4528 s = spltty();
4529 siocnopen(&sp, iobase, comdefaultrate);
4530 siocntxwait(iobase);
4531 outb(iobase + com_data, c);
4532 siocnclose(&sp, iobase);
4533 splx(s);
4534}
4535
4536#ifdef __alpha__
4537int
4538siogdbgetc()
4539{
4540 int c;
4541 Port_t iobase;
4542 int s;
4543 struct siocnstate sp;
4544
4545 iobase = siogdbiobase;
4546 s = spltty();
4547 siocnopen(&sp, iobase, gdbdefaultrate);
4548 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
4549 ;
4550 c = inb(iobase + com_data);
4551 siocnclose(&sp, iobase);
4552 splx(s);
4553 return (c);
4554}
4555
4556void
4557siogdbputc(c)
4558 int c;
4559{
4560 int s;
4561 struct siocnstate sp;
4562
4563 s = spltty();
4564 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
4565 siocntxwait(siogdbiobase);
4566 outb(siogdbiobase + com_data, c);
4567 siocnclose(&sp, siogdbiobase);
4568 splx(s);
4569}
4570#endif
4571
4572DRIVER_MODULE(sio, isa, sio_isa_driver, sio_devclass, 0, 0);
4573#if NCARD > 0
4574DRIVER_MODULE(sio, pccard, sio_pccard_driver, sio_devclass, 0, 0);
4575#endif
4576#if NPCI > 0
4577DRIVER_MODULE(sio, pci, sio_pci_driver, sio_devclass, 0, 0);
4578#endif
4579
4580#ifdef PC98
4581/*
4582 * pc98 local function
4583 */
4584
4585static void
4586com_tiocm_set(struct com_s *com, int msr)
4587{
4588 int s;
4589 int tmp = 0;
4590 int mask = CMD8251_TxEN|CMD8251_RxEN|CMD8251_DTR|CMD8251_RTS;
4591
4592 s=spltty();
4593 com->pc98_prev_modem_status = ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) )
4594 | ( com->pc98_prev_modem_status & ~(TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4595 tmp |= (CMD8251_TxEN|CMD8251_RxEN);
4596 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4597 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4598 pc98_i8251_clear_or_cmd( com, mask, tmp );
4599 splx(s);
4600}
4601
4602static void
4603com_tiocm_bis(struct com_s *com, int msr)
4604{
4605 int s;
4606 int tmp = 0;
4607
4608 s=spltty();
4609 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4610 tmp |= CMD8251_TxEN|CMD8251_RxEN;
4611 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4612 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4613
4614 pc98_i8251_or_cmd( com, tmp );
4615 splx(s);
4616}
4617
4618static void
4619com_tiocm_bic(struct com_s *com, int msr)
4620{
4621 int s;
4622 int tmp = msr;
4623
4624 s=spltty();
4625 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4626 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4627 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4628
4629 pc98_i8251_clear_cmd( com, tmp );
4630 splx(s);
4631}
4632
4633static int
4634com_tiocm_get(struct com_s *com)
4635{
4636 return( com->pc98_prev_modem_status );
4637}
4638
4639static int
4640com_tiocm_get_delta(struct com_s *com)
4641{
4642 int tmp;
4643
4644 tmp = com->pc98_modem_delta;
4645 com->pc98_modem_delta = 0;
4646 return( tmp );
4647}
4648
4649/* convert to TIOCM_?? ( ioctl.h ) */
4650static int
4651pc98_get_modem_status(struct com_s *com)
4652{
4653 register int msr;
4654
4655 msr = com->pc98_prev_modem_status
4656 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
4657 if (com->pc98_8251fifo_enable) {
4658 int stat2;
4659
4660 stat2 = inb(I8251F_msr);
4661 if ( stat2 & CICSCDF_CD ) msr |= TIOCM_CAR;
4662 if ( stat2 & CICSCDF_CI ) msr |= TIOCM_RI;
4663 if ( stat2 & CICSCDF_DR ) msr |= TIOCM_DSR;
4664 if ( stat2 & CICSCDF_CS ) msr |= TIOCM_CTS;
4665#if COM_CARRIER_DETECT_EMULATE
4666 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) {
4667 msr |= TIOCM_CAR;
4668 }
4669#endif
4670 } else {
4671 int stat, stat2;
4672
4673 stat = inb(com->sts_port);
4674 stat2 = inb(com->in_modem_port);
4675 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR;
4676 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI;
4677 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR;
4678 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS;
4679#if COM_CARRIER_DETECT_EMULATE
4680 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) {
4681 msr |= TIOCM_CAR;
4682 }
4683#endif
4684 }
4685 return(msr);
4686}
4687
4688static void
4689pc98_check_msr(void* chan)
4690{
4691 int msr, delta;
4692 int s;
4693 register struct tty *tp;
4694 struct com_s *com;
4695 int mynor;
4696 int unit;
4697 dev_t dev;
4698
4699 dev=(dev_t)chan;
4700 mynor = minor(dev);
4701 unit = MINOR_TO_UNIT(mynor);
4702 com = com_addr(unit);
4703 tp = com->tp;
4704
4705 s = spltty();
4706 msr = pc98_get_modem_status(com);
4707 /* make change flag */
4708 delta = msr ^ com->pc98_prev_modem_status;
4709 if ( delta & TIOCM_CAR ) {
4710 if ( com->modem_car_chg_timer ) {
4711 if ( -- com->modem_car_chg_timer )
4712 msr ^= TIOCM_CAR;
4713 } else {
4714 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ?
4715 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0)
4716 msr ^= TIOCM_CAR;
4717 }
4718 } else
4719 com->modem_car_chg_timer = 0;
4720 delta = ( msr ^ com->pc98_prev_modem_status ) &
4721 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
4722 com->pc98_prev_modem_status = msr;
4723 delta = ( com->pc98_modem_delta |= delta );
4724 splx(s);
4725 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) {
4726 if ( delta ) {
4727 commint(dev);
4728 }
4729 timeout(pc98_check_msr, (caddr_t)dev,
4730 PC98_CHECK_MODEM_INTERVAL);
4731 } else {
4732 com->modem_checking = 0;
4733 }
4734}
4735
4736static void
4737pc98_msrint_start(dev_t dev)
4738{
4739 struct com_s *com;
4740 int mynor;
4741 int unit;
4742 int s = spltty();
4743
4744 mynor = minor(dev);
4745 unit = MINOR_TO_UNIT(mynor);
4746 com = com_addr(unit);
4747 /* modem control line check routine envoke interval is 1/10 sec */
4748 if ( com->modem_checking == 0 ) {
4749 com->pc98_prev_modem_status = pc98_get_modem_status(com);
4750 com->pc98_modem_delta = 0;
4751 timeout(pc98_check_msr, (caddr_t)dev,
4752 PC98_CHECK_MODEM_INTERVAL);
4753 com->modem_checking = 1;
4754 }
4755 splx(s);
4756}
4757
4758static void
4759pc98_disable_i8251_interrupt(struct com_s *com, int mod)
4760{
4761 /* disable interrupt */
4762 register int tmp;
4763
4764 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4765 COM_INT_DISABLE
4766 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4767 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp );
4768 COM_INT_ENABLE
4769}
4770
4771static void
4772pc98_enable_i8251_interrupt(struct com_s *com, int mod)
4773{
4774 register int tmp;
4775
4776 COM_INT_DISABLE
4777 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4778 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp );
4779 COM_INT_ENABLE
4780}
4781
4782static int
4783pc98_check_i8251_interrupt(struct com_s *com)
4784{
4785 return ( com->intr_enable & 0x07 );
4786}
4787
4788static void
4789pc98_i8251_clear_cmd(struct com_s *com, int x)
4790{
4791 int tmp;
4792
4793 COM_INT_DISABLE
4794 tmp = com->pc98_prev_siocmd & ~(x);
4795 if (com->pc98_8251fifo_enable)
4796 outb(I8251F_fcr, 0);
4797 outb(com->cmd_port, tmp);
4798 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4799 if (com->pc98_8251fifo_enable)
4800 outb(I8251F_fcr, CTRL8251F_ENABLE);
4801 COM_INT_ENABLE
4802}
4803
4804static void
4805pc98_i8251_or_cmd(struct com_s *com, int x)
4806{
4807 int tmp;
4808
4809 COM_INT_DISABLE
4810 if (com->pc98_8251fifo_enable)
4811 outb(I8251F_fcr, 0);
4812 tmp = com->pc98_prev_siocmd | (x);
4813 outb(com->cmd_port, tmp);
4814 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4815 if (com->pc98_8251fifo_enable)
4816 outb(I8251F_fcr, CTRL8251F_ENABLE);
4817 COM_INT_ENABLE
4818}
4819
4820static void
4821pc98_i8251_set_cmd(struct com_s *com, int x)
4822{
4823 int tmp;
4824
4825 COM_INT_DISABLE
4826 if (com->pc98_8251fifo_enable)
4827 outb(I8251F_fcr, 0);
4828 tmp = (x);
4829 outb(com->cmd_port, tmp);
4830 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4831 if (com->pc98_8251fifo_enable)
4832 outb(I8251F_fcr, CTRL8251F_ENABLE);
4833 COM_INT_ENABLE
4834}
4835
4836static void
4837pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x)
4838{
4839 int tmp;
4840 COM_INT_DISABLE
4841 if (com->pc98_8251fifo_enable)
4842 outb(I8251F_fcr, 0);
4843 tmp = com->pc98_prev_siocmd & ~(clr);
4844 tmp |= (x);
4845 outb(com->cmd_port, tmp);
4846 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4847 if (com->pc98_8251fifo_enable)
4848 outb(I8251F_fcr, CTRL8251F_ENABLE);
4849 COM_INT_ENABLE
4850}
4851
4852static int
4853pc98_i8251_get_cmd(struct com_s *com)
4854{
4855 return com->pc98_prev_siocmd;
4856}
4857
4858static int
4859pc98_i8251_get_mod(struct com_s *com)
4860{
4861 return com->pc98_prev_siomod;
4862}
4863
4864static void
4865pc98_i8251_reset(struct com_s *com, int mode, int command)
4866{
4867 if (com->pc98_8251fifo_enable)
4868 outb(I8251F_fcr, 0);
4869 outb(com->cmd_port, 0); /* dummy */
4870 DELAY(2);
4871 outb(com->cmd_port, 0); /* dummy */
4872 DELAY(2);
4873 outb(com->cmd_port, 0); /* dummy */
4874 DELAY(2);
4875 outb(com->cmd_port, CMD8251_RESET); /* internal reset */
4876 DELAY(2);
4877 outb(com->cmd_port, mode ); /* mode register */
4878 com->pc98_prev_siomod = mode;
4879 DELAY(2);
4880 pc98_i8251_set_cmd( com, (command|CMD8251_ER) );
4881 DELAY(10);
4882 if (com->pc98_8251fifo_enable)
4883 outb(I8251F_fcr, CTRL8251F_ENABLE |
4884 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST);
4885}
4886
4887static void
4888pc98_check_sysclock(void)
4889{
4890 /* get system clock from port */
4891 if ( pc98_machine_type & M_8M ) {
4892 /* 8 MHz system & H98 */
4893 sysclock = 8;
4894 } else {
4895 /* 5 MHz system */
4896 sysclock = 5;
4897 }
4898}
4899
4900static void
4901com_cflag_and_speed_set( struct com_s *com, int cflag, int speed)
4902{
4903 int cfcr=0, count;
4904 int previnterrupt;
4905
4906 count = pc98_ttspeedtab( com, speed );
4907 if ( count < 0 ) return;
4908
4909 previnterrupt = pc98_check_i8251_interrupt(com);
4910 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx );
4911
4912 switch ( cflag&CSIZE ) {
4913 case CS5:
4914 cfcr = MOD8251_5BITS; break;
4915 case CS6:
4916 cfcr = MOD8251_6BITS; break;
4917 case CS7:
4918 cfcr = MOD8251_7BITS; break;
4919 case CS8:
4920 cfcr = MOD8251_8BITS; break;
4921 }
4922 if ( cflag&PARENB ) {
4923 if ( cflag&PARODD )
4924 cfcr |= MOD8251_PODD;
4925 else
4926 cfcr |= MOD8251_PEVEN;
4927 } else
4928 cfcr |= MOD8251_PDISAB;
4929
4930 if ( cflag&CSTOPB )
4931 cfcr |= MOD8251_STOP2;
4932 else
4933 cfcr |= MOD8251_STOP1;
4934
4935 if ( count & 0x10000 )
4936 cfcr |= MOD8251_CLKX1;
4937 else
4938 cfcr |= MOD8251_CLKX16;
4939
4940 if (epson_machine_id != 0x20) { /* XXX */
4941 int tmp;
4942 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP))
4943 ;
4944 }
4945 /* set baud rate from ospeed */
4946 pc98_set_baud_rate( com, count );
4947
4948 if ( cfcr != pc98_i8251_get_mod(com) )
4949 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) );
4950
4951 pc98_enable_i8251_interrupt( com, previnterrupt );
4952}
4953
4954static int
4955pc98_ttspeedtab(struct com_s *com, int speed)
4956{
4957 int if_type, effect_sp, count = -1, mod;
4958
4959 if_type = com->pc98_if_type & 0x0f;
4960
4961 switch (com->pc98_if_type) {
4962 case COM_IF_INTERNAL:
4963 if (PC98SIO_baud_rate_port(if_type) != -1) {
4964 count = ttspeedtab(speed, if_8251_type[if_type].speedtab);
4965 if (count > 0) {
4966 count |= COM1_EXT_CLOCK;
4967 break;
4968 }
4969 }
4970
4971 /* for *1CLK asynchronous! mode, TEFUTEFU */
4972 mod = (sysclock == 5) ? 2457600 : 1996800;
4973 effect_sp = ttspeedtab( speed, pc98speedtab );
4974 if ( effect_sp < 0 ) /* XXX */
4975 effect_sp = ttspeedtab( (speed - 1), pc98speedtab );
4976 if ( effect_sp <= 0 )
4977 return effect_sp;
4978 if ( effect_sp == speed )
4979 mod /= 16;
4980 if ( mod % effect_sp )
4981 return(-1);
4982 count = mod / effect_sp;
4983 if ( count > 65535 )
4984 return(-1);
4985 if ( effect_sp != speed )
4986 count |= 0x10000;
4987 break;
4988 case COM_IF_PC9861K_1:
4989 case COM_IF_PC9861K_2:
4990 count = 1;
4991 break;
4992 case COM_IF_IND_SS_1:
4993 case COM_IF_IND_SS_2:
4994 case COM_IF_PIO9032B_1:
4995 case COM_IF_PIO9032B_2:
4996 if ( speed == 0 ) return 0;
4997 count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
4998 break;
4999 case COM_IF_B98_01_1:
5000 case COM_IF_B98_01_2:
5001 if ( speed == 0 ) return 0;
5002 count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
5003#ifdef B98_01_OLD
5004 if (count == 0 || count == 1) {
5005 count += 4;
5006 count |= 0x20000; /* x1 mode for 76800 and 153600 */
5007 }
5008#endif
5009 break;
5010 }
5011
5012 return count;
5013}
5014
5015static void
5016pc98_set_baud_rate( struct com_s *com, int count )
5017{
5018 int if_type, io, s;
5019
5020 if_type = com->pc98_if_type & 0x0f;
5021 io = rman_get_start(com->ioportres) & 0xff00;
5022
5023 switch (com->pc98_if_type) {
5024 case COM_IF_INTERNAL:
5025 if (PC98SIO_baud_rate_port(if_type) != -1) {
5026 if (count & COM1_EXT_CLOCK) {
5027 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff);
5028 break;
5029 } else {
5030 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09);
5031 }
5032 }
5033
5034 if ( count < 0 ) {
5035 printf( "[ Illegal count : %d ]", count );
5036 return;
5037 } else if ( count == 0 )
5038 return;
5039 /* set i8253 */
5040 s = splclock();
5041 if (count != 3)
5042 outb( 0x77, 0xb6 );
5043 else
5044 outb( 0x77, 0xb4 );
5045 outb( 0x5f, 0);
5046 outb( 0x75, count & 0xff );
5047 outb( 0x5f, 0);
5048 outb( 0x75, (count >> 8) & 0xff );
5049 splx(s);
5050 break;
5051 case COM_IF_IND_SS_1:
5052 case COM_IF_IND_SS_2:
5053 outb(io | PC98SIO_intr_ctrl_port(if_type), 0);
5054 outb(io | PC98SIO_baud_rate_port(if_type), 0);
5055 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0);
5056 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80);
5057 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff);
5058 break;
5059 case COM_IF_PIO9032B_1:
5060 case COM_IF_PIO9032B_2:
5061 outb(io | PC98SIO_baud_rate_port(if_type), count);
5062 break;
5063 case COM_IF_B98_01_1:
5064 case COM_IF_B98_01_2:
5065 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f);
5066#ifdef B98_01_OLD
5067 /*
5068 * Some old B98_01 board should be controlled
5069 * in different way, but this hasn't been tested yet.
5070 */
5071 outb(io | PC98SIO_func_port(if_type),
5072 (count & 0x20000) ? 0xf0 : 0xf2);
5073#endif
5074 break;
5075 }
5076}
5077static int
5078pc98_check_if_type(device_t dev, struct siodev *iod)
5079{
5080 int irr, io, if_type, tmp;
5081 static short irq_tab[2][8] = {
5082 { 3, 5, 6, 9, 10, 12, 13, -1},
5083 { 3, 10, 12, 13, 5, 6, 9, -1}
5084 };
5085
5086 if_type = iod->if_type & 0x0f;
5087 iod->irq = 0;
5088 io = isa_get_port(dev) & 0xff00;
5089
5090 if (IS_8251(iod->if_type)) {
5091 if (PC98SIO_func_port(if_type) != -1) {
5092 outb(io | PC98SIO_func_port(if_type), 0xf2);
5093 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab);
5094 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1)
5095 outb(io | PC98SIO_baud_rate_port(if_type), tmp);
5096 }
5097
5098 iod->cmd = io | PC98SIO_cmd_port(if_type);
5099 iod->sts = io | PC98SIO_sts_port(if_type);
5100 iod->mod = io | PC98SIO_in_modem_port(if_type);
5101 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type);
5102
5103 if (iod->if_type == COM_IF_INTERNAL) {
5104 iod->irq = 4;
5105
5106 if (pc98_check_8251vfast()) {
5107 PC98SIO_baud_rate_port(if_type) = I8251F_div;
5108 if_8251_type[if_type].speedtab = pc98fast_speedtab;
5109 }
5110 } else {
5111 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask;
5112 if ((isa_get_port(dev) & 0xff) == IO_COM2)
5113 iod->irq = irq_tab[0][tmp];
5114 else
5115 iod->irq = irq_tab[1][tmp];
5116 }
5117 } else {
5118 irr = if_16550a_type[if_type].irr_read;
5119#ifdef COM_MULTIPORT
5120 if (!COM_ISMULTIPORT(device_get_flags(dev)) ||
5121 device_get_unit(dev) == COM_MPMASTER(device_get_flags(dev)))
5122#endif
5123 if (irr != -1) {
5124 tmp = inb(io | irr);
5125 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */
5126 iod->irq = irq_tab[1][tmp >> 3];
5127 else
5128 iod->irq = irq_tab[0][tmp & 0x07];
5129 }
5130 }
5131 if ( iod->irq == -1 ) return -1;
5132
5133 return 0;
5134}
5135static void
5136pc98_set_ioport(struct com_s *com)
5137{
5138 int if_type = com->pc98_if_type & 0x0f;
5139 Port_t io = rman_get_start(com->ioportres) & 0xff00;
5140
5141 pc98_check_sysclock();
5142 com->data_port = io | PC98SIO_data_port(if_type);
5143 com->cmd_port = io | PC98SIO_cmd_port(if_type);
5144 com->sts_port = io | PC98SIO_sts_port(if_type);
5145 com->in_modem_port = io | PC98SIO_in_modem_port(if_type);
5146 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type);
5147}
5148static int
5149pc98_check_8251vfast(void)
5150{
5151 int i;
5152
5153 outb(I8251F_div, 0x8c);
5154 DELAY(10);
5155 for (i = 0; i < 100; i++) {
5156 if ((inb(I8251F_div) & 0x80) != 0) {
5157 i = 0;
5158 break;
5159 }
5160 DELAY(1);
5161 }
5162 outb(I8251F_div, 0);
5163 DELAY(10);
5164 for (; i < 100; i++) {
5165 if ((inb(I8251F_div) & 0x80) == 0)
5166 return 1;
5167 DELAY(1);
5168 }
5169
5170 return 0;
5171}
5172static int
5173pc98_check_8251fifo(void)
5174{
5175 u_char tmp1, tmp2;
5176
5177 tmp1 = inb(I8251F_iir);
5178 DELAY(10);
5179 tmp2 = inb(I8251F_iir);
5180 if (((tmp1 ^ tmp2) & 0x40) != 0 && ((tmp1 | tmp2) & 0x20) == 0)
5181 return 1;
5182
5183 return 0;
5184}
5185#endif /* PC98 defined */
|