| fdcreg.h (16359) | fdcreg.h (18208) |
|---|---|
| 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 24 unchanged lines hidden (view full) --- 33 * from: @(#)fdreg.h 7.1 (Berkeley) 5/9/91 34 * $Id: fdreg.h,v 1.8 1994/09/25 23:37:38 phk Exp $ 35 */ 36 37/* 38 * AT floppy controller registers and bitfields 39 */ 40 | 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 24 unchanged lines hidden (view full) --- 33 * from: @(#)fdreg.h 7.1 (Berkeley) 5/9/91 34 * $Id: fdreg.h,v 1.8 1994/09/25 23:37:38 phk Exp $ 35 */ 36 37/* 38 * AT floppy controller registers and bitfields 39 */ 40 |
| 41#ifdef PC98 | |
| 42/* uses NEC765 controller */ | 41/* uses NEC765 controller */ |
| 43#include <pc98/pc98/ic/nec765.h> | 42#include <i386/isa/ic/nec765.h> |
| 44 | 43 |
| 44#ifdef PC98 45/* registers */ |
|
| 45#define FDSTS 0 /* NEC 765 Main Status Register (R) */ 46#define FDDATA 2 /* NEC 765 Data Register (R/W) */ | 46#define FDSTS 0 /* NEC 765 Main Status Register (R) */ 47#define FDDATA 2 /* NEC 765 Data Register (R/W) */ |
| 47 48/* registers */ | |
| 49#define FDOUT 4 /* Digital Output Register (W) */ 50#define FDO_RST 0x80 /* FDC RESET */ 51#define FDO_FRY 0x40 /* force READY */ 52#define FDO_AIE 0x20 /* Attention Interrupt Enable */ 53#define FDO_DD 0x20 /* FDD Mode Exchange 0:1M 1:640K */ 54#define FDO_DMAE 0x10 /* enable floppy DMA */ 55#define FDO_MTON 0x08 /* MOTOR ON (when EMTON=1)*/ 56#define FDO_TMSK 0x04 /* TIMER MASK */ --- 7 unchanged lines hidden (view full) --- 64#define FDI_FINT0 0x40 /* Interrupt */ 65#define FDI_FINT1 0x80 /* Interrupt */ 66 67#define FDP_EMTON 0x04 /* enable MTON */ 68#define FDP_FDDEXC 0x02 /* FDD Mode Exchange 1:1M 0:640K */ 69#define FDP_PORTEXC 0x01 /* PORT Exchane 1:1M 0:640K */ 70 71#else | 48#define FDOUT 4 /* Digital Output Register (W) */ 49#define FDO_RST 0x80 /* FDC RESET */ 50#define FDO_FRY 0x40 /* force READY */ 51#define FDO_AIE 0x20 /* Attention Interrupt Enable */ 52#define FDO_DD 0x20 /* FDD Mode Exchange 0:1M 1:640K */ 53#define FDO_DMAE 0x10 /* enable floppy DMA */ 54#define FDO_MTON 0x08 /* MOTOR ON (when EMTON=1)*/ 55#define FDO_TMSK 0x04 /* TIMER MASK */ --- 7 unchanged lines hidden (view full) --- 63#define FDI_FINT0 0x40 /* Interrupt */ 64#define FDI_FINT1 0x80 /* Interrupt */ 65 66#define FDP_EMTON 0x04 /* enable MTON */ 67#define FDP_FDDEXC 0x02 /* FDD Mode Exchange 1:1M 0:640K */ 68#define FDP_PORTEXC 0x01 /* PORT Exchane 1:1M 0:640K */ 69 70#else |
| 72 73/* uses NEC765 controller */ 74#include <i386/isa/ic/nec765.h> 75 | |
| 76/* registers */ 77#define FDOUT 2 /* Digital Output Register (W) */ 78#define FDO_FDSEL 0x03 /* floppy device select */ 79#define FDO_FRST 0x04 /* floppy controller reset */ 80#define FDO_FDMAEN 0x08 /* enable floppy DMA and Interrupt */ 81#define FDO_MOEN0 0x10 /* motor enable drive 0 */ 82#define FDO_MOEN1 0x20 /* motor enable drive 1 */ 83#define FDO_MOEN2 0x40 /* motor enable drive 2 */ --- 19 unchanged lines hidden --- | 71/* registers */ 72#define FDOUT 2 /* Digital Output Register (W) */ 73#define FDO_FDSEL 0x03 /* floppy device select */ 74#define FDO_FRST 0x04 /* floppy controller reset */ 75#define FDO_FDMAEN 0x08 /* enable floppy DMA and Interrupt */ 76#define FDO_MOEN0 0x10 /* motor enable drive 0 */ 77#define FDO_MOEN1 0x20 /* motor enable drive 1 */ 78#define FDO_MOEN2 0x40 /* motor enable drive 2 */ --- 19 unchanged lines hidden --- |