| cbus_dma.c (53121) | cbus_dma.c (57973) |
|---|---|
| 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * Redistribution and use in source and binary forms, with or without --- 20 unchanged lines hidden (view full) --- 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 | 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * Redistribution and use in source and binary forms, with or without --- 20 unchanged lines hidden (view full) --- 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 |
| 37 * $FreeBSD: head/sys/pc98/cbus/cbus_dma.c 53121 1999-11-13 14:09:08Z nyan $ | 37 * $FreeBSD: head/sys/pc98/cbus/cbus_dma.c 57973 2000-03-13 10:19:32Z phk $ |
| 38 */ 39 40/* 41 * code to manage AT bus 42 * 43 * 92/08/18 Frank P. MacLachlan (fpm@crash.cts.com): 44 * Fixed uninitialized variable problem and added code to deal 45 * with DMA page boundaries in isa_dmarangecheck(). Fixed word 46 * mode DMA count compution and reorganized DMA setup code in 47 * isa_dmastart() 48 */ 49 50#ifdef PC98 51#include "opt_pc98.h" 52#endif 53 54#include <sys/param.h> 55#include <sys/systm.h> | 38 */ 39 40/* 41 * code to manage AT bus 42 * 43 * 92/08/18 Frank P. MacLachlan (fpm@crash.cts.com): 44 * Fixed uninitialized variable problem and added code to deal 45 * with DMA page boundaries in isa_dmarangecheck(). Fixed word 46 * mode DMA count compution and reorganized DMA setup code in 47 * isa_dmastart() 48 */ 49 50#ifdef PC98 51#include "opt_pc98.h" 52#endif 53 54#include <sys/param.h> 55#include <sys/systm.h> |
| 56#include <sys/buf.h> /* B_READ and B_RAW */ | |
| 57#include <sys/malloc.h> 58#ifdef PC98 59#include <machine/md_var.h> 60#endif 61#include <vm/vm.h> 62#include <vm/vm_param.h> 63#include <vm/pmap.h> 64#ifdef PC98 --- 207 unchanged lines hidden (view full) --- 272 if (isa_dmarangecheck(addr, nbytes, chan)) { 273 if (dma_bouncebuf[chan] == NULL 274 || dma_bouncebufsize[chan] < nbytes) 275 panic("isa_dmastart: bad bounce buffer"); 276 dma_bounced |= (1 << chan); 277 newaddr = dma_bouncebuf[chan]; 278 279 /* copy bounce buffer on write */ | 56#include <sys/malloc.h> 57#ifdef PC98 58#include <machine/md_var.h> 59#endif 60#include <vm/vm.h> 61#include <vm/vm_param.h> 62#include <vm/pmap.h> 63#ifdef PC98 --- 207 unchanged lines hidden (view full) --- 271 if (isa_dmarangecheck(addr, nbytes, chan)) { 272 if (dma_bouncebuf[chan] == NULL 273 || dma_bouncebufsize[chan] < nbytes) 274 panic("isa_dmastart: bad bounce buffer"); 275 dma_bounced |= (1 << chan); 276 newaddr = dma_bouncebuf[chan]; 277 278 /* copy bounce buffer on write */ |
| 280 if (!(flags & B_READ)) | 279 if (!(flags & ISADMA_READ)) |
| 281 bcopy(addr, newaddr, nbytes); 282 addr = newaddr; 283 } 284 285 /* translate to physical */ 286 phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr); 287 | 280 bcopy(addr, newaddr, nbytes); 281 addr = newaddr; 282 } 283 284 /* translate to physical */ 285 phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr); 286 |
| 288 if (flags & B_RAW) { | 287 if (flags & ISADMA_RAW) { |
| 289 dma_auto_mode |= (1 << chan); 290 } else { 291 dma_auto_mode &= ~(1 << chan); 292 } 293 294#ifdef PC98 295 if (need_pre_dma_flush) 296 wbinvd(); /* wbinvd (WB cache flush) */ 297#endif 298 299#ifndef PC98 300 if ((chan & 4) == 0) { 301 /* 302 * Program one of DMA channels 0..3. These are 303 * byte mode channels. 304 */ 305#endif 306 /* set dma channel mode, and reset address ff */ 307 | 288 dma_auto_mode |= (1 << chan); 289 } else { 290 dma_auto_mode &= ~(1 << chan); 291 } 292 293#ifdef PC98 294 if (need_pre_dma_flush) 295 wbinvd(); /* wbinvd (WB cache flush) */ 296#endif 297 298#ifndef PC98 299 if ((chan & 4) == 0) { 300 /* 301 * Program one of DMA channels 0..3. These are 302 * byte mode channels. 303 */ 304#endif 305 /* set dma channel mode, and reset address ff */ 306 |
| 308 /* If B_RAW flag is set, then use autoinitialise mode */ 309 if (flags & B_RAW) { 310 if (flags & B_READ) | 307 /* If ISADMA_RAW flag is set, then use autoinitialise mode */ 308 if (flags & ISADMA_RAW) { 309 if (flags & ISADMA_READ) |
| 311 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan); 312 else 313 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan); 314 } 315 else | 310 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan); 311 else 312 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan); 313 } 314 else |
| 316 if (flags & B_READ) | 315 if (flags & ISADMA_READ) |
| 317 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan); 318 else 319 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan); 320 outb(DMA1_FFC, 0); 321 322 /* send start address */ 323 waport = DMA1_CHN(chan); 324 outb(waport, phys); --- 14 unchanged lines hidden (view full) --- 339#ifndef PC98 340 } else { 341 /* 342 * Program one of DMA channels 4..7. These are 343 * word mode channels. 344 */ 345 /* set dma channel mode, and reset address ff */ 346 | 316 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan); 317 else 318 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan); 319 outb(DMA1_FFC, 0); 320 321 /* send start address */ 322 waport = DMA1_CHN(chan); 323 outb(waport, phys); --- 14 unchanged lines hidden (view full) --- 338#ifndef PC98 339 } else { 340 /* 341 * Program one of DMA channels 4..7. These are 342 * word mode channels. 343 */ 344 /* set dma channel mode, and reset address ff */ 345 |
| 347 /* If B_RAW flag is set, then use autoinitialise mode */ 348 if (flags & B_RAW) { 349 if (flags & B_READ) | 346 /* If ISADMA_RAW flag is set, then use autoinitialise mode */ 347 if (flags & ISADMA_RAW) { 348 if (flags & ISADMA_READ) |
| 350 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3)); 351 else 352 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3)); 353 } 354 else | 349 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3)); 350 else 351 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3)); 352 } 353 else |
| 355 if (flags & B_READ) | 354 if (flags & ISADMA_READ) |
| 356 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3)); 357 else 358 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3)); 359 outb(DMA2_FFC, 0); 360 361 /* send start address */ 362 waport = DMA2_CHN(chan - 4); 363 outb(waport, phys>>1); --- 10 unchanged lines hidden (view full) --- 374 } 375#endif 376} 377 378void 379isa_dmadone(int flags, caddr_t addr, int nbytes, int chan) 380{ 381#ifdef PC98 | 355 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3)); 356 else 357 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3)); 358 outb(DMA2_FFC, 0); 359 360 /* send start address */ 361 waport = DMA2_CHN(chan - 4); 362 outb(waport, phys>>1); --- 10 unchanged lines hidden (view full) --- 373 } 374#endif 375} 376 377void 378isa_dmadone(int flags, caddr_t addr, int nbytes, int chan) 379{ 380#ifdef PC98 |
| 382 if (flags & B_READ) { | 381 if (flags & ISADMA_READ) { |
| 383 /* cache flush only after reading 92/12/9 by A.Kojima */ 384 if (need_post_dma_flush) 385 invd(); 386 } 387#endif 388 389#ifdef DIAGNOSTIC 390 if (chan & ~VALID_DMA_MASK) --- 12 unchanged lines hidden (view full) --- 403 outb(DMA1_SMSK, (chan & 3) | 4); 404#else 405 if ((dma_auto_mode & (1 << chan)) == 0) 406 outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4); 407#endif 408 409 if (dma_bounced & (1 << chan)) { 410 /* copy bounce buffer on read */ | 382 /* cache flush only after reading 92/12/9 by A.Kojima */ 383 if (need_post_dma_flush) 384 invd(); 385 } 386#endif 387 388#ifdef DIAGNOSTIC 389 if (chan & ~VALID_DMA_MASK) --- 12 unchanged lines hidden (view full) --- 402 outb(DMA1_SMSK, (chan & 3) | 4); 403#else 404 if ((dma_auto_mode & (1 << chan)) == 0) 405 outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4); 406#endif 407 408 if (dma_bounced & (1 << chan)) { 409 /* copy bounce buffer on read */ |
| 411 if (flags & B_READ) | 410 if (flags & ISADMA_READ) |
| 412 bcopy(dma_bouncebuf[chan], addr, nbytes); 413 414 dma_bounced &= ~(1 << chan); 415 } 416 dma_busy &= ~(1 << chan); 417} 418 419/* --- 149 unchanged lines hidden --- | 411 bcopy(dma_bouncebuf[chan], addr, nbytes); 412 413 dma_bounced &= ~(1 << chan); 414 } 415 dma_busy &= ~(1 << chan); 416} 417 418/* --- 149 unchanged lines hidden --- |