| sb_machdep.c (223562) | sb_machdep.c (232615) |
|---|---|
| 1/*- 2 * Copyright (c) 2007 Bruce M. Simpson. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2007 Bruce M. Simpson. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> |
| 28__FBSDID("$FreeBSD: head/sys/mips/sibyte/sb_machdep.c 223562 2011-06-26 10:07:48Z kevlo $"); | 28__FBSDID("$FreeBSD: head/sys/mips/sibyte/sb_machdep.c 232615 2012-03-06 19:01:32Z jmallett $"); |
| 29 30#include "opt_ddb.h" 31#include "opt_kdb.h" 32 33#include <sys/param.h> 34#include <sys/conf.h> 35#include <sys/kernel.h> 36#include <sys/systm.h> --- 211 unchanged lines hidden (view full) --- 248 * This means that if get a TLB miss for any address above 0xc0000000 249 * and the SR_KX bit is set then we will end up in the XTLB exception 250 * vector. 251 * 252 * For now work around this by copying the TLB exception handling 253 * code to the XTLB exception vector. 254 */ 255 { | 29 30#include "opt_ddb.h" 31#include "opt_kdb.h" 32 33#include <sys/param.h> 34#include <sys/conf.h> 35#include <sys/kernel.h> 36#include <sys/systm.h> --- 211 unchanged lines hidden (view full) --- 248 * This means that if get a TLB miss for any address above 0xc0000000 249 * and the SR_KX bit is set then we will end up in the XTLB exception 250 * vector. 251 * 252 * For now work around this by copying the TLB exception handling 253 * code to the XTLB exception vector. 254 */ 255 { |
| 256 bcopy(MipsTLBMiss, (void *)MIPS3_XTLB_MISS_EXC_VEC, | 256 bcopy(MipsTLBMiss, (void *)MIPS_XTLB_MISS_EXC_VEC, |
| 257 MipsTLBMissEnd - MipsTLBMiss); 258 259 mips_icache_sync_all(); 260 mips_dcache_wbinv_all(); 261 } 262 263 pmap_bootstrap(); 264 mips_proc0_init(); --- 44 unchanged lines hidden (view full) --- 309 310static void 311kseg0_map_coherent(void) 312{ 313 uint32_t config; 314 const int CFG_K0_COHERENT = 5; 315 316 config = mips_rd_config(); | 257 MipsTLBMissEnd - MipsTLBMiss); 258 259 mips_icache_sync_all(); 260 mips_dcache_wbinv_all(); 261 } 262 263 pmap_bootstrap(); 264 mips_proc0_init(); --- 44 unchanged lines hidden (view full) --- 309 310static void 311kseg0_map_coherent(void) 312{ 313 uint32_t config; 314 const int CFG_K0_COHERENT = 5; 315 316 config = mips_rd_config(); |
| 317 config &= ~MIPS3_CONFIG_K0_MASK; | 317 config &= ~MIPS_CONFIG_K0_MASK; |
| 318 config |= CFG_K0_COHERENT; 319 mips_wr_config(config); 320} 321 322#ifdef SMP 323void 324platform_ipi_send(int cpuid) 325{ --- 133 unchanged lines hidden --- | 318 config |= CFG_K0_COHERENT; 319 mips_wr_config(config); 320} 321 322#ifdef SMP 323void 324platform_ipi_send(int cpuid) 325{ --- 133 unchanged lines hidden --- |