| nae.h (233545) | nae.h (255368) |
|---|---|
| 1/*- 2 * Copyright (c) 2003-2012 Broadcom Corporation 3 * All Rights Reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * --- 11 unchanged lines hidden (view full) --- 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * | 1/*- 2 * Copyright (c) 2003-2012 Broadcom Corporation 3 * All Rights Reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * --- 11 unchanged lines hidden (view full) --- 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * |
| 28 * $FreeBSD: head/sys/mips/nlm/hal/nae.h 233545 2012-03-27 14:05:12Z jchandra $ | 28 * $FreeBSD: head/sys/mips/nlm/hal/nae.h 255368 2013-09-07 18:26:16Z jchandra $ |
| 29 */ 30 31#ifndef __NLM_NAE_H__ 32#define __NLM_NAE_H__ 33 34/** 35* @file_name nae.h 36* @author Netlogic Microsystems --- 431 unchanged lines hidden (view full) --- 468#define XLP8XX_STG2_EH_CREDIT XLP8XX_EH_FIFO_SZ 469#define XLP8XX_STG2_FROUT_CREDIT XLP8XX_FROUT_FIFO_SZ 470#define XLP8XX_STG2_MS_CREDIT XLP8XX_MS_FIFO_SZ 471 472#define MAX_CAL_SLOTS 64 473#define XLP_MAX_PORTS 18 474#define XLP_STORM_MAX_PORTS 8 475 | 29 */ 30 31#ifndef __NLM_NAE_H__ 32#define __NLM_NAE_H__ 33 34/** 35* @file_name nae.h 36* @author Netlogic Microsystems --- 431 unchanged lines hidden (view full) --- 468#define XLP8XX_STG2_EH_CREDIT XLP8XX_EH_FIFO_SZ 469#define XLP8XX_STG2_FROUT_CREDIT XLP8XX_FROUT_FIFO_SZ 470#define XLP8XX_STG2_MS_CREDIT XLP8XX_MS_FIFO_SZ 471 472#define MAX_CAL_SLOTS 64 473#define XLP_MAX_PORTS 18 474#define XLP_STORM_MAX_PORTS 8 475 |
| 476#define MAX_FREE_FIFO_POOL_8XX 20 477#define MAX_FREE_FIFO_POOL_3XX 9 478 |
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| 476#if !defined(LOCORE) && !defined(__ASSEMBLY__) 477 478#define nlm_read_nae_reg(b, r) nlm_read_reg_xkphys(b, r) 479#define nlm_write_nae_reg(b, r, v) nlm_write_reg_xkphys(b, r, v) 480#define nlm_get_nae_pcibase(node) \ 481 nlm_pcicfg_base(XLP_IO_NAE_OFFSET(node)) 482#define nlm_get_nae_regbase(node) \ 483 nlm_xkphys_map_pcibar0(nlm_get_nae_pcibase(node)) --- 5 unchanged lines hidden (view full) --- 489enum XLPNAE_TX_TYPE { 490 P2D_NEOP = 0, 491 P2P, 492 P2D_EOP, 493 MSC 494}; 495 496enum nblock_type { | 479#if !defined(LOCORE) && !defined(__ASSEMBLY__) 480 481#define nlm_read_nae_reg(b, r) nlm_read_reg_xkphys(b, r) 482#define nlm_write_nae_reg(b, r, v) nlm_write_reg_xkphys(b, r, v) 483#define nlm_get_nae_pcibase(node) \ 484 nlm_pcicfg_base(XLP_IO_NAE_OFFSET(node)) 485#define nlm_get_nae_regbase(node) \ 486 nlm_xkphys_map_pcibar0(nlm_get_nae_pcibase(node)) --- 5 unchanged lines hidden (view full) --- 492enum XLPNAE_TX_TYPE { 493 P2D_NEOP = 0, 494 P2P, 495 P2D_EOP, 496 MSC 497}; 498 499enum nblock_type { |
| 500 UNKNOWN = 0, /* DONT MAKE IT NON-ZERO */ |
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| 497 SGMIIC = 1, 498 XAUIC = 2, 499 ILC = 3 500}; 501 502enum nae_interface_type { 503 GMAC_0 = 0, 504 GMAC_1, --- 40 unchanged lines hidden (view full) --- 545static __inline int 546nae_num_context(uint64_t nae_pcibase) 547{ 548 return (nlm_read_reg(nae_pcibase, XLP_PCI_DEVINFO_REG5)); 549} 550 551/* per port config structure */ 552struct nae_port_config { | 501 SGMIIC = 1, 502 XAUIC = 2, 503 ILC = 3 504}; 505 506enum nae_interface_type { 507 GMAC_0 = 0, 508 GMAC_1, --- 40 unchanged lines hidden (view full) --- 549static __inline int 550nae_num_context(uint64_t nae_pcibase) 551{ 552 return (nlm_read_reg(nae_pcibase, XLP_PCI_DEVINFO_REG5)); 553} 554 555/* per port config structure */ 556struct nae_port_config { |
| 557 int node; /* node id (quickread) */ 558 int block; /* network block id (quickread) */ 559 int port; /* port id - among the 18 in XLP */ 560 int type; /* port type - see xlp_gmac_port_types */ 561 int mdio_bus; 562 int phy_addr; |
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| 553 int num_channels; 554 int num_free_descs; 555 int free_desc_sizes; 556 int ucore_mask; 557 int loopback_mode; /* is complex is in loopback? */ 558 uint32_t freein_spill_size; /* Freein spill size for each port */ 559 uint32_t free_fifo_size; /* (512entries x 2desc/entry)1024desc */ 560 uint32_t iface_fifo_size;/* 256 entries x 64B/entry = 16KB */ --- 39 unchanged lines hidden (view full) --- 600int nlm_set_nae_frequency(int, int); 601void nlm_setup_poe_class_config(uint64_t nae_base, int max_poe_classes, 602 int num_contexts, int *poe_cl_tbl); 603void nlm_setup_vfbid_mapping(uint64_t); 604void nlm_setup_flow_crc_poly(uint64_t, uint32_t); 605void nlm_setup_iface_fifo_cfg(uint64_t, int, struct nae_port_config *); 606void nlm_setup_rx_base_config(uint64_t, int, struct nae_port_config *); 607void nlm_setup_rx_buf_config(uint64_t, int, struct nae_port_config *); | 563 int num_channels; 564 int num_free_descs; 565 int free_desc_sizes; 566 int ucore_mask; 567 int loopback_mode; /* is complex is in loopback? */ 568 uint32_t freein_spill_size; /* Freein spill size for each port */ 569 uint32_t free_fifo_size; /* (512entries x 2desc/entry)1024desc */ 570 uint32_t iface_fifo_size;/* 256 entries x 64B/entry = 16KB */ --- 39 unchanged lines hidden (view full) --- 610int nlm_set_nae_frequency(int, int); 611void nlm_setup_poe_class_config(uint64_t nae_base, int max_poe_classes, 612 int num_contexts, int *poe_cl_tbl); 613void nlm_setup_vfbid_mapping(uint64_t); 614void nlm_setup_flow_crc_poly(uint64_t, uint32_t); 615void nlm_setup_iface_fifo_cfg(uint64_t, int, struct nae_port_config *); 616void nlm_setup_rx_base_config(uint64_t, int, struct nae_port_config *); 617void nlm_setup_rx_buf_config(uint64_t, int, struct nae_port_config *); |
| 608void nlm_setup_freein_fifo_cfg(uint64_t, int, struct nae_port_config *); | 618void nlm_setup_freein_fifo_cfg(uint64_t, struct nae_port_config *); |
| 609int nlm_get_flow_mask(int); 610void nlm_program_flow_cfg(uint64_t, int, uint32_t, uint32_t); 611void xlp_ax_nae_lane_reset_txpll(uint64_t, int, int, int); 612void xlp_nae_lane_reset_txpll(uint64_t, int, int, int); 613void xlp_nae_config_lane_gmac(uint64_t, int); 614void config_egress_fifo_carvings(uint64_t, int, int, int, int, 615 struct nae_port_config *); 616void config_egress_fifo_credits(uint64_t, int, int, int, int, --- 30 unchanged lines hidden --- | 619int nlm_get_flow_mask(int); 620void nlm_program_flow_cfg(uint64_t, int, uint32_t, uint32_t); 621void xlp_ax_nae_lane_reset_txpll(uint64_t, int, int, int); 622void xlp_nae_lane_reset_txpll(uint64_t, int, int, int); 623void xlp_nae_config_lane_gmac(uint64_t, int); 624void config_egress_fifo_carvings(uint64_t, int, int, int, int, 625 struct nae_port_config *); 626void config_egress_fifo_credits(uint64_t, int, int, int, int, --- 30 unchanged lines hidden --- |