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board.c (238290) board.c (255368)
1/*-
2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
3 * reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met:
8 *

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23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * NETLOGIC_BSD */
29
30#include <sys/cdefs.h>
1/*-
2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
3 * reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met:
8 *

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23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * NETLOGIC_BSD */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/mips/nlm/board.c 238290 2012-07-09 10:24:45Z jchandra $");
31__FBSDID("$FreeBSD: head/sys/mips/nlm/board.c 255368 2013-09-07 18:26:16Z jchandra $");
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/bus.h>
35#include <sys/kernel.h>
36#include <sys/lock.h>
37#include <sys/mutex.h>
38
39#include <net/ethernet.h>

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275 * 0 2 6 0
276 * 0 3 5 0
277 * 1 0 8 0
278 * 1 1 11 0
279 * 1 2 10 0
280 * 1 3 9 0
281 */
282static void
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/bus.h>
35#include <sys/kernel.h>
36#include <sys/lock.h>
37#include <sys/mutex.h>
38
39#include <net/ethernet.h>

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275 * 0 2 6 0
276 * 0 3 5 0
277 * 1 0 8 0
278 * 1 1 11 0
279 * 1 2 10 0
280 * 1 3 9 0
281 */
282static void
283nlm_board_get_phyaddr(int block, int port, int *mdio, int *phyaddr)
283nlm_board_get_phyaddr(int block, int port, int *phyaddr)
284{
284{
285
286 /* XXXJC: this is a board feature, check for chip not proper */
287 if (nlm_is_xlp3xx() || (nlm_is_xlp8xx() && block == 4))
288 *mdio = 0;
289 else
290 *mdio = 1;
291
292 switch (block) {
293 case 0: switch (port) {
294 case 0: *phyaddr = 4; break;
295 case 1: *phyaddr = 7; break;
296 case 2: *phyaddr = 6; break;
297 case 3: *phyaddr = 5; break;
298 }
299 break;

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372 printf(" Netlogic %s %s [%x]\n", chip, revstr, procid);
373}
374
375/*
376 * All our knowledge of chip and board that cannot be detected by probing
377 * at run-time goes here
378 */
379static int
285 switch (block) {
286 case 0: switch (port) {
287 case 0: *phyaddr = 4; break;
288 case 1: *phyaddr = 7; break;
289 case 2: *phyaddr = 6; break;
290 case 3: *phyaddr = 5; break;
291 }
292 break;

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365 printf(" Netlogic %s %s [%x]\n", chip, revstr, procid);
366}
367
368/*
369 * All our knowledge of chip and board that cannot be detected by probing
370 * at run-time goes here
371 */
372static int
380nlm_setup_xlp_board(void)
373nlm_setup_xlp_board(int node)
381{
382 struct xlp_board_info *boardp;
383 struct xlp_node_info *nodep;
384 struct xlp_nae_ivars *naep;
385 struct xlp_block_ivars *blockp;
386 struct xlp_port_ivars *portp;
387 uint64_t cpldbase, nae_pcibase;
374{
375 struct xlp_board_info *boardp;
376 struct xlp_node_info *nodep;
377 struct xlp_nae_ivars *naep;
378 struct xlp_block_ivars *blockp;
379 struct xlp_port_ivars *portp;
380 uint64_t cpldbase, nae_pcibase;
388 int node, block, port, rv, dbtype, usecpld;
381 int block, port, rv, dbtype, usecpld = 0, evp = 0, svp = 0;
389 uint8_t *b;
390
391 /* start with a clean slate */
392 boardp = &xlp_board_info;
382 uint8_t *b;
383
384 /* start with a clean slate */
385 boardp = &xlp_board_info;
393 memset(boardp, 0, sizeof(xlp_board_info));
394 boardp->nodemask = 0x1; /* only node 0 */
386 if (boardp->nodemask == 0)
387 memset(boardp, 0, sizeof(xlp_board_info));
388 boardp->nodemask |= (1 << node);
395 nlm_print_processor_info();
396
397 b = board_eeprom_buf;
389 nlm_print_processor_info();
390
391 b = board_eeprom_buf;
398 rv = nlm_board_eeprom_read(0, EEPROM_I2CBUS, EEPROM_I2CADDR, 0, b,
392 rv = nlm_board_eeprom_read(node, EEPROM_I2CBUS, EEPROM_I2CADDR, 0, b,
399 EEPROM_SIZE);
400 if (rv == 0) {
401 board_eeprom_set = 1;
402 printf("Board info (EEPROM on i2c@%d at %#X):\n",
403 EEPROM_I2CBUS, EEPROM_I2CADDR);
404 printf(" Model: %7.7s %2.2s\n", &b[16], &b[24]);
405 printf(" Serial #: %3.3s-%2.2s\n", &b[27], &b[31]);
406 printf(" MAC addr: %02x:%02x:%02x:%02x:%02x:%02x\n",
407 b[2], b[3], b[4], b[5], b[6], b[7]);
408 } else
409 printf("Board Info: Error on EEPROM read (i2c@%d %#X).\n",
410 EEPROM_I2CBUS, EEPROM_I2CADDR);
411
393 EEPROM_SIZE);
394 if (rv == 0) {
395 board_eeprom_set = 1;
396 printf("Board info (EEPROM on i2c@%d at %#X):\n",
397 EEPROM_I2CBUS, EEPROM_I2CADDR);
398 printf(" Model: %7.7s %2.2s\n", &b[16], &b[24]);
399 printf(" Serial #: %3.3s-%2.2s\n", &b[27], &b[31]);
400 printf(" MAC addr: %02x:%02x:%02x:%02x:%02x:%02x\n",
401 b[2], b[3], b[4], b[5], b[6], b[7]);
402 } else
403 printf("Board Info: Error on EEPROM read (i2c@%d %#X).\n",
404 EEPROM_I2CBUS, EEPROM_I2CADDR);
405
406 nae_pcibase = nlm_get_nae_pcibase(node);
407 nodep = &boardp->nodes[node];
408 naep = &nodep->nae_ivars;
409 naep->node = node;
412
410
413 /* XXXJC: check for boards with right CPLD, for now
414 * 4xx PCI cards don't have CPLD with daughter
415 * card info */
416 usecpld = !nlm_is_xlp4xx();
411 /* frequency at which network block runs */
412 naep->freq = 500;
417
413
418 for (node = 0; node < XLP_MAX_NODES; node++) {
419 if ((boardp->nodemask & (1 << node)) == 0)
420 continue;
421 nae_pcibase = nlm_get_nae_pcibase(node);
422 nodep = &boardp->nodes[node];
423 naep = &nodep->nae_ivars;
424 naep->node = node;
414 /* CRC16 polynomial used for flow table generation */
415 naep->flow_crc_poly = 0xffff;
416 naep->hw_parser_en = 1;
417 naep->prepad_en = 1;
418 naep->prepad_size = 3; /* size in 16 byte units */
419 naep->ieee_1588_en = 1;
425
420
426 naep->nblocks = nae_num_complex(nae_pcibase);
427 /* 3xx chips lie shamelessly about this */
428 if (nlm_is_xlp3xx())
429 naep->nblocks = naep->nblocks - 1;
430 naep->blockmask = (1 << naep->nblocks) - 1; /* XXXJC: redundant */
431 naep->xauimask = 0x0; /* set this based on daughter card */
432 naep->sgmiimask = 0x0; /* set this based on daughter card */
421 naep->ilmask = 0x0; /* set this based on daughter card */
422 naep->xauimask = 0x0; /* set this based on daughter card */
423 naep->sgmiimask = 0x0; /* set this based on daughter card */
424 naep->nblocks = nae_num_complex(nae_pcibase);
425 if (strncmp(&b[16], "PCIE", 4) == 0) {
426 usecpld = 0; /* XLP PCIe card */
427 /* Broadcom's XLP PCIe card has the following
428 * blocks fixed.
429 * blk 0-XAUI, 1-XAUI, 4-SGMII(one port) */
430 naep->blockmask = 0x13;
431 } else if (strncmp(&b[16], "MB-EVP", 6) == 0) {
432 usecpld = 1; /* XLP non-PCIe card which has CPLD */
433 evp = 1;
434 naep->blockmask = (1 << naep->nblocks) - 1;
435 } else if ((strncmp(&b[16], "MB-S", 4) == 0) ||
436 (strncmp(&b[16], "MB_S", 4) == 0)) {
437 usecpld = 1; /* XLP non-PCIe card which has CPLD */
438 svp = 1;
439 /* 3xx chip reports one block extra which is a bug */
440 naep->nblocks = naep->nblocks - 1;
441 naep->blockmask = (1 << naep->nblocks) - 1;
442 } else {
443 printf("ERROR!!! Board type:%7s didn't match any board"
444 " type we support\n", &b[16]);
445 return (-1);
446 }
447 cpldbase = nlm_board_cpld_base(node, XLP_EVB_CPLD_CHIPSELECT);
433
448
434 /* frequency at which network block runs */
435 naep->freq = 500;
449 /* pretty print network config */
450 printf("Network config");
451 if (usecpld)
452 printf("(from CPLD@%d):\n", XLP_EVB_CPLD_CHIPSELECT);
453 else
454 printf("(defaults):\n");
455 printf(" NAE@%d Blocks: ", node);
456 for (block = 0; block < naep->nblocks; block++) {
457 char *s = "???";
436
458
437 /* CRC16 polynomial used for flow table generation */
438 naep->flow_crc_poly = 0xffff;
439 naep->hw_parser_en = 1;
440 naep->prepad_en = 1;
441 naep->prepad_size = 3; /* size in 16 byte units */
459 if ((naep->blockmask & (1 << block)) == 0)
460 continue;
461 blockp = &naep->block_ivars[block];
462 blockp->block = block;
463 if (usecpld)
464 dbtype = nlm_board_cpld_dboard_type(cpldbase, block);
465 else
466 dbtype = DCARD_XAUI; /* default XAUI */
442
467
443 naep->ieee_1588_en = 1;
444 cpldbase = nlm_board_cpld_base(node, XLP_EVB_CPLD_CHIPSELECT);
468 /* XLP PCIe cards */
469 if ((!evp && !svp) && ((block == 2) || (block == 3)))
470 dbtype = DCARD_NOT_PRSNT;
445
471
446 for (block = 0; block < naep->nblocks; block++) {
447 blockp = &naep->block_ivars[block];
448 blockp->block = block;
449 if (usecpld)
450 dbtype = nlm_board_cpld_dboard_type(cpldbase,
451 block);
472 if (block == 4) {
473 /* management block 4 on 8xx or XLP PCIe */
474 blockp->type = SGMIIC;
475 if (evp)
476 blockp->portmask = 0x3;
452 else
477 else
453 dbtype = DCARD_XAUI; /* default XAUI */
454
455 if (block == 4) {
456 /* management block 4 on 8xx */
478 blockp->portmask = 0x1;
479 naep->sgmiimask |= (1 << block);
480 } else {
481 switch (dbtype) {
482 case DCARD_ILAKEN:
483 blockp->type = ILC;
484 blockp->portmask = 0x1;
485 naep->ilmask |= (1 << block);
486 break;
487 case DCARD_SGMII:
457 blockp->type = SGMIIC;
488 blockp->type = SGMIIC;
458 blockp->portmask = 0x3;
489 blockp->portmask = 0xf;
459 naep->sgmiimask |= (1 << block);
490 naep->sgmiimask |= (1 << block);
460 } else {
461 switch (dbtype) {
462 case DCARD_ILAKEN:
463 blockp->type = ILC;
464 blockp->portmask = 0x1;
465 naep->xauimask |= (1 << block);
466 break;
467 case DCARD_SGMII:
468 blockp->type = SGMIIC;
469 blockp->portmask = 0xf;
470 naep->sgmiimask |= (1 << block);
471 break;
472 case DCARD_XAUI:
473 default:
474 blockp->type = XAUIC;
475 blockp->portmask = 0x1;
476 naep->xauimask |= (1 << block);
477 break;
478 }
491 break;
492 case DCARD_XAUI:
493 blockp->type = XAUIC;
494 blockp->portmask = 0x1;
495 naep->xauimask |= (1 << block);
496 break;
497 default: /* DCARD_NOT_PRSNT */
498 blockp->type = UNKNOWN;
499 blockp->portmask = 0;
500 break;
479 }
501 }
502 }
503 if (blockp->type != UNKNOWN) {
480 for (port = 0; port < PORTS_PER_CMPLX; port++) {
481 if ((blockp->portmask & (1 << port)) == 0)
482 continue;
483 portp = &blockp->port_ivars[port];
484 nlm_board_get_phyaddr(block, port,
504 for (port = 0; port < PORTS_PER_CMPLX; port++) {
505 if ((blockp->portmask & (1 << port)) == 0)
506 continue;
507 portp = &blockp->port_ivars[port];
508 nlm_board_get_phyaddr(block, port,
485 &portp->mdio_bus, &portp->phy_addr);
509 &portp->phy_addr);
510 if (svp || (block == 4))
511 portp->mdio_bus = 0;
512 else
513 portp->mdio_bus = 1;
486 portp->port = port;
487 portp->block = block;
488 portp->node = node;
489 portp->type = blockp->type;
490 nlm_setup_port_defaults(portp);
491 }
492 }
514 portp->port = port;
515 portp->block = block;
516 portp->node = node;
517 portp->type = blockp->type;
518 nlm_setup_port_defaults(portp);
519 }
520 }
493 }
494
495 /* pretty print network config */
496 printf("Network config");
497 if (usecpld)
498 printf("(from CPLD@%d):\n", XLP_EVB_CPLD_CHIPSELECT);
499 else
500 printf("(defaults):\n");
501 for (node = 0; node < XLP_MAX_NODES; node++) {
502 if ((boardp->nodemask & (1 << node)) == 0)
503 continue;
504 nodep = &boardp->nodes[node];
505 naep = &nodep->nae_ivars;
506 printf(" NAE@%d Blocks: ", node);
507 for (block = 0; block < naep->nblocks; block++) {
508 char *s = "???";
509
510 blockp = &naep->block_ivars[block];
511 switch (blockp->type) {
512 case SGMIIC : s = "SGMII"; break;
513 case XAUIC : s = "XAUI"; break;
514 case ILC : s = "IL"; break;
515 }
516 printf(" [%d %s]", block, s);
521 switch (blockp->type) {
522 case SGMIIC : s = "SGMII"; break;
523 case XAUIC : s = "XAUI"; break;
524 case ILC : s = "IL"; break;
517 }
525 }
518 printf("\n");
526 printf(" [%d %s]", block, s);
519 }
527 }
528 printf("\n");
520 return (0);
521}
522
523int nlm_board_info_setup(void)
524{
529 return (0);
530}
531
532int nlm_board_info_setup(void)
533{
525 nlm_setup_xlp_board();
534 if (nlm_setup_xlp_board(0) != 0)
535 return (-1);
526 return (0);
527}
536 return (0);
537}