32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/bus.h> 35#include <sys/kernel.h> 36#include <sys/lock.h> 37#include <sys/mutex.h> 38 39#include <net/ethernet.h> 40 41#include <mips/nlm/hal/mips-extns.h> 42#include <mips/nlm/hal/haldefs.h> 43#include <mips/nlm/hal/iomap.h> 44#include <mips/nlm/hal/fmn.h> 45#include <mips/nlm/hal/pic.h> 46#include <mips/nlm/hal/sys.h> 47#include <mips/nlm/hal/nae.h> 48#include <mips/nlm/hal/uart.h> 49#include <mips/nlm/hal/poe.h> 50 51#include <mips/nlm/xlp.h> 52#include <mips/nlm/board.h> 53#include <mips/nlm/msgring.h> 54 55static uint8_t board_eeprom_buf[EEPROM_SIZE]; 56static int board_eeprom_set; 57 58struct xlp_board_info xlp_board_info; 59 60struct vfbid_tbl { 61 int vfbid; 62 int dest_vc; 63}; 64 65/* XXXJC : this should be derived from msg thread mask */ 66static struct vfbid_tbl nlm_vfbid[] = { 67 /* NULL FBID should map to cpu0 to detect NAE send msg errors */ 68 {127, 0}, /* NAE <-> NAE mappings */ 69 {51, 1019}, {50, 1018}, {49, 1017}, {48, 1016}, 70 {47, 1015}, {46, 1014}, {45, 1013}, {44, 1012}, 71 {43, 1011}, {42, 1010}, {41, 1009}, {40, 1008}, 72 {39, 1007}, {38, 1006}, {37, 1005}, {36, 1004}, 73 {35, 1003}, {34, 1002}, {33, 1001}, {32, 1000}, 74 /* NAE <-> CPU mappings, freeback got to vc 3 of each thread */ 75 {31, 127}, {30, 123}, {29, 119}, {28, 115}, 76 {27, 111}, {26, 107}, {25, 103}, {24, 99}, 77 {23, 95}, {22, 91}, {21, 87}, {20, 83}, 78 {19, 79}, {18, 75}, {17, 71}, {16, 67}, 79 {15, 63}, {14, 59}, {13, 55}, {12, 51}, 80 {11, 47}, {10, 43}, { 9, 39}, { 8, 35}, 81 { 7, 31}, { 6, 27}, { 5, 23}, { 4, 19}, 82 { 3, 15}, { 2, 11}, { 1, 7}, { 0, 3}, 83}; 84 85static struct vfbid_tbl nlm3xx_vfbid[] = { 86 /* NULL FBID should map to cpu0 to detect NAE send msg errors */ 87 {127, 0}, /* NAE <-> NAE mappings */ 88 {39, 503}, {38, 502}, {37, 501}, {36, 500}, 89 {35, 499}, {34, 498}, {33, 497}, {32, 496}, 90 /* NAE <-> CPU mappings, freeback got to vc 3 of each thread */ 91 {31, 127}, {30, 123}, {29, 119}, {28, 115}, 92 {27, 111}, {26, 107}, {25, 103}, {24, 99}, 93 {23, 95}, {22, 91}, {21, 87}, {20, 83}, 94 {19, 79}, {18, 75}, {17, 71}, {16, 67}, 95 {15, 63}, {14, 59}, {13, 55}, {12, 51}, 96 {11, 47}, {10, 43}, { 9, 39}, { 8, 35}, 97 { 7, 31}, { 6, 27}, { 5, 23}, { 4, 19}, 98 { 3, 15}, { 2, 11}, { 1, 7}, { 0, 3}, 99}; 100 101int 102nlm_get_vfbid_mapping(int vfbid) 103{ 104 int i, nentries; 105 struct vfbid_tbl *p; 106 107 if (nlm_is_xlp3xx()) { 108 nentries = sizeof(nlm3xx_vfbid)/sizeof(struct vfbid_tbl); 109 p = nlm3xx_vfbid; 110 } else { 111 nentries = sizeof(nlm_vfbid)/sizeof(struct vfbid_tbl); 112 p = nlm_vfbid; 113 } 114 115 for (i = 0; i < nentries; i++) { 116 if (p[i].vfbid == vfbid) 117 return (p[i].dest_vc); 118 } 119 120 return (-1); 121} 122 123int 124nlm_get_poe_distvec(int vec, uint32_t *distvec) 125{ 126 127 if (vec != 0) 128 return (-1); /* we support just vec 0 */ 129 nlm_calc_poe_distvec(xlp_msg_thread_mask, 0, 0, 0, 130 0x1 << XLPGE_RX_VC, distvec); 131 return (0); 132} 133 134/* 135 * All our knowledge of chip and board that cannot be detected by probing 136 * at run-time goes here 137 */ 138 139void 140xlpge_get_macaddr(uint8_t *macaddr) 141{ 142 143 if (board_eeprom_set == 0) { 144 /* No luck, take some reasonable value */ 145 macaddr[0] = 0x00; macaddr[1] = 0x0f; macaddr[2] = 0x30; 146 macaddr[3] = 0x20; macaddr[4] = 0x0d; macaddr[5] = 0x5b; 147 } else 148 memcpy(macaddr, &board_eeprom_buf[EEPROM_MACADDR_OFFSET], 149 ETHER_ADDR_LEN); 150} 151 152static void 153nlm_setup_port_defaults(struct xlp_port_ivars *p) 154{ 155 p->loopback_mode = 0; 156 p->num_channels = 1; 157 p->free_desc_sizes = 2048; 158 p->vlan_pri_en = 0; 159 p->hw_parser_en = 1; 160 p->ieee1588_userval = 0; 161 p->ieee1588_ptpoff = 0; 162 p->ieee1588_tmr1 = 0; 163 p->ieee1588_tmr2 = 0; 164 p->ieee1588_tmr3 = 0; 165 p->ieee1588_inc_intg = 0; 166 p->ieee1588_inc_den = 1; 167 p->ieee1588_inc_num = 1; 168 169 if (nlm_is_xlp3xx()) { 170 p->stg2_fifo_size = XLP3XX_STG2_FIFO_SZ; 171 p->eh_fifo_size = XLP3XX_EH_FIFO_SZ; 172 p->frout_fifo_size = XLP3XX_FROUT_FIFO_SZ; 173 p->ms_fifo_size = XLP3XX_MS_FIFO_SZ; 174 p->pkt_fifo_size = XLP3XX_PKT_FIFO_SZ; 175 p->pktlen_fifo_size = XLP3XX_PKTLEN_FIFO_SZ; 176 p->max_stg2_offset = XLP3XX_MAX_STG2_OFFSET; 177 p->max_eh_offset = XLP3XX_MAX_EH_OFFSET; 178 p->max_frout_offset = XLP3XX_MAX_FREE_OUT_OFFSET; 179 p->max_ms_offset = XLP3XX_MAX_MS_OFFSET; 180 p->max_pmem_offset = XLP3XX_MAX_PMEM_OFFSET; 181 p->stg1_2_credit = XLP3XX_STG1_2_CREDIT; 182 p->stg2_eh_credit = XLP3XX_STG2_EH_CREDIT; 183 p->stg2_frout_credit = XLP3XX_STG2_FROUT_CREDIT; 184 p->stg2_ms_credit = XLP3XX_STG2_MS_CREDIT; 185 } else { 186 p->stg2_fifo_size = XLP8XX_STG2_FIFO_SZ; 187 p->eh_fifo_size = XLP8XX_EH_FIFO_SZ; 188 p->frout_fifo_size = XLP8XX_FROUT_FIFO_SZ; 189 p->ms_fifo_size = XLP8XX_MS_FIFO_SZ; 190 p->pkt_fifo_size = XLP8XX_PKT_FIFO_SZ; 191 p->pktlen_fifo_size = XLP8XX_PKTLEN_FIFO_SZ; 192 p->max_stg2_offset = XLP8XX_MAX_STG2_OFFSET; 193 p->max_eh_offset = XLP8XX_MAX_EH_OFFSET; 194 p->max_frout_offset = XLP8XX_MAX_FREE_OUT_OFFSET; 195 p->max_ms_offset = XLP8XX_MAX_MS_OFFSET; 196 p->max_pmem_offset = XLP8XX_MAX_PMEM_OFFSET; 197 p->stg1_2_credit = XLP8XX_STG1_2_CREDIT; 198 p->stg2_eh_credit = XLP8XX_STG2_EH_CREDIT; 199 p->stg2_frout_credit = XLP8XX_STG2_FROUT_CREDIT; 200 p->stg2_ms_credit = XLP8XX_STG2_MS_CREDIT; 201 } 202 203 switch (p->type) { 204 case SGMIIC: 205 p->num_free_descs = 52; 206 p->iface_fifo_size = 13; 207 p->rxbuf_size = 128; 208 p->rx_slots_reqd = SGMII_CAL_SLOTS; 209 p->tx_slots_reqd = SGMII_CAL_SLOTS; 210 if (nlm_is_xlp3xx()) 211 p->pseq_fifo_size = 30; 212 else 213 p->pseq_fifo_size = 62; 214 break; 215 case ILC: 216 p->num_free_descs = 150; 217 p->rxbuf_size = 944; 218 p->rx_slots_reqd = IL8_CAL_SLOTS; 219 p->tx_slots_reqd = IL8_CAL_SLOTS; 220 p->pseq_fifo_size = 225; 221 p->iface_fifo_size = 55; 222 break; 223 case XAUIC: 224 default: 225 p->num_free_descs = 150; 226 p->rxbuf_size = 944; 227 p->rx_slots_reqd = XAUI_CAL_SLOTS; 228 p->tx_slots_reqd = XAUI_CAL_SLOTS; 229 if (nlm_is_xlp3xx()) { 230 p->pseq_fifo_size = 120; 231 p->iface_fifo_size = 52; 232 } else { 233 p->pseq_fifo_size = 225; 234 p->iface_fifo_size = 55; 235 } 236 break; 237 } 238} 239 240/* XLP 8XX evaluation boards have the following phy-addr 241 * assignment. There are two external mdio buses in XLP -- 242 * bus 0 and bus 1. The management ports (16 and 17) are 243 * on mdio bus 0 while blocks/complexes[0 to 3] are all 244 * on mdio bus 1. The phy_addr on bus 0 (mgmt ports 16 245 * and 17) match the port numbers. 246 * These are the details: 247 * block port phy_addr mdio_bus 248 * ==================================== 249 * 0 0 4 1 250 * 0 1 7 1 251 * 0 2 6 1 252 * 0 3 5 1 253 * 1 0 8 1 254 * 1 1 11 1 255 * 1 2 10 1 256 * 1 3 9 1 257 * 2 0 0 1 258 * 2 1 3 1 259 * 2 2 2 1 260 * 2 3 1 1 261 * 3 0 12 1 262 * 3 1 15 1 263 * 3 2 14 1 264 * 3 3 13 1 265 * 266 * 4 0 16 0 267 * 4 1 17 0 268 * 269 * The XLP 3XX evaluation boards have the following phy-addr 270 * assignments. 271 * block port phy_addr mdio_bus 272 * ==================================== 273 * 0 0 4 0 274 * 0 1 7 0 275 * 0 2 6 0 276 * 0 3 5 0 277 * 1 0 8 0 278 * 1 1 11 0 279 * 1 2 10 0 280 * 1 3 9 0 281 */ 282static void
| 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/bus.h> 35#include <sys/kernel.h> 36#include <sys/lock.h> 37#include <sys/mutex.h> 38 39#include <net/ethernet.h> 40 41#include <mips/nlm/hal/mips-extns.h> 42#include <mips/nlm/hal/haldefs.h> 43#include <mips/nlm/hal/iomap.h> 44#include <mips/nlm/hal/fmn.h> 45#include <mips/nlm/hal/pic.h> 46#include <mips/nlm/hal/sys.h> 47#include <mips/nlm/hal/nae.h> 48#include <mips/nlm/hal/uart.h> 49#include <mips/nlm/hal/poe.h> 50 51#include <mips/nlm/xlp.h> 52#include <mips/nlm/board.h> 53#include <mips/nlm/msgring.h> 54 55static uint8_t board_eeprom_buf[EEPROM_SIZE]; 56static int board_eeprom_set; 57 58struct xlp_board_info xlp_board_info; 59 60struct vfbid_tbl { 61 int vfbid; 62 int dest_vc; 63}; 64 65/* XXXJC : this should be derived from msg thread mask */ 66static struct vfbid_tbl nlm_vfbid[] = { 67 /* NULL FBID should map to cpu0 to detect NAE send msg errors */ 68 {127, 0}, /* NAE <-> NAE mappings */ 69 {51, 1019}, {50, 1018}, {49, 1017}, {48, 1016}, 70 {47, 1015}, {46, 1014}, {45, 1013}, {44, 1012}, 71 {43, 1011}, {42, 1010}, {41, 1009}, {40, 1008}, 72 {39, 1007}, {38, 1006}, {37, 1005}, {36, 1004}, 73 {35, 1003}, {34, 1002}, {33, 1001}, {32, 1000}, 74 /* NAE <-> CPU mappings, freeback got to vc 3 of each thread */ 75 {31, 127}, {30, 123}, {29, 119}, {28, 115}, 76 {27, 111}, {26, 107}, {25, 103}, {24, 99}, 77 {23, 95}, {22, 91}, {21, 87}, {20, 83}, 78 {19, 79}, {18, 75}, {17, 71}, {16, 67}, 79 {15, 63}, {14, 59}, {13, 55}, {12, 51}, 80 {11, 47}, {10, 43}, { 9, 39}, { 8, 35}, 81 { 7, 31}, { 6, 27}, { 5, 23}, { 4, 19}, 82 { 3, 15}, { 2, 11}, { 1, 7}, { 0, 3}, 83}; 84 85static struct vfbid_tbl nlm3xx_vfbid[] = { 86 /* NULL FBID should map to cpu0 to detect NAE send msg errors */ 87 {127, 0}, /* NAE <-> NAE mappings */ 88 {39, 503}, {38, 502}, {37, 501}, {36, 500}, 89 {35, 499}, {34, 498}, {33, 497}, {32, 496}, 90 /* NAE <-> CPU mappings, freeback got to vc 3 of each thread */ 91 {31, 127}, {30, 123}, {29, 119}, {28, 115}, 92 {27, 111}, {26, 107}, {25, 103}, {24, 99}, 93 {23, 95}, {22, 91}, {21, 87}, {20, 83}, 94 {19, 79}, {18, 75}, {17, 71}, {16, 67}, 95 {15, 63}, {14, 59}, {13, 55}, {12, 51}, 96 {11, 47}, {10, 43}, { 9, 39}, { 8, 35}, 97 { 7, 31}, { 6, 27}, { 5, 23}, { 4, 19}, 98 { 3, 15}, { 2, 11}, { 1, 7}, { 0, 3}, 99}; 100 101int 102nlm_get_vfbid_mapping(int vfbid) 103{ 104 int i, nentries; 105 struct vfbid_tbl *p; 106 107 if (nlm_is_xlp3xx()) { 108 nentries = sizeof(nlm3xx_vfbid)/sizeof(struct vfbid_tbl); 109 p = nlm3xx_vfbid; 110 } else { 111 nentries = sizeof(nlm_vfbid)/sizeof(struct vfbid_tbl); 112 p = nlm_vfbid; 113 } 114 115 for (i = 0; i < nentries; i++) { 116 if (p[i].vfbid == vfbid) 117 return (p[i].dest_vc); 118 } 119 120 return (-1); 121} 122 123int 124nlm_get_poe_distvec(int vec, uint32_t *distvec) 125{ 126 127 if (vec != 0) 128 return (-1); /* we support just vec 0 */ 129 nlm_calc_poe_distvec(xlp_msg_thread_mask, 0, 0, 0, 130 0x1 << XLPGE_RX_VC, distvec); 131 return (0); 132} 133 134/* 135 * All our knowledge of chip and board that cannot be detected by probing 136 * at run-time goes here 137 */ 138 139void 140xlpge_get_macaddr(uint8_t *macaddr) 141{ 142 143 if (board_eeprom_set == 0) { 144 /* No luck, take some reasonable value */ 145 macaddr[0] = 0x00; macaddr[1] = 0x0f; macaddr[2] = 0x30; 146 macaddr[3] = 0x20; macaddr[4] = 0x0d; macaddr[5] = 0x5b; 147 } else 148 memcpy(macaddr, &board_eeprom_buf[EEPROM_MACADDR_OFFSET], 149 ETHER_ADDR_LEN); 150} 151 152static void 153nlm_setup_port_defaults(struct xlp_port_ivars *p) 154{ 155 p->loopback_mode = 0; 156 p->num_channels = 1; 157 p->free_desc_sizes = 2048; 158 p->vlan_pri_en = 0; 159 p->hw_parser_en = 1; 160 p->ieee1588_userval = 0; 161 p->ieee1588_ptpoff = 0; 162 p->ieee1588_tmr1 = 0; 163 p->ieee1588_tmr2 = 0; 164 p->ieee1588_tmr3 = 0; 165 p->ieee1588_inc_intg = 0; 166 p->ieee1588_inc_den = 1; 167 p->ieee1588_inc_num = 1; 168 169 if (nlm_is_xlp3xx()) { 170 p->stg2_fifo_size = XLP3XX_STG2_FIFO_SZ; 171 p->eh_fifo_size = XLP3XX_EH_FIFO_SZ; 172 p->frout_fifo_size = XLP3XX_FROUT_FIFO_SZ; 173 p->ms_fifo_size = XLP3XX_MS_FIFO_SZ; 174 p->pkt_fifo_size = XLP3XX_PKT_FIFO_SZ; 175 p->pktlen_fifo_size = XLP3XX_PKTLEN_FIFO_SZ; 176 p->max_stg2_offset = XLP3XX_MAX_STG2_OFFSET; 177 p->max_eh_offset = XLP3XX_MAX_EH_OFFSET; 178 p->max_frout_offset = XLP3XX_MAX_FREE_OUT_OFFSET; 179 p->max_ms_offset = XLP3XX_MAX_MS_OFFSET; 180 p->max_pmem_offset = XLP3XX_MAX_PMEM_OFFSET; 181 p->stg1_2_credit = XLP3XX_STG1_2_CREDIT; 182 p->stg2_eh_credit = XLP3XX_STG2_EH_CREDIT; 183 p->stg2_frout_credit = XLP3XX_STG2_FROUT_CREDIT; 184 p->stg2_ms_credit = XLP3XX_STG2_MS_CREDIT; 185 } else { 186 p->stg2_fifo_size = XLP8XX_STG2_FIFO_SZ; 187 p->eh_fifo_size = XLP8XX_EH_FIFO_SZ; 188 p->frout_fifo_size = XLP8XX_FROUT_FIFO_SZ; 189 p->ms_fifo_size = XLP8XX_MS_FIFO_SZ; 190 p->pkt_fifo_size = XLP8XX_PKT_FIFO_SZ; 191 p->pktlen_fifo_size = XLP8XX_PKTLEN_FIFO_SZ; 192 p->max_stg2_offset = XLP8XX_MAX_STG2_OFFSET; 193 p->max_eh_offset = XLP8XX_MAX_EH_OFFSET; 194 p->max_frout_offset = XLP8XX_MAX_FREE_OUT_OFFSET; 195 p->max_ms_offset = XLP8XX_MAX_MS_OFFSET; 196 p->max_pmem_offset = XLP8XX_MAX_PMEM_OFFSET; 197 p->stg1_2_credit = XLP8XX_STG1_2_CREDIT; 198 p->stg2_eh_credit = XLP8XX_STG2_EH_CREDIT; 199 p->stg2_frout_credit = XLP8XX_STG2_FROUT_CREDIT; 200 p->stg2_ms_credit = XLP8XX_STG2_MS_CREDIT; 201 } 202 203 switch (p->type) { 204 case SGMIIC: 205 p->num_free_descs = 52; 206 p->iface_fifo_size = 13; 207 p->rxbuf_size = 128; 208 p->rx_slots_reqd = SGMII_CAL_SLOTS; 209 p->tx_slots_reqd = SGMII_CAL_SLOTS; 210 if (nlm_is_xlp3xx()) 211 p->pseq_fifo_size = 30; 212 else 213 p->pseq_fifo_size = 62; 214 break; 215 case ILC: 216 p->num_free_descs = 150; 217 p->rxbuf_size = 944; 218 p->rx_slots_reqd = IL8_CAL_SLOTS; 219 p->tx_slots_reqd = IL8_CAL_SLOTS; 220 p->pseq_fifo_size = 225; 221 p->iface_fifo_size = 55; 222 break; 223 case XAUIC: 224 default: 225 p->num_free_descs = 150; 226 p->rxbuf_size = 944; 227 p->rx_slots_reqd = XAUI_CAL_SLOTS; 228 p->tx_slots_reqd = XAUI_CAL_SLOTS; 229 if (nlm_is_xlp3xx()) { 230 p->pseq_fifo_size = 120; 231 p->iface_fifo_size = 52; 232 } else { 233 p->pseq_fifo_size = 225; 234 p->iface_fifo_size = 55; 235 } 236 break; 237 } 238} 239 240/* XLP 8XX evaluation boards have the following phy-addr 241 * assignment. There are two external mdio buses in XLP -- 242 * bus 0 and bus 1. The management ports (16 and 17) are 243 * on mdio bus 0 while blocks/complexes[0 to 3] are all 244 * on mdio bus 1. The phy_addr on bus 0 (mgmt ports 16 245 * and 17) match the port numbers. 246 * These are the details: 247 * block port phy_addr mdio_bus 248 * ==================================== 249 * 0 0 4 1 250 * 0 1 7 1 251 * 0 2 6 1 252 * 0 3 5 1 253 * 1 0 8 1 254 * 1 1 11 1 255 * 1 2 10 1 256 * 1 3 9 1 257 * 2 0 0 1 258 * 2 1 3 1 259 * 2 2 2 1 260 * 2 3 1 1 261 * 3 0 12 1 262 * 3 1 15 1 263 * 3 2 14 1 264 * 3 3 13 1 265 * 266 * 4 0 16 0 267 * 4 1 17 0 268 * 269 * The XLP 3XX evaluation boards have the following phy-addr 270 * assignments. 271 * block port phy_addr mdio_bus 272 * ==================================== 273 * 0 0 4 0 274 * 0 1 7 0 275 * 0 2 6 0 276 * 0 3 5 0 277 * 1 0 8 0 278 * 1 1 11 0 279 * 1 2 10 0 280 * 1 3 9 0 281 */ 282static void
|