| cpu.c (256281) | cpu.c (257528) |
|---|---|
| 1/*- 2 * Copyright (c) 2004 Juli Mallett. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. --- 11 unchanged lines hidden (view full) --- 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 */ 26 27#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2004 Juli Mallett. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. --- 11 unchanged lines hidden (view full) --- 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 */ 26 27#include <sys/cdefs.h> |
| 28__FBSDID("$FreeBSD: stable/10/sys/mips/mips/cpu.c 232896 2012-03-12 21:25:32Z jmallett $"); | 28__FBSDID("$FreeBSD: stable/10/sys/mips/mips/cpu.c 257528 2013-11-01 21:17:45Z brooks $"); |
| 29 30#include <sys/param.h> 31#include <sys/kernel.h> 32#include <sys/module.h> 33#include <sys/stdint.h> 34 35#include <sys/bus.h> 36#include <sys/rman.h> --- 57 unchanged lines hidden (view full) --- 94 cpuinfo->icache_virtual = cfg0 & MIPS_CONFIG0_VI; 95 96 /* If config register selection 1 does not exist, exit. */ 97 if (!(cfg0 & MIPS_CONFIG_CM)) 98 return; 99 100 /* Learn TLB size and L1 cache geometry. */ 101 cfg1 = mips_rd_config1(); | 29 30#include <sys/param.h> 31#include <sys/kernel.h> 32#include <sys/module.h> 33#include <sys/stdint.h> 34 35#include <sys/bus.h> 36#include <sys/rman.h> --- 57 unchanged lines hidden (view full) --- 94 cpuinfo->icache_virtual = cfg0 & MIPS_CONFIG0_VI; 95 96 /* If config register selection 1 does not exist, exit. */ 97 if (!(cfg0 & MIPS_CONFIG_CM)) 98 return; 99 100 /* Learn TLB size and L1 cache geometry. */ 101 cfg1 = mips_rd_config1(); |
| 102#ifndef CPU_NLM 103 cpuinfo->tlb_nentries = 104 ((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1; 105#else | 102 103#if defined(CPU_NLM) |
| 106 /* Account for Extended TLB entries in XLP */ 107 tmp = mips_rd_config6(); 108 cpuinfo->tlb_nentries = ((tmp >> 16) & 0xffff) + 1; | 104 /* Account for Extended TLB entries in XLP */ 105 tmp = mips_rd_config6(); 106 cpuinfo->tlb_nentries = ((tmp >> 16) & 0xffff) + 1; |
| 107#elif defined(BERI_LARGE_TLB) 108 /* Check if we support extended TLB entries and if so activate. */ 109 tmp = mips_rd_config5(); 110#define BERI_CP5_LTLB_SUPPORTED 0x1 111 if (tmp & BERI_CP5_LTLB_SUPPORTED) { 112 /* See how many extra TLB entries we have. */ 113 tmp = mips_rd_config6(); 114 cpuinfo->tlb_nentries = (tmp >> 16) + 1; 115 /* Activate the extended entries. */ 116 mips_wr_config6(tmp|0x4); 117 } else |
|
| 109#endif | 118#endif |
| 110 111 /* Add extended TLB size information from config4. */ | 119#if !defined(CPU_NLM) 120 cpuinfo->tlb_nentries = 121 ((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1; 122#endif |
| 112#if defined(CPU_CNMIPS) | 123#if defined(CPU_CNMIPS) |
| 124 /* Add extended TLB size information from config4. */ |
|
| 113 cfg4 = mips_rd_config4(); 114 if ((cfg4 & MIPS_CONFIG4_MMUEXTDEF) == MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT) 115 cpuinfo->tlb_nentries += (cfg4 & MIPS_CONFIG4_MMUSIZEEXT) * 0x40; 116#endif 117 118 /* L1 instruction cache. */ 119 tmp = (cfg1 & MIPS_CONFIG1_IL_MASK) >> MIPS_CONFIG1_IL_SHIFT; 120 if (tmp != 0) { 121 cpuinfo->l1.ic_linesize = 1 << (tmp + 1); 122 cpuinfo->l1.ic_nways = (((cfg1 & MIPS_CONFIG1_IA_MASK) >> MIPS_CONFIG1_IA_SHIFT)) + 1; 123 cpuinfo->l1.ic_nsets = 124 1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >> MIPS_CONFIG1_IS_SHIFT) + 6); 125 } 126 | 125 cfg4 = mips_rd_config4(); 126 if ((cfg4 & MIPS_CONFIG4_MMUEXTDEF) == MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT) 127 cpuinfo->tlb_nentries += (cfg4 & MIPS_CONFIG4_MMUSIZEEXT) * 0x40; 128#endif 129 130 /* L1 instruction cache. */ 131 tmp = (cfg1 & MIPS_CONFIG1_IL_MASK) >> MIPS_CONFIG1_IL_SHIFT; 132 if (tmp != 0) { 133 cpuinfo->l1.ic_linesize = 1 << (tmp + 1); 134 cpuinfo->l1.ic_nways = (((cfg1 & MIPS_CONFIG1_IA_MASK) >> MIPS_CONFIG1_IA_SHIFT)) + 1; 135 cpuinfo->l1.ic_nsets = 136 1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >> MIPS_CONFIG1_IS_SHIFT) + 6); 137 } 138 |
| 127#ifndef CPU_CNMIPS | |
| 128 /* L1 data cache. */ | 139 /* L1 data cache. */ |
| 140#ifndef CPU_CNMIPS |
|
| 129 tmp = (cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT; 130 if (tmp != 0) { 131 cpuinfo->l1.dc_linesize = 1 << (tmp + 1); 132 cpuinfo->l1.dc_nways = 133 (((cfg1 & MIPS_CONFIG1_DA_MASK) >> MIPS_CONFIG1_DA_SHIFT)) + 1; 134 cpuinfo->l1.dc_nsets = 135 1 << (((cfg1 & MIPS_CONFIG1_DS_MASK) >> MIPS_CONFIG1_DS_SHIFT) + 6); 136 } --- 280 unchanged lines hidden --- | 141 tmp = (cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT; 142 if (tmp != 0) { 143 cpuinfo->l1.dc_linesize = 1 << (tmp + 1); 144 cpuinfo->l1.dc_nways = 145 (((cfg1 & MIPS_CONFIG1_DA_MASK) >> MIPS_CONFIG1_DA_SHIFT)) + 1; 146 cpuinfo->l1.dc_nsets = 147 1 << (((cfg1 & MIPS_CONFIG1_DS_MASK) >> MIPS_CONFIG1_DS_SHIFT) + 6); 148 } --- 280 unchanged lines hidden --- |