| cpuregs.h (229677) | cpuregs.h (232615) |
|---|---|
| 1/* $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $ */ 2 3/* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. --- 38 unchanged lines hidden (view full) --- 47 * 48 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 49 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 50 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 51 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 52 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 53 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 54 * | 1/* $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $ */ 2 3/* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. --- 38 unchanged lines hidden (view full) --- 47 * 48 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 49 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 50 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 51 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 52 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 53 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 54 * |
| 55 * $FreeBSD: head/sys/mips/include/cpuregs.h 229677 2012-01-06 01:23:26Z gonzo $ | 55 * $FreeBSD: head/sys/mips/include/cpuregs.h 232615 2012-03-06 19:01:32Z jmallett $ |
| 56 */ 57 58#ifndef _MIPS_CPUREGS_H_ 59#define _MIPS_CPUREGS_H_ 60 61/* 62 * Address space. 63 * 32-bit mips CPUS partition their 32-bit address space into four segments: --- 160 unchanged lines hidden (view full) --- 224 * (same meaning as in CAUSE register). 225 * MIPS_CR_EXC_CODE The exception type (see exception codes below). 226 * 227 * Differences: 228 * r3k has 4 bits of execption type, r4k has 5 bits. 229 */ 230#define MIPS_CR_BR_DELAY 0x80000000 231#define MIPS_CR_COP_ERR 0x30000000 | 56 */ 57 58#ifndef _MIPS_CPUREGS_H_ 59#define _MIPS_CPUREGS_H_ 60 61/* 62 * Address space. 63 * 32-bit mips CPUS partition their 32-bit address space into four segments: --- 160 unchanged lines hidden (view full) --- 224 * (same meaning as in CAUSE register). 225 * MIPS_CR_EXC_CODE The exception type (see exception codes below). 226 * 227 * Differences: 228 * r3k has 4 bits of execption type, r4k has 5 bits. 229 */ 230#define MIPS_CR_BR_DELAY 0x80000000 231#define MIPS_CR_COP_ERR 0x30000000 |
| 232#define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */ 233#define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */ | 232#define MIPS_CR_EXC_CODE 0x0000007C /* five bits */ |
| 234#define MIPS_CR_IP 0x0000FF00 235#define MIPS_CR_EXC_CODE_SHIFT 2 236#define MIPS_CR_COP_ERR_SHIFT 28 237 238/* 239 * The bits in the status register. All bits are active when set to 1. 240 * 241 * R3000 status register fields: --- 21 unchanged lines hidden (view full) --- 263#define MIPS_SR_TS 0x00200000 264#define MIPS_SR_DE 0x00010000 265 266#define MIPS_SR_INT_IE 0x00000001 267/*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ 268#define MIPS_SR_INT_MASK 0x0000ff00 269 270/* | 233#define MIPS_CR_IP 0x0000FF00 234#define MIPS_CR_EXC_CODE_SHIFT 2 235#define MIPS_CR_COP_ERR_SHIFT 28 236 237/* 238 * The bits in the status register. All bits are active when set to 1. 239 * 240 * R3000 status register fields: --- 21 unchanged lines hidden (view full) --- 262#define MIPS_SR_TS 0x00200000 263#define MIPS_SR_DE 0x00010000 264 265#define MIPS_SR_INT_IE 0x00000001 266/*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ 267#define MIPS_SR_INT_MASK 0x0000ff00 268 269/* |
| 271 * The R2000/R3000-specific status register bit definitions. 272 * all bits are active when set to 1. 273 * 274 * MIPS_SR_PARITY_ERR Parity error. 275 * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 276 * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits. 277 * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache. 278 * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory. 279 * Interrupt enable bits defined below. 280 * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 281 * MIPS_SR_INT_ENA_OLD Old interrupt enable bit. 282 * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 283 * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit. 284 * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 285 */ 286 287#define MIPS1_PARITY_ERR 0x00100000 288#define MIPS1_CACHE_MISS 0x00080000 289#define MIPS1_PARITY_ZERO 0x00040000 290#define MIPS1_SWAP_CACHES 0x00020000 291#define MIPS1_ISOL_CACHES 0x00010000 292 293#define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/ 294#define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/ 295#define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/ 296#define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/ 297#define MIPS1_SR_KU_CUR 0x00000002 /* current KU */ 298 299/* backwards compatibility */ 300#define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR 301#define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS 302#define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO 303#define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES 304#define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES 305 306#define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD 307#define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD 308#define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV 309#define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR 310#define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV 311 312/* | |
| 313 * R4000 status register bit definitons, 314 * where different from r2000/r3000. 315 */ | 270 * R4000 status register bit definitons, 271 * where different from r2000/r3000. 272 */ |
| 316#define MIPS3_SR_XX 0x80000000 317#define MIPS3_SR_RP 0x08000000 318#define MIPS3_SR_FR 0x04000000 319#define MIPS3_SR_RE 0x02000000 | 273#define MIPS_SR_XX 0x80000000 274#define MIPS_SR_RP 0x08000000 275#define MIPS_SR_FR 0x04000000 276#define MIPS_SR_RE 0x02000000 |
| 320 | 277 |
| 321#define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */ 322#define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */ 323#define MIPS3_SR_SR 0x00100000 324#define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */ 325#define MIPS3_SR_DIAG_CH 0x00040000 326#define MIPS3_SR_DIAG_CE 0x00020000 327#define MIPS3_SR_DIAG_PE 0x00010000 328#define MIPS3_SR_EIE 0x00010000 /* TX79/R5900 */ 329#define MIPS3_SR_KX 0x00000080 330#define MIPS3_SR_SX 0x00000040 331#define MIPS3_SR_UX 0x00000020 332#define MIPS3_SR_KSU_MASK 0x00000018 333#define MIPS3_SR_KSU_USER 0x00000010 334#define MIPS3_SR_KSU_SUPER 0x00000008 335#define MIPS3_SR_KSU_KERNEL 0x00000000 336#define MIPS3_SR_ERL 0x00000004 337#define MIPS3_SR_EXL 0x00000002 | 278#define MIPS_SR_DIAG_DL 0x01000000 /* QED 52xx */ 279#define MIPS_SR_DIAG_IL 0x00800000 /* QED 52xx */ 280#define MIPS_SR_SR 0x00100000 281#define MIPS_SR_NMI 0x00080000 /* MIPS32/64 */ 282#define MIPS_SR_DIAG_CH 0x00040000 283#define MIPS_SR_DIAG_CE 0x00020000 284#define MIPS_SR_DIAG_PE 0x00010000 285#define MIPS_SR_EIE 0x00010000 /* TX79/R5900 */ 286#define MIPS_SR_KX 0x00000080 287#define MIPS_SR_SX 0x00000040 288#define MIPS_SR_UX 0x00000020 289#define MIPS_SR_KSU_MASK 0x00000018 290#define MIPS_SR_KSU_USER 0x00000010 291#define MIPS_SR_KSU_SUPER 0x00000008 292#define MIPS_SR_KSU_KERNEL 0x00000000 293#define MIPS_SR_ERL 0x00000004 294#define MIPS_SR_EXL 0x00000002 |
| 338 | 295 |
| 339#ifdef MIPS3_5900 340#undef MIPS_SR_INT_IE 341#define MIPS_SR_INT_IE 0x00010001 /* XXX */ 342#endif 343 344#define MIPS_SR_SOFT_RESET MIPS3_SR_SR 345#define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH 346#define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE 347#define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE 348#define MIPS_SR_KX MIPS3_SR_KX 349#define MIPS_SR_SX MIPS3_SR_SX 350#define MIPS_SR_UX MIPS3_SR_UX 351 352#define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK 353#define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER 354#define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER 355#define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL 356#define MIPS_SR_ERL MIPS3_SR_ERL 357#define MIPS_SR_EXL MIPS3_SR_EXL 358 359 | |
| 360/* 361 * The interrupt masks. 362 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 363 */ 364#define MIPS_INT_MASK 0xff00 365#define MIPS_INT_MASK_5 0x8000 366#define MIPS_INT_MASK_4 0x4000 367#define MIPS_INT_MASK_3 0x2000 368#define MIPS_INT_MASK_2 0x1000 369#define MIPS_INT_MASK_1 0x0800 370#define MIPS_INT_MASK_0 0x0400 371#define MIPS_HARD_INT_MASK 0xfc00 372#define MIPS_SOFT_INT_MASK_1 0x0200 373#define MIPS_SOFT_INT_MASK_0 0x0100 374 375/* | 296/* 297 * The interrupt masks. 298 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 299 */ 300#define MIPS_INT_MASK 0xff00 301#define MIPS_INT_MASK_5 0x8000 302#define MIPS_INT_MASK_4 0x4000 303#define MIPS_INT_MASK_3 0x2000 304#define MIPS_INT_MASK_2 0x1000 305#define MIPS_INT_MASK_1 0x0800 306#define MIPS_INT_MASK_0 0x0400 307#define MIPS_HARD_INT_MASK 0xfc00 308#define MIPS_SOFT_INT_MASK_1 0x0200 309#define MIPS_SOFT_INT_MASK_0 0x0100 310 311/* |
| 376 * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can 377 * choose to enable this interrupt. 378 */ 379#if defined(MIPS3_ENABLE_CLOCK_INTR) 380#define MIPS3_INT_MASK MIPS_INT_MASK 381#define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK 382#else 383#define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5) 384#define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5) 385#endif 386 387/* 388 * The bits in the context register. 389 */ 390#define MIPS1_CNTXT_PTE_BASE 0xFFE00000 391#define MIPS1_CNTXT_BAD_VPN 0x001FFFFC 392 393#define MIPS3_CNTXT_PTE_BASE 0xFF800000 394#define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0 395 396/* 397 * Location of MIPS32 exception vectors. Most are multiplexed in 398 * the sense that further decoding is necessary (e.g. reading the 399 * CAUSE register or NMI bits in STATUS). 400 * Most interrupts go via the 401 * The INT vector is dedicated for hardware interrupts; it is 402 * only referenced if the IV bit in CAUSE is set to 1. 403 */ 404#define MIPS_VEC_RESET 0xBFC00000 /* Hard, soft, or NMI */ 405#define MIPS_VEC_EJTAG 0xBFC00480 406#define MIPS_VEC_TLB 0x80000000 407#define MIPS_VEC_XTLB 0x80000080 408#define MIPS_VEC_CACHE 0x80000100 409#define MIPS_VEC_GENERIC 0x80000180 /* Most exceptions */ 410#define MIPS_VEC_INTERRUPT 0x80000200 411 412/* | |
| 413 * The bits in the MIPS3 config register. 414 * 415 * bit 0..5: R/W, Bit 6..31: R/O 416 */ 417 418/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ | 312 * The bits in the MIPS3 config register. 313 * 314 * bit 0..5: R/W, Bit 6..31: R/O 315 */ 316 317/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ |
| 419#define MIPS3_CONFIG_K0_MASK 0x00000007 | 318#define MIPS_CONFIG_K0_MASK 0x00000007 |
| 420 421/* 422 * R/W Update on Store Conditional 423 * 0: Store Conditional uses coherency algorithm specified by TLB 424 * 1: Store Conditional uses cacheable coherent update on write 425 */ | 319 320/* 321 * R/W Update on Store Conditional 322 * 0: Store Conditional uses coherency algorithm specified by TLB 323 * 1: Store Conditional uses cacheable coherent update on write 324 */ |
| 426#define MIPS3_CONFIG_CU 0x00000008 | 325#define MIPS_CONFIG_CU 0x00000008 |
| 427 | 326 |
| 428#define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */ 429#define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */ 430#define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \ | 327#define MIPS_CONFIG_DB 0x00000010 /* Primary D-cache line size */ 328#define MIPS_CONFIG_IB 0x00000020 /* Primary I-cache line size */ 329#define MIPS_CONFIG_CACHE_L1_LSIZE(config, bit) \ |
| 431 (((config) & (bit)) ? 32 : 16) 432 | 330 (((config) & (bit)) ? 32 : 16) 331 |
| 433#define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */ 434#define MIPS3_CONFIG_DC_SHIFT 6 435#define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */ 436#define MIPS3_CONFIG_IC_SHIFT 9 437#define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */ | 332#define MIPS_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */ 333#define MIPS_CONFIG_DC_SHIFT 6 334#define MIPS_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */ 335#define MIPS_CONFIG_IC_SHIFT 9 336#define MIPS_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */ |
| 438 439/* Cache size mode indication: available only on Vr41xx CPUs */ | 337 338/* Cache size mode indication: available only on Vr41xx CPUs */ |
| 440#define MIPS3_CONFIG_CS 0x00001000 441#define MIPS3_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */ 442#define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \ | 339#define MIPS_CONFIG_CS 0x00001000 340#define MIPS_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */ 341#define MIPS_CONFIG_CACHE_SIZE(config, mask, base, shift) \ |
| 443 ((base) << (((config) & (mask)) >> (shift))) 444 445/* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */ | 342 ((base) << (((config) & (mask)) >> (shift))) 343 344/* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */ |
| 446#define MIPS3_CONFIG_SE 0x00001000 | 345#define MIPS_CONFIG_SE 0x00001000 |
| 447 448/* Block ordering: 0: sequential, 1: sub-block */ | 346 347/* Block ordering: 0: sequential, 1: sub-block */ |
| 449#define MIPS3_CONFIG_EB 0x00002000 | 348#define MIPS_CONFIG_EB 0x00002000 |
| 450 451/* ECC mode - 0: ECC mode, 1: parity mode */ | 349 350/* ECC mode - 0: ECC mode, 1: parity mode */ |
| 452#define MIPS3_CONFIG_EM 0x00004000 | 351#define MIPS_CONFIG_EM 0x00004000 |
| 453 454/* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */ | 352 353/* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */ |
| 455#define MIPS3_CONFIG_BE 0x00008000 | 354#define MIPS_CONFIG_BE 0x00008000 |
| 456 457/* Dirty Shared coherency state - 0: enabled, 1: disabled */ | 355 356/* Dirty Shared coherency state - 0: enabled, 1: disabled */ |
| 458#define MIPS3_CONFIG_SM 0x00010000 | 357#define MIPS_CONFIG_SM 0x00010000 |
| 459 460/* Secondary Cache - 0: present, 1: not present */ | 358 359/* Secondary Cache - 0: present, 1: not present */ |
| 461#define MIPS3_CONFIG_SC 0x00020000 | 360#define MIPS_CONFIG_SC 0x00020000 |
| 462 463/* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */ | 361 362/* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */ |
| 464#define MIPS3_CONFIG_EW_MASK 0x000c0000 465#define MIPS3_CONFIG_EW_SHIFT 18 | 363#define MIPS_CONFIG_EW_MASK 0x000c0000 364#define MIPS_CONFIG_EW_SHIFT 18 |
| 466 467/* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */ | 365 366/* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */ |
| 468#define MIPS3_CONFIG_SW 0x00100000 | 367#define MIPS_CONFIG_SW 0x00100000 |
| 469 470/* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */ | 368 369/* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */ |
| 471#define MIPS3_CONFIG_SS 0x00200000 | 370#define MIPS_CONFIG_SS 0x00200000 |
| 472 473/* Secondary Cache line size */ | 371 372/* Secondary Cache line size */ |
| 474#define MIPS3_CONFIG_SB_MASK 0x00c00000 475#define MIPS3_CONFIG_SB_SHIFT 22 476#define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \ 477 (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT)) | 373#define MIPS_CONFIG_SB_MASK 0x00c00000 374#define MIPS_CONFIG_SB_SHIFT 22 375#define MIPS_CONFIG_CACHE_L2_LSIZE(config) \ 376 (0x10 << (((config) & MIPS_CONFIG_SB_MASK) >> MIPS_CONFIG_SB_SHIFT)) |
| 478 479/* Write back data rate */ | 377 378/* Write back data rate */ |
| 480#define MIPS3_CONFIG_EP_MASK 0x0f000000 481#define MIPS3_CONFIG_EP_SHIFT 24 | 379#define MIPS_CONFIG_EP_MASK 0x0f000000 380#define MIPS_CONFIG_EP_SHIFT 24 |
| 482 483/* System clock ratio - this value is CPU dependent */ | 381 382/* System clock ratio - this value is CPU dependent */ |
| 484#define MIPS3_CONFIG_EC_MASK 0x70000000 485#define MIPS3_CONFIG_EC_SHIFT 28 | 383#define MIPS_CONFIG_EC_MASK 0x70000000 384#define MIPS_CONFIG_EC_SHIFT 28 |
| 486 487/* Master-Checker Mode - 1: enabled */ | 385 386/* Master-Checker Mode - 1: enabled */ |
| 488#define MIPS3_CONFIG_CM 0x80000000 | 387#define MIPS_CONFIG_CM 0x80000000 |
| 489 490/* 491 * The bits in the MIPS4 config register. 492 */ 493 | 388 389/* 390 * The bits in the MIPS4 config register. 391 */ 392 |
| 494/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 495#define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK 496#define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */ 497#define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */ 498#define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */ 499#define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */ 500#define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */ 501#define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */ 502#define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */ 503#define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */ 504#define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */ 505#define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */ 506#define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */ 507#define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */ 508#define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */ 509 510#define MIPS4_CONFIG_DC_SHIFT 26 511#define MIPS4_CONFIG_IC_SHIFT 29 512 513#define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 514 ((base) << (((config) & (mask)) >> (shift))) 515 516#define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \ 517 (((config) & MIPS4_CONFIG_SB) ? 128 : 64) 518 | |
| 519/* 520 * Location of exception vectors. 521 * 522 * Common vectors: reset and UTLB miss. 523 */ 524#define MIPS_RESET_EXC_VEC ((intptr_t)(int32_t)0xBFC00000) 525#define MIPS_UTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000000) 526 527/* | 393/* 394 * Location of exception vectors. 395 * 396 * Common vectors: reset and UTLB miss. 397 */ 398#define MIPS_RESET_EXC_VEC ((intptr_t)(int32_t)0xBFC00000) 399#define MIPS_UTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000000) 400 401/* |
| 528 * MIPS-1 general exception vector (everything else) 529 */ 530#define MIPS1_GEN_EXC_VEC ((intptr_t)(int32_t)0x80000080) 531 532/* | |
| 533 * MIPS-III exception vectors 534 */ | 402 * MIPS-III exception vectors 403 */ |
| 535#define MIPS3_XTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000080) 536#define MIPS3_CACHE_ERR_EXC_VEC ((intptr_t)(int32_t)0x80000100) 537#define MIPS3_GEN_EXC_VEC ((intptr_t)(int32_t)0x80000180) | 404#define MIPS_XTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000080) 405#define MIPS_CACHE_ERR_EXC_VEC ((intptr_t)(int32_t)0x80000100) 406#define MIPS_GEN_EXC_VEC ((intptr_t)(int32_t)0x80000180) |
| 538 539/* | 407 408/* |
| 540 * TX79 (R5900) exception vectors 541 */ 542#define MIPS_R5900_COUNTER_EXC_VEC 0x80000080 543#define MIPS_R5900_DEBUG_EXC_VEC 0x80000100 544 545/* | |
| 546 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector. 547 */ | 409 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector. 410 */ |
| 548#define MIPS3_INTR_EXC_VEC 0x80000200 | 411#define MIPS_INTR_EXC_VEC 0x80000200 |
| 549 550/* 551 * Coprocessor 0 registers: 552 * 553 * v--- width for mips I,III,32,64 554 * (3=32bit, 6=64bit, i=impl dep) 555 * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index. 556 * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random. --- 150 unchanged lines hidden (view full) --- 707#define MIPS_BREAK_DDB (MIPS_BREAK_INSTR | \ 708 (MIPS_BREAK_DDB_VAL << MIPS_BREAK_VAL_SHIFT)) 709 710/* 711 * Mininum and maximum cache sizes. 712 */ 713#define MIPS_MIN_CACHE_SIZE (16 * 1024) 714#define MIPS_MAX_CACHE_SIZE (256 * 1024) | 412 413/* 414 * Coprocessor 0 registers: 415 * 416 * v--- width for mips I,III,32,64 417 * (3=32bit, 6=64bit, i=impl dep) 418 * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index. 419 * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random. --- 150 unchanged lines hidden (view full) --- 570#define MIPS_BREAK_DDB (MIPS_BREAK_INSTR | \ 571 (MIPS_BREAK_DDB_VAL << MIPS_BREAK_VAL_SHIFT)) 572 573/* 574 * Mininum and maximum cache sizes. 575 */ 576#define MIPS_MIN_CACHE_SIZE (16 * 1024) 577#define MIPS_MAX_CACHE_SIZE (256 * 1024) |
| 715#define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */ | 578#define MIPS_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */ |
| 716 717/* 718 * The floating point version and status registers. 719 */ 720#define MIPS_FPU_ID $0 721#define MIPS_FPU_CSR $31 722 723/* --- 20 unchanged lines hidden (view full) --- 744#define MIPS_FPU_EXCEPTION_INEXACT 0x00001000 745#define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000 746#define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000 747#define MIPS_FPU_EXCEPTION_DIV0 0x00008000 748#define MIPS_FPU_EXCEPTION_INVALID 0x00010000 749#define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000 750#define MIPS_FPU_COND_BIT 0x00800000 751#define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ | 579 580/* 581 * The floating point version and status registers. 582 */ 583#define MIPS_FPU_ID $0 584#define MIPS_FPU_CSR $31 585 586/* --- 20 unchanged lines hidden (view full) --- 607#define MIPS_FPU_EXCEPTION_INEXACT 0x00001000 608#define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000 609#define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000 610#define MIPS_FPU_EXCEPTION_DIV0 0x00008000 611#define MIPS_FPU_EXCEPTION_INVALID 0x00010000 612#define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000 613#define MIPS_FPU_COND_BIT 0x00800000 614#define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ |
| 752#define MIPS1_FPC_MBZ_BITS 0xff7c0000 753#define MIPS3_FPC_MBZ_BITS 0xfe7c0000 | 615#define MIPS_FPC_MBZ_BITS 0xfe7c0000 |
| 754 755 756/* 757 * Constants to determine if have a floating point instruction. 758 */ 759#define MIPS_OPCODE_SHIFT 26 760#define MIPS_OPCODE_C1 0x11 761 | 616 617 618/* 619 * Constants to determine if have a floating point instruction. 620 */ 621#define MIPS_OPCODE_SHIFT 26 622#define MIPS_OPCODE_C1 0x11 623 |
| 762 763/* 764 * The low part of the TLB entry. 765 */ 766#define MIPS1_TLB_PFN 0xfffff000 767#define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800 768#define MIPS1_TLB_DIRTY_BIT 0x00000400 769#define MIPS1_TLB_VALID_BIT 0x00000200 770#define MIPS1_TLB_GLOBAL_BIT 0x00000100 771 772#define MIPS3_TLB_PFN 0x3fffffc0 773#define MIPS3_TLB_ATTR_MASK 0x00000038 774#define MIPS3_TLB_ATTR_SHIFT 3 775#define MIPS3_TLB_DIRTY_BIT 0x00000004 776#define MIPS3_TLB_VALID_BIT 0x00000002 777#define MIPS3_TLB_GLOBAL_BIT 0x00000001 778 779#define MIPS1_TLB_PHYS_PAGE_SHIFT 12 780#define MIPS3_TLB_PHYS_PAGE_SHIFT 6 781#define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN 782#define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN 783#define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT 784#define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT 785 786/* 787 * MIPS3_TLB_ATTR values - coherency algorithm: 788 * 0: cacheable, noncoherent, write-through, no write allocate 789 * 1: cacheable, noncoherent, write-through, write allocate 790 * 2: uncached 791 * 3: cacheable, noncoherent, write-back (noncoherent) 792 * 4: cacheable, coherent, write-back, exclusive (exclusive) 793 * 5: cacheable, coherent, write-back, exclusive on write (sharable) 794 * 6: cacheable, coherent, write-back, update on write (update) 795 * 7: uncached, accelerated (gather STORE operations) 796 */ 797#define MIPS3_TLB_ATTR_WT 0 /* IDT */ 798#define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */ 799#define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */ 800#define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */ 801#define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */ 802#define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */ 803#define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */ 804#define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */ 805 806 807/* 808 * The high part of the TLB entry. 809 */ 810#define MIPS1_TLB_VPN 0xfffff000 811#define MIPS1_TLB_PID 0x00000fc0 812#define MIPS1_TLB_PID_SHIFT 6 813 814#define MIPS3_TLB_VPN2 0xffffe000 815#define MIPS3_TLB_ASID 0x000000ff 816 817#define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN 818#define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2 819#define MIPS3_TLB_PID MIPS3_TLB_ASID 820#define MIPS_TLB_VIRT_PAGE_SHIFT 12 821 822/* 823 * r3000: shift count to put the index in the right spot. 824 */ 825#define MIPS1_TLB_INDEX_SHIFT 8 826 827/* 828 * The first TLB that write random hits. 829 */ 830#define MIPS1_TLB_FIRST_RAND_ENTRY 8 831#define MIPS3_TLB_WIRED_UPAGES 1 832 833/* 834 * The number of process id entries. 835 */ 836#define MIPS1_TLB_NUM_PIDS 64 837#define MIPS3_TLB_NUM_ASIDS 256 838 839/* 840 * Patch codes to hide CPU design differences between MIPS1 and MIPS3. 841 */ 842 843/* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */ 844 845#if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ 846 && defined(MIPS1) /* XXX simonb must be neater! */ 847#define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT 848#define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS 849#endif 850 851#if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ 852 && !defined(MIPS1) /* XXX simonb must be neater! */ 853#define MIPS_TLB_PID_SHIFT 0 854#define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS 855#endif 856 857 858#if !defined(MIPS_TLB_PID_SHIFT) 859#define MIPS_TLB_PID_SHIFT \ 860 ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT) 861 862#define MIPS_TLB_NUM_PIDS \ 863 ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS) 864#endif 865 866/* 867 * CPU processor revision IDs for company ID == 0 (non mips32/64 chips) 868 */ 869#define MIPS_R2000 0x01 /* MIPS R2000 ISA I */ 870#define MIPS_R3000 0x02 /* MIPS R3000 ISA I */ 871#define MIPS_R6000 0x03 /* MIPS R6000 ISA II */ 872#define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */ 873#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */ 874#define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */ 875#define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */ 876#define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */ 877#define MIPS_R4200 0x0a /* NEC VR4200 ISA III */ 878#define MIPS_R4300 0x0b /* NEC VR4300 ISA III */ 879#define MIPS_R4100 0x0c /* NEC VR4100 ISA III */ 880#define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */ 881#define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */ 882#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 883#define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */ 884#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 885#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ 886#define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */ 887#define MIPS_R4650 0x22 /* QED R4650 ISA III */ 888#define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */ 889#define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */ 890#define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */ 891#define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */ 892#define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */ 893#define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */ 894#define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */ 895#define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */ 896#define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */ 897#define MIPS_TX7900 0x38 /* Toshiba TX79 ISA III+*/ 898#define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */ 899#define MIPS_R5500 0x55 /* NEC VR5500 ISA IV */ 900 901/* 902 * CPU revision IDs for some prehistoric processors. 903 */ 904 905/* For MIPS_R3000 */ 906#define MIPS_REV_R3000 0x20 907#define MIPS_REV_R3000A 0x30 908 909/* For MIPS_TX3900 */ 910#define MIPS_REV_TX3912 0x10 911#define MIPS_REV_TX3922 0x30 912#define MIPS_REV_TX3927 0x40 913 914/* For MIPS_R4000 */ 915#define MIPS_REV_R4000_A 0x00 916#define MIPS_REV_R4000_B 0x22 917#define MIPS_REV_R4000_C 0x30 918#define MIPS_REV_R4400_A 0x40 919#define MIPS_REV_R4400_B 0x50 920#define MIPS_REV_R4400_C 0x60 921 922/* For MIPS_TX4900 */ 923#define MIPS_REV_TX4927 0x22 924 925/* 926 * CPU processor revision IDs for company ID == 1 (MIPS) 927 */ 928#define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */ 929#define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */ 930#define MIPS_20Kc 0x82 /* MIPS 20Kc ISA 64 */ 931#define MIPS_4Kmp 0x83 /* MIPS 4Km/4Kp ISA 32 */ 932#define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */ 933#define MIPS_4KEmp 0x85 /* MIPS 4KEm/4KEp ISA 32 */ 934#define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */ 935#define MIPS_M4K 0x87 /* MIPS M4K ISA 32 Rel 2 */ 936#define MIPS_25Kf 0x88 /* MIPS 25Kf ISA 64 */ 937#define MIPS_5KE 0x89 /* MIPS 5KE ISA 64 Rel 2 */ 938#define MIPS_4KEc_R2 0x90 /* MIPS 4KEc_R2 ISA 32 Rel 2 */ 939#define MIPS_4KEmp_R2 0x91 /* MIPS 4KEm/4KEp_R2 ISA 32 Rel 2 */ 940#define MIPS_4KSd 0x92 /* MIPS 4KSd ISA 32 Rel 2 */ 941#define MIPS_24K 0x93 /* MIPS 24Kc/24Kf ISA 32 Rel 2 */ 942#define MIPS_34K 0x95 /* MIPS 34K ISA 32 R2 MT */ 943#define MIPS_24KE 0x96 /* MIPS 24KEc ISA 32 Rel 2 */ 944#define MIPS_74K 0x97 /* MIPS 74Kc/74Kf ISA 32 Rel 2 */ 945 946/* 947 * AMD (company ID 3) use the processor ID field to donote the CPU core 948 * revision and the company options field do donate the SOC chip type. 949 */ 950 951/* CPU processor revision IDs */ 952#define MIPS_AU_REV1 0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */ 953#define MIPS_AU_REV2 0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */ 954 955/* CPU company options IDs */ 956#define MIPS_AU1000 0x00 957#define MIPS_AU1500 0x01 958#define MIPS_AU1100 0x02 959#define MIPS_AU1550 0x03 960 961/* 962 * CPU processor revision IDs for company ID == 4 (Broadcom) 963 */ 964#define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */ 965 966/* 967 * CPU processor revision IDs for company ID == 5 (SandCraft) 968 */ 969#define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */ 970 971/* 972 * FPU processor revision ID 973 */ 974#define MIPS_SOFT 0x00 /* Software emulation ISA I */ 975#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 976#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 977#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 978#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 979#define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */ 980#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 981#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ 982 983#ifdef ENABLE_MIPS_TX3900 984#include <mips/r3900regs.h> 985#endif 986#ifdef MIPS3_5900 987#include <mips/r5900regs.h> 988#endif 989#ifdef MIPS64_SB1 990#include <mips/sb1regs.h> 991#endif 992 | |
| 993#endif /* _MIPS_CPUREGS_H_ */ | 624#endif /* _MIPS_CPUREGS_H_ */ |