1/* $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $ */ 2 3/* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)machConst.h 8.1 (Berkeley) 6/10/93 35 * 36 * machConst.h -- 37 * 38 * Machine dependent constants. 39 * 40 * Copyright (C) 1989 Digital Equipment Corporation. 41 * Permission to use, copy, modify, and distribute this software and 42 * its documentation for any purpose and without fee is hereby granted, 43 * provided that the above copyright notice appears in all copies. 44 * Digital Equipment Corporation makes no representations about the 45 * suitability of this software for any purpose. It is provided "as is" 46 * without express or implied warranty. 47 * 48 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 49 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 50 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 51 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 52 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 53 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 54 *
| 1/* $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $ */ 2 3/* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)machConst.h 8.1 (Berkeley) 6/10/93 35 * 36 * machConst.h -- 37 * 38 * Machine dependent constants. 39 * 40 * Copyright (C) 1989 Digital Equipment Corporation. 41 * Permission to use, copy, modify, and distribute this software and 42 * its documentation for any purpose and without fee is hereby granted, 43 * provided that the above copyright notice appears in all copies. 44 * Digital Equipment Corporation makes no representations about the 45 * suitability of this software for any purpose. It is provided "as is" 46 * without express or implied warranty. 47 * 48 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 49 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 50 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 51 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 52 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 53 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 54 *
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56 */ 57 58#ifndef _MIPS_CPUREGS_H_ 59#define _MIPS_CPUREGS_H_ 60 61/* 62 * Address space. 63 * 32-bit mips CPUS partition their 32-bit address space into four segments: 64 * 65 * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped 66 * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped 67 * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped 68 * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped 69 * 70 * Caching of mapped addresses is controlled by bits in the TLB entry. 71 */ 72 73#define MIPS_KSEG0_LARGEST_PHYS (0x20000000) 74#define MIPS_KSEG0_PHYS_MASK (0x1fffffff) 75#define MIPS_XKPHYS_LARGEST_PHYS (0x10000000000) /* 40 bit PA */ 76#define MIPS_XKPHYS_PHYS_MASK (0x0ffffffffff) 77 78#ifndef LOCORE 79#define MIPS_KUSEG_START 0x00000000 80#define MIPS_KSEG0_START ((intptr_t)(int32_t)0x80000000) 81#define MIPS_KSEG0_END ((intptr_t)(int32_t)0x9fffffff) 82#define MIPS_KSEG1_START ((intptr_t)(int32_t)0xa0000000) 83#define MIPS_KSEG1_END ((intptr_t)(int32_t)0xbfffffff) 84#define MIPS_KSSEG_START ((intptr_t)(int32_t)0xc0000000) 85#define MIPS_KSSEG_END ((intptr_t)(int32_t)0xdfffffff) 86#define MIPS_KSEG3_START ((intptr_t)(int32_t)0xe0000000) 87#define MIPS_KSEG3_END ((intptr_t)(int32_t)0xffffffff) 88#define MIPS_KSEG2_START MIPS_KSSEG_START 89#define MIPS_KSEG2_END MIPS_KSSEG_END 90#endif 91 92#define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START) 93#define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | MIPS_KSEG1_START) 94#define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK) 95#define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK) 96 97#define MIPS_IS_KSEG0_ADDR(x) \ 98 (((vm_offset_t)(x) >= MIPS_KSEG0_START) && \ 99 ((vm_offset_t)(x) <= MIPS_KSEG0_END)) 100#define MIPS_IS_KSEG1_ADDR(x) \ 101 (((vm_offset_t)(x) >= MIPS_KSEG1_START) && \ 102 ((vm_offset_t)(x) <= MIPS_KSEG1_END)) 103#define MIPS_IS_VALID_PTR(x) (MIPS_IS_KSEG0_ADDR(x) || \ 104 MIPS_IS_KSEG1_ADDR(x)) 105 106/* 107 * Cache Coherency Attributes: 108 * UC: Uncached. 109 * UA: Uncached accelerated. 110 * C: Cacheable, coherency unspecified. 111 * CNC: Cacheable non-coherent. 112 * CC: Cacheable coherent. 113 * CCE: Cacheable coherent, exclusive read. 114 * CCEW: Cacheable coherent, exclusive write. 115 * CCUOW: Cacheable coherent, update on write. 116 * 117 * Note that some bits vary in meaning across implementations (and that the 118 * listing here is no doubt incomplete) and that the optimal cached mode varies 119 * between implementations. 0x02 is required to be UC and 0x03 is required to 120 * be a least C. 121 * 122 * We define the following logical bits: 123 * UNCACHED: 124 * The optimal uncached mode for the target CPU type. This must 125 * be suitable for use in accessing memory-mapped devices. 126 * CACHED: The optional cached mode for the target CPU type. 127 */ 128 129#define MIPS_CCA_UC 0x02 /* Uncached. */ 130#define MIPS_CCA_C 0x03 /* Cacheable, coherency unspecified. */ 131 132#if defined(CPU_R4000) || defined(CPU_R10000) 133#define MIPS_CCA_CNC 0x03 134#define MIPS_CCA_CCE 0x04 135#define MIPS_CCA_CCEW 0x05 136 137#ifdef CPU_R4000 138#define MIPS_CCA_CCUOW 0x06 139#endif 140 141#ifdef CPU_R10000 142#define MIPS_CCA_UA 0x07 143#endif 144 145#define MIPS_CCA_CACHED MIPS_CCA_CCEW 146#endif /* defined(CPU_R4000) || defined(CPU_R10000) */ 147 148#if defined(CPU_SB1) 149#define MIPS_CCA_CC 0x05 /* Cacheable Coherent. */ 150#endif 151 152#ifndef MIPS_CCA_UNCACHED 153#define MIPS_CCA_UNCACHED MIPS_CCA_UC 154#endif 155 156/* 157 * If we don't know which cached mode to use and there is a cache coherent 158 * mode, use it. If there is not a cache coherent mode, use the required 159 * cacheable mode. 160 */ 161#ifndef MIPS_CCA_CACHED 162#ifdef MIPS_CCA_CC 163#define MIPS_CCA_CACHED MIPS_CCA_CC 164#else 165#define MIPS_CCA_CACHED MIPS_CCA_C 166#endif 167#endif 168 169#define MIPS_PHYS_TO_XKPHYS(cca,x) \ 170 ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x)) 171#define MIPS_PHYS_TO_XKPHYS_CACHED(x) \ 172 ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_CACHED) << 59) | (x)) 173#define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \ 174 ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_UNCACHED) << 59) | (x)) 175 176#define MIPS_XKPHYS_TO_PHYS(x) ((uintptr_t)(x) & MIPS_XKPHYS_PHYS_MASK) 177 178#define MIPS_XKPHYS_START 0x8000000000000000 179#define MIPS_XKPHYS_END 0xbfffffffffffffff 180#define MIPS_XUSEG_START 0x0000000000000000 181#define MIPS_XUSEG_END 0x0000010000000000 182#define MIPS_XKSEG_START 0xc000000000000000 183#define MIPS_XKSEG_END 0xc00000ff80000000 184#define MIPS_XKSEG_COMPAT32_START 0xffffffff80000000 185#define MIPS_XKSEG_COMPAT32_END 0xffffffffffffffff 186#define MIPS_XKSEG_TO_COMPAT32(va) ((va) & 0xffffffff) 187 188#ifdef __mips_n64 189#define MIPS_DIRECT_MAPPABLE(pa) 1 190#define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_XKPHYS_CACHED(pa) 191#define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_XKPHYS_UNCACHED(pa) 192#define MIPS_DIRECT_TO_PHYS(va) MIPS_XKPHYS_TO_PHYS(va) 193#else 194#define MIPS_DIRECT_MAPPABLE(pa) ((pa) < MIPS_KSEG0_LARGEST_PHYS) 195#define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_KSEG0(pa) 196#define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_KSEG1(pa) 197#define MIPS_DIRECT_TO_PHYS(va) MIPS_KSEG0_TO_PHYS(va) 198#endif 199 200/* CPU dependent mtc0 hazard hook */ 201#if defined(CPU_CNMIPS) || defined(CPU_RMI) 202#define COP0_SYNC 203#elif defined(CPU_NLM) 204#define COP0_SYNC .word 0xc0 /* ehb */ 205#elif defined(CPU_SB1) 206#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop 207#else 208/* 209 * Pick a reasonable default based on the "typical" spacing described in the 210 * "CP0 Hazards" chapter of MIPS Architecture Book Vol III. 211 */ 212#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop 213#endif 214#define COP0_HAZARD_FPUENABLE nop; nop; nop; nop; 215 216/* 217 * The bits in the cause register. 218 * 219 * Bits common to r3000 and r4000: 220 * 221 * MIPS_CR_BR_DELAY Exception happened in branch delay slot. 222 * MIPS_CR_COP_ERR Coprocessor error. 223 * MIPS_CR_IP Interrupt pending bits defined below. 224 * (same meaning as in CAUSE register). 225 * MIPS_CR_EXC_CODE The exception type (see exception codes below). 226 * 227 * Differences: 228 * r3k has 4 bits of execption type, r4k has 5 bits. 229 */ 230#define MIPS_CR_BR_DELAY 0x80000000 231#define MIPS_CR_COP_ERR 0x30000000 232#define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */ 233#define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */ 234#define MIPS_CR_IP 0x0000FF00 235#define MIPS_CR_EXC_CODE_SHIFT 2
| 56 */ 57 58#ifndef _MIPS_CPUREGS_H_ 59#define _MIPS_CPUREGS_H_ 60 61/* 62 * Address space. 63 * 32-bit mips CPUS partition their 32-bit address space into four segments: 64 * 65 * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped 66 * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped 67 * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped 68 * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped 69 * 70 * Caching of mapped addresses is controlled by bits in the TLB entry. 71 */ 72 73#define MIPS_KSEG0_LARGEST_PHYS (0x20000000) 74#define MIPS_KSEG0_PHYS_MASK (0x1fffffff) 75#define MIPS_XKPHYS_LARGEST_PHYS (0x10000000000) /* 40 bit PA */ 76#define MIPS_XKPHYS_PHYS_MASK (0x0ffffffffff) 77 78#ifndef LOCORE 79#define MIPS_KUSEG_START 0x00000000 80#define MIPS_KSEG0_START ((intptr_t)(int32_t)0x80000000) 81#define MIPS_KSEG0_END ((intptr_t)(int32_t)0x9fffffff) 82#define MIPS_KSEG1_START ((intptr_t)(int32_t)0xa0000000) 83#define MIPS_KSEG1_END ((intptr_t)(int32_t)0xbfffffff) 84#define MIPS_KSSEG_START ((intptr_t)(int32_t)0xc0000000) 85#define MIPS_KSSEG_END ((intptr_t)(int32_t)0xdfffffff) 86#define MIPS_KSEG3_START ((intptr_t)(int32_t)0xe0000000) 87#define MIPS_KSEG3_END ((intptr_t)(int32_t)0xffffffff) 88#define MIPS_KSEG2_START MIPS_KSSEG_START 89#define MIPS_KSEG2_END MIPS_KSSEG_END 90#endif 91 92#define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START) 93#define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | MIPS_KSEG1_START) 94#define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK) 95#define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK) 96 97#define MIPS_IS_KSEG0_ADDR(x) \ 98 (((vm_offset_t)(x) >= MIPS_KSEG0_START) && \ 99 ((vm_offset_t)(x) <= MIPS_KSEG0_END)) 100#define MIPS_IS_KSEG1_ADDR(x) \ 101 (((vm_offset_t)(x) >= MIPS_KSEG1_START) && \ 102 ((vm_offset_t)(x) <= MIPS_KSEG1_END)) 103#define MIPS_IS_VALID_PTR(x) (MIPS_IS_KSEG0_ADDR(x) || \ 104 MIPS_IS_KSEG1_ADDR(x)) 105 106/* 107 * Cache Coherency Attributes: 108 * UC: Uncached. 109 * UA: Uncached accelerated. 110 * C: Cacheable, coherency unspecified. 111 * CNC: Cacheable non-coherent. 112 * CC: Cacheable coherent. 113 * CCE: Cacheable coherent, exclusive read. 114 * CCEW: Cacheable coherent, exclusive write. 115 * CCUOW: Cacheable coherent, update on write. 116 * 117 * Note that some bits vary in meaning across implementations (and that the 118 * listing here is no doubt incomplete) and that the optimal cached mode varies 119 * between implementations. 0x02 is required to be UC and 0x03 is required to 120 * be a least C. 121 * 122 * We define the following logical bits: 123 * UNCACHED: 124 * The optimal uncached mode for the target CPU type. This must 125 * be suitable for use in accessing memory-mapped devices. 126 * CACHED: The optional cached mode for the target CPU type. 127 */ 128 129#define MIPS_CCA_UC 0x02 /* Uncached. */ 130#define MIPS_CCA_C 0x03 /* Cacheable, coherency unspecified. */ 131 132#if defined(CPU_R4000) || defined(CPU_R10000) 133#define MIPS_CCA_CNC 0x03 134#define MIPS_CCA_CCE 0x04 135#define MIPS_CCA_CCEW 0x05 136 137#ifdef CPU_R4000 138#define MIPS_CCA_CCUOW 0x06 139#endif 140 141#ifdef CPU_R10000 142#define MIPS_CCA_UA 0x07 143#endif 144 145#define MIPS_CCA_CACHED MIPS_CCA_CCEW 146#endif /* defined(CPU_R4000) || defined(CPU_R10000) */ 147 148#if defined(CPU_SB1) 149#define MIPS_CCA_CC 0x05 /* Cacheable Coherent. */ 150#endif 151 152#ifndef MIPS_CCA_UNCACHED 153#define MIPS_CCA_UNCACHED MIPS_CCA_UC 154#endif 155 156/* 157 * If we don't know which cached mode to use and there is a cache coherent 158 * mode, use it. If there is not a cache coherent mode, use the required 159 * cacheable mode. 160 */ 161#ifndef MIPS_CCA_CACHED 162#ifdef MIPS_CCA_CC 163#define MIPS_CCA_CACHED MIPS_CCA_CC 164#else 165#define MIPS_CCA_CACHED MIPS_CCA_C 166#endif 167#endif 168 169#define MIPS_PHYS_TO_XKPHYS(cca,x) \ 170 ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x)) 171#define MIPS_PHYS_TO_XKPHYS_CACHED(x) \ 172 ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_CACHED) << 59) | (x)) 173#define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \ 174 ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_UNCACHED) << 59) | (x)) 175 176#define MIPS_XKPHYS_TO_PHYS(x) ((uintptr_t)(x) & MIPS_XKPHYS_PHYS_MASK) 177 178#define MIPS_XKPHYS_START 0x8000000000000000 179#define MIPS_XKPHYS_END 0xbfffffffffffffff 180#define MIPS_XUSEG_START 0x0000000000000000 181#define MIPS_XUSEG_END 0x0000010000000000 182#define MIPS_XKSEG_START 0xc000000000000000 183#define MIPS_XKSEG_END 0xc00000ff80000000 184#define MIPS_XKSEG_COMPAT32_START 0xffffffff80000000 185#define MIPS_XKSEG_COMPAT32_END 0xffffffffffffffff 186#define MIPS_XKSEG_TO_COMPAT32(va) ((va) & 0xffffffff) 187 188#ifdef __mips_n64 189#define MIPS_DIRECT_MAPPABLE(pa) 1 190#define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_XKPHYS_CACHED(pa) 191#define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_XKPHYS_UNCACHED(pa) 192#define MIPS_DIRECT_TO_PHYS(va) MIPS_XKPHYS_TO_PHYS(va) 193#else 194#define MIPS_DIRECT_MAPPABLE(pa) ((pa) < MIPS_KSEG0_LARGEST_PHYS) 195#define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_KSEG0(pa) 196#define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_KSEG1(pa) 197#define MIPS_DIRECT_TO_PHYS(va) MIPS_KSEG0_TO_PHYS(va) 198#endif 199 200/* CPU dependent mtc0 hazard hook */ 201#if defined(CPU_CNMIPS) || defined(CPU_RMI) 202#define COP0_SYNC 203#elif defined(CPU_NLM) 204#define COP0_SYNC .word 0xc0 /* ehb */ 205#elif defined(CPU_SB1) 206#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop 207#else 208/* 209 * Pick a reasonable default based on the "typical" spacing described in the 210 * "CP0 Hazards" chapter of MIPS Architecture Book Vol III. 211 */ 212#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop 213#endif 214#define COP0_HAZARD_FPUENABLE nop; nop; nop; nop; 215 216/* 217 * The bits in the cause register. 218 * 219 * Bits common to r3000 and r4000: 220 * 221 * MIPS_CR_BR_DELAY Exception happened in branch delay slot. 222 * MIPS_CR_COP_ERR Coprocessor error. 223 * MIPS_CR_IP Interrupt pending bits defined below. 224 * (same meaning as in CAUSE register). 225 * MIPS_CR_EXC_CODE The exception type (see exception codes below). 226 * 227 * Differences: 228 * r3k has 4 bits of execption type, r4k has 5 bits. 229 */ 230#define MIPS_CR_BR_DELAY 0x80000000 231#define MIPS_CR_COP_ERR 0x30000000 232#define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */ 233#define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */ 234#define MIPS_CR_IP 0x0000FF00 235#define MIPS_CR_EXC_CODE_SHIFT 2
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236 237/* 238 * The bits in the status register. All bits are active when set to 1. 239 * 240 * R3000 status register fields: 241 * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors. 242 * MIPS_SR_TS TLB shutdown. 243 * 244 * MIPS_SR_INT_IE Master (current) interrupt enable bit. 245 * 246 * Differences: 247 * r3k has cache control is via frobbing SR register bits, whereas the 248 * r4k cache control is via explicit instructions. 249 * r3k has a 3-entry stack of kernel/user bits, whereas the 250 * r4k has kernel/supervisor/user. 251 */ 252#define MIPS_SR_COP_USABILITY 0xf0000000 253#define MIPS_SR_COP_0_BIT 0x10000000 254#define MIPS_SR_COP_1_BIT 0x20000000 255#define MIPS_SR_COP_2_BIT 0x40000000 256 257 /* r4k and r3k differences, see below */ 258 259#define MIPS_SR_MX 0x01000000 /* MIPS64 */ 260#define MIPS_SR_PX 0x00800000 /* MIPS64 */ 261#define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */ 262#define MIPS_SR_TS 0x00200000 263#define MIPS_SR_DE 0x00010000 264 265#define MIPS_SR_INT_IE 0x00000001 266/*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ 267#define MIPS_SR_INT_MASK 0x0000ff00 268 269/* 270 * The R2000/R3000-specific status register bit definitions. 271 * all bits are active when set to 1. 272 * 273 * MIPS_SR_PARITY_ERR Parity error. 274 * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 275 * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits. 276 * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache. 277 * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory. 278 * Interrupt enable bits defined below. 279 * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 280 * MIPS_SR_INT_ENA_OLD Old interrupt enable bit. 281 * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 282 * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit. 283 * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 284 */ 285 286#define MIPS1_PARITY_ERR 0x00100000 287#define MIPS1_CACHE_MISS 0x00080000 288#define MIPS1_PARITY_ZERO 0x00040000 289#define MIPS1_SWAP_CACHES 0x00020000 290#define MIPS1_ISOL_CACHES 0x00010000 291 292#define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/ 293#define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/ 294#define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/ 295#define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/ 296#define MIPS1_SR_KU_CUR 0x00000002 /* current KU */ 297 298/* backwards compatibility */ 299#define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR 300#define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS 301#define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO 302#define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES 303#define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES 304 305#define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD 306#define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD 307#define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV 308#define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR 309#define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV 310 311/* 312 * R4000 status register bit definitons, 313 * where different from r2000/r3000. 314 */ 315#define MIPS3_SR_XX 0x80000000 316#define MIPS3_SR_RP 0x08000000 317#define MIPS3_SR_FR 0x04000000 318#define MIPS3_SR_RE 0x02000000 319 320#define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */ 321#define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */ 322#define MIPS3_SR_SR 0x00100000 323#define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */ 324#define MIPS3_SR_DIAG_CH 0x00040000 325#define MIPS3_SR_DIAG_CE 0x00020000 326#define MIPS3_SR_DIAG_PE 0x00010000 327#define MIPS3_SR_EIE 0x00010000 /* TX79/R5900 */ 328#define MIPS3_SR_KX 0x00000080 329#define MIPS3_SR_SX 0x00000040 330#define MIPS3_SR_UX 0x00000020 331#define MIPS3_SR_KSU_MASK 0x00000018 332#define MIPS3_SR_KSU_USER 0x00000010 333#define MIPS3_SR_KSU_SUPER 0x00000008 334#define MIPS3_SR_KSU_KERNEL 0x00000000 335#define MIPS3_SR_ERL 0x00000004 336#define MIPS3_SR_EXL 0x00000002 337 338#ifdef MIPS3_5900 339#undef MIPS_SR_INT_IE 340#define MIPS_SR_INT_IE 0x00010001 /* XXX */ 341#endif 342 343#define MIPS_SR_SOFT_RESET MIPS3_SR_SR 344#define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH 345#define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE 346#define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE 347#define MIPS_SR_KX MIPS3_SR_KX 348#define MIPS_SR_SX MIPS3_SR_SX 349#define MIPS_SR_UX MIPS3_SR_UX 350 351#define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK 352#define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER 353#define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER 354#define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL 355#define MIPS_SR_ERL MIPS3_SR_ERL 356#define MIPS_SR_EXL MIPS3_SR_EXL 357 358 359/* 360 * The interrupt masks. 361 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 362 */ 363#define MIPS_INT_MASK 0xff00 364#define MIPS_INT_MASK_5 0x8000 365#define MIPS_INT_MASK_4 0x4000 366#define MIPS_INT_MASK_3 0x2000 367#define MIPS_INT_MASK_2 0x1000 368#define MIPS_INT_MASK_1 0x0800 369#define MIPS_INT_MASK_0 0x0400 370#define MIPS_HARD_INT_MASK 0xfc00 371#define MIPS_SOFT_INT_MASK_1 0x0200 372#define MIPS_SOFT_INT_MASK_0 0x0100 373 374/* 375 * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can 376 * choose to enable this interrupt. 377 */ 378#if defined(MIPS3_ENABLE_CLOCK_INTR) 379#define MIPS3_INT_MASK MIPS_INT_MASK 380#define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK 381#else 382#define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5) 383#define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5) 384#endif 385 386/* 387 * The bits in the context register. 388 */ 389#define MIPS1_CNTXT_PTE_BASE 0xFFE00000 390#define MIPS1_CNTXT_BAD_VPN 0x001FFFFC 391 392#define MIPS3_CNTXT_PTE_BASE 0xFF800000 393#define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0 394 395/* 396 * Location of MIPS32 exception vectors. Most are multiplexed in 397 * the sense that further decoding is necessary (e.g. reading the 398 * CAUSE register or NMI bits in STATUS). 399 * Most interrupts go via the 400 * The INT vector is dedicated for hardware interrupts; it is 401 * only referenced if the IV bit in CAUSE is set to 1. 402 */ 403#define MIPS_VEC_RESET 0xBFC00000 /* Hard, soft, or NMI */ 404#define MIPS_VEC_EJTAG 0xBFC00480 405#define MIPS_VEC_TLB 0x80000000 406#define MIPS_VEC_XTLB 0x80000080 407#define MIPS_VEC_CACHE 0x80000100 408#define MIPS_VEC_GENERIC 0x80000180 /* Most exceptions */ 409#define MIPS_VEC_INTERRUPT 0x80000200 410 411/* 412 * The bits in the MIPS3 config register. 413 * 414 * bit 0..5: R/W, Bit 6..31: R/O 415 */ 416 417/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 418#define MIPS3_CONFIG_K0_MASK 0x00000007 419 420/* 421 * R/W Update on Store Conditional 422 * 0: Store Conditional uses coherency algorithm specified by TLB 423 * 1: Store Conditional uses cacheable coherent update on write 424 */ 425#define MIPS3_CONFIG_CU 0x00000008 426 427#define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */ 428#define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */ 429#define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \ 430 (((config) & (bit)) ? 32 : 16) 431 432#define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */ 433#define MIPS3_CONFIG_DC_SHIFT 6 434#define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */ 435#define MIPS3_CONFIG_IC_SHIFT 9 436#define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */ 437 438/* Cache size mode indication: available only on Vr41xx CPUs */ 439#define MIPS3_CONFIG_CS 0x00001000 440#define MIPS3_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */ 441#define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 442 ((base) << (((config) & (mask)) >> (shift))) 443 444/* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */ 445#define MIPS3_CONFIG_SE 0x00001000 446 447/* Block ordering: 0: sequential, 1: sub-block */ 448#define MIPS3_CONFIG_EB 0x00002000 449 450/* ECC mode - 0: ECC mode, 1: parity mode */ 451#define MIPS3_CONFIG_EM 0x00004000 452 453/* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */ 454#define MIPS3_CONFIG_BE 0x00008000 455 456/* Dirty Shared coherency state - 0: enabled, 1: disabled */ 457#define MIPS3_CONFIG_SM 0x00010000 458 459/* Secondary Cache - 0: present, 1: not present */ 460#define MIPS3_CONFIG_SC 0x00020000 461 462/* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */ 463#define MIPS3_CONFIG_EW_MASK 0x000c0000 464#define MIPS3_CONFIG_EW_SHIFT 18 465 466/* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */ 467#define MIPS3_CONFIG_SW 0x00100000 468 469/* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */ 470#define MIPS3_CONFIG_SS 0x00200000 471 472/* Secondary Cache line size */ 473#define MIPS3_CONFIG_SB_MASK 0x00c00000 474#define MIPS3_CONFIG_SB_SHIFT 22 475#define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \ 476 (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT)) 477 478/* Write back data rate */ 479#define MIPS3_CONFIG_EP_MASK 0x0f000000 480#define MIPS3_CONFIG_EP_SHIFT 24 481 482/* System clock ratio - this value is CPU dependent */ 483#define MIPS3_CONFIG_EC_MASK 0x70000000 484#define MIPS3_CONFIG_EC_SHIFT 28 485 486/* Master-Checker Mode - 1: enabled */ 487#define MIPS3_CONFIG_CM 0x80000000 488 489/* 490 * The bits in the MIPS4 config register. 491 */ 492 493/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 494#define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK 495#define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */ 496#define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */ 497#define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */ 498#define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */ 499#define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */ 500#define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */ 501#define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */ 502#define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */ 503#define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */ 504#define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */ 505#define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */ 506#define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */ 507#define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */ 508 509#define MIPS4_CONFIG_DC_SHIFT 26 510#define MIPS4_CONFIG_IC_SHIFT 29 511 512#define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 513 ((base) << (((config) & (mask)) >> (shift))) 514 515#define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \ 516 (((config) & MIPS4_CONFIG_SB) ? 128 : 64) 517 518/* 519 * Location of exception vectors. 520 * 521 * Common vectors: reset and UTLB miss. 522 */ 523#define MIPS_RESET_EXC_VEC ((intptr_t)(int32_t)0xBFC00000) 524#define MIPS_UTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000000) 525 526/* 527 * MIPS-1 general exception vector (everything else) 528 */ 529#define MIPS1_GEN_EXC_VEC ((intptr_t)(int32_t)0x80000080) 530 531/* 532 * MIPS-III exception vectors 533 */ 534#define MIPS3_XTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000080) 535#define MIPS3_CACHE_ERR_EXC_VEC ((intptr_t)(int32_t)0x80000100) 536#define MIPS3_GEN_EXC_VEC ((intptr_t)(int32_t)0x80000180) 537 538/* 539 * TX79 (R5900) exception vectors 540 */ 541#define MIPS_R5900_COUNTER_EXC_VEC 0x80000080 542#define MIPS_R5900_DEBUG_EXC_VEC 0x80000100 543 544/* 545 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector. 546 */ 547#define MIPS3_INTR_EXC_VEC 0x80000200 548 549/* 550 * Coprocessor 0 registers: 551 * 552 * v--- width for mips I,III,32,64 553 * (3=32bit, 6=64bit, i=impl dep) 554 * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index. 555 * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random. 556 * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low. 557 * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended. 558 * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context. 559 * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register. 560 * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number. 561 * 7 MIPS_COP_0_INFO ..33 Info registers 562 * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address. 563 * 9 MIPS_COP_0_COUNT .333 Count register. 564 * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high. 565 * 11 MIPS_COP_0_COMPARE .333 Compare (against Count). 566 * 12 MIPS_COP_0_STATUS 3333 Status register. 567 * 13 MIPS_COP_0_CAUSE 3333 Exception cause register. 568 * 14 MIPS_COP_0_EXC_PC 3636 Exception PC. 569 * 15 MIPS_COP_0_PRID 3333 Processor revision identifier. 570 * 16 MIPS_COP_0_CONFIG 3333 Configuration register. 571 * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1. 572 * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2. 573 * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3. 574 * 16/4 MIPS_COP_0_CONFIG4 ..33 Configuration register 4. 575 * 17 MIPS_COP_0_LLADDR .336 Load Linked Address. 576 * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register. 577 * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register. 578 * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register. 579 * 23 MIPS_COP_0_DEBUG .... Debug JTAG register. 580 * 24 MIPS_COP_0_DEPC .... DEPC JTAG register. 581 * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register. 582 * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register. 583 * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register. 584 * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr). 585 * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr). 586 * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data). 587 * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data). 588 * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr). 589 * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr). 590 * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data). 591 * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data). 592 * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register. 593 * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register. 594 */ 595 596/* Deal with inclusion from an assembly file. */ 597#if defined(_LOCORE) || defined(LOCORE) 598#define _(n) $n 599#else 600#define _(n) n 601#endif 602 603 604#define MIPS_COP_0_TLB_INDEX _(0) 605#define MIPS_COP_0_TLB_RANDOM _(1) 606 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */ 607 608#define MIPS_COP_0_TLB_CONTEXT _(4) 609 /* $5 and $6 new with MIPS-III */ 610#define MIPS_COP_0_BAD_VADDR _(8) 611#define MIPS_COP_0_TLB_HI _(10) 612#define MIPS_COP_0_STATUS _(12) 613#define MIPS_COP_0_CAUSE _(13) 614#define MIPS_COP_0_EXC_PC _(14) 615#define MIPS_COP_0_PRID _(15) 616 617/* MIPS-III */ 618#define MIPS_COP_0_TLB_LO0 _(2) 619#define MIPS_COP_0_TLB_LO1 _(3) 620 621#define MIPS_COP_0_TLB_PG_MASK _(5) 622#define MIPS_COP_0_TLB_WIRED _(6) 623 624#define MIPS_COP_0_COUNT _(9) 625#define MIPS_COP_0_COMPARE _(11) 626 627#define MIPS_COP_0_CONFIG _(16) 628#define MIPS_COP_0_LLADDR _(17) 629#define MIPS_COP_0_WATCH_LO _(18) 630#define MIPS_COP_0_WATCH_HI _(19) 631#define MIPS_COP_0_TLB_XCONTEXT _(20) 632#define MIPS_COP_0_ECC _(26) 633#define MIPS_COP_0_CACHE_ERR _(27) 634#define MIPS_COP_0_TAG_LO _(28) 635#define MIPS_COP_0_TAG_HI _(29) 636#define MIPS_COP_0_ERROR_PC _(30) 637 638/* MIPS32/64 */ 639#define MIPS_COP_0_INFO _(7) 640#define MIPS_COP_0_DEBUG _(23) 641#define MIPS_COP_0_DEPC _(24) 642#define MIPS_COP_0_PERFCNT _(25) 643#define MIPS_COP_0_DATA_LO _(28) 644#define MIPS_COP_0_DATA_HI _(29) 645#define MIPS_COP_0_DESAVE _(31) 646 647/* MIPS32 Config register definitions */ 648#define MIPS_MMU_NONE 0x00 /* No MMU present */ 649#define MIPS_MMU_TLB 0x01 /* Standard TLB */ 650#define MIPS_MMU_BAT 0x02 /* Standard BAT */ 651#define MIPS_MMU_FIXED 0x03 /* Standard fixed mapping */ 652 653#define MIPS_CONFIG0_MT_MASK 0x00000380 /* bits 9..7 MMU Type */ 654#define MIPS_CONFIG0_MT_SHIFT 7 655#define MIPS_CONFIG0_BE 0x00008000 /* data is big-endian */ 656#define MIPS_CONFIG0_VI 0x00000004 /* instruction cache is virtual */ 657 658#define MIPS_CONFIG1_TLBSZ_MASK 0x7E000000 /* bits 30..25 # tlb entries minus one */ 659#define MIPS_CONFIG1_TLBSZ_SHIFT 25 660#define MIPS_MAX_TLB_ENTRIES 128 661 662#define MIPS_CONFIG1_IS_MASK 0x01C00000 /* bits 24..22 icache sets per way */ 663#define MIPS_CONFIG1_IS_SHIFT 22 664#define MIPS_CONFIG1_IL_MASK 0x00380000 /* bits 21..19 icache line size */ 665#define MIPS_CONFIG1_IL_SHIFT 19 666#define MIPS_CONFIG1_IA_MASK 0x00070000 /* bits 18..16 icache associativity */ 667#define MIPS_CONFIG1_IA_SHIFT 16 668#define MIPS_CONFIG1_DS_MASK 0x0000E000 /* bits 15..13 dcache sets per way */ 669#define MIPS_CONFIG1_DS_SHIFT 13 670#define MIPS_CONFIG1_DL_MASK 0x00001C00 /* bits 12..10 dcache line size */ 671#define MIPS_CONFIG1_DL_SHIFT 10 672#define MIPS_CONFIG1_DA_MASK 0x00000380 /* bits 9.. 7 dcache associativity */ 673#define MIPS_CONFIG1_DA_SHIFT 7 674#define MIPS_CONFIG1_LOWBITS 0x0000007F 675#define MIPS_CONFIG1_C2 0x00000040 /* Coprocessor 2 implemented */ 676#define MIPS_CONFIG1_MD 0x00000020 /* MDMX ASE implemented (MIPS64) */ 677#define MIPS_CONFIG1_PC 0x00000010 /* Performance counters implemented */ 678#define MIPS_CONFIG1_WR 0x00000008 /* Watch registers implemented */ 679#define MIPS_CONFIG1_CA 0x00000004 /* MIPS16e ISA implemented */ 680#define MIPS_CONFIG1_EP 0x00000002 /* EJTAG implemented */ 681#define MIPS_CONFIG1_FP 0x00000001 /* FPU implemented */ 682 683#define MIPS_CONFIG4_MMUSIZEEXT 0x000000FF /* bits 7.. 0 MMU Size Extension */ 684#define MIPS_CONFIG4_MMUEXTDEF 0x0000C000 /* bits 15.14 MMU Extension Definition */ 685#define MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT 0x00004000 /* This values denotes CONFIG4 bits */ 686 687/* 688 * Values for the code field in a break instruction. 689 */ 690#define MIPS_BREAK_INSTR 0x0000000d 691#define MIPS_BREAK_VAL_MASK 0x03ff0000 692#define MIPS_BREAK_VAL_SHIFT 16 693#define MIPS_BREAK_KDB_VAL 512 694#define MIPS_BREAK_SSTEP_VAL 513 695#define MIPS_BREAK_BRKPT_VAL 514 696#define MIPS_BREAK_SOVER_VAL 515 697#define MIPS_BREAK_DDB_VAL 516 698#define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \ 699 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT)) 700#define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \ 701 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT)) 702#define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \ 703 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT)) 704#define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \ 705 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT)) 706#define MIPS_BREAK_DDB (MIPS_BREAK_INSTR | \ 707 (MIPS_BREAK_DDB_VAL << MIPS_BREAK_VAL_SHIFT)) 708 709/* 710 * Mininum and maximum cache sizes. 711 */ 712#define MIPS_MIN_CACHE_SIZE (16 * 1024) 713#define MIPS_MAX_CACHE_SIZE (256 * 1024) 714#define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */ 715 716/* 717 * The floating point version and status registers. 718 */ 719#define MIPS_FPU_ID $0 720#define MIPS_FPU_CSR $31 721 722/* 723 * The floating point coprocessor status register bits. 724 */ 725#define MIPS_FPU_ROUNDING_BITS 0x00000003 726#define MIPS_FPU_ROUND_RN 0x00000000 727#define MIPS_FPU_ROUND_RZ 0x00000001 728#define MIPS_FPU_ROUND_RP 0x00000002 729#define MIPS_FPU_ROUND_RM 0x00000003 730#define MIPS_FPU_STICKY_BITS 0x0000007c 731#define MIPS_FPU_STICKY_INEXACT 0x00000004 732#define MIPS_FPU_STICKY_UNDERFLOW 0x00000008 733#define MIPS_FPU_STICKY_OVERFLOW 0x00000010 734#define MIPS_FPU_STICKY_DIV0 0x00000020 735#define MIPS_FPU_STICKY_INVALID 0x00000040 736#define MIPS_FPU_ENABLE_BITS 0x00000f80 737#define MIPS_FPU_ENABLE_INEXACT 0x00000080 738#define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100 739#define MIPS_FPU_ENABLE_OVERFLOW 0x00000200 740#define MIPS_FPU_ENABLE_DIV0 0x00000400 741#define MIPS_FPU_ENABLE_INVALID 0x00000800 742#define MIPS_FPU_EXCEPTION_BITS 0x0003f000 743#define MIPS_FPU_EXCEPTION_INEXACT 0x00001000 744#define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000 745#define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000 746#define MIPS_FPU_EXCEPTION_DIV0 0x00008000 747#define MIPS_FPU_EXCEPTION_INVALID 0x00010000 748#define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000 749#define MIPS_FPU_COND_BIT 0x00800000 750#define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ 751#define MIPS1_FPC_MBZ_BITS 0xff7c0000 752#define MIPS3_FPC_MBZ_BITS 0xfe7c0000 753 754 755/* 756 * Constants to determine if have a floating point instruction. 757 */ 758#define MIPS_OPCODE_SHIFT 26 759#define MIPS_OPCODE_C1 0x11 760 761 762/* 763 * The low part of the TLB entry. 764 */ 765#define MIPS1_TLB_PFN 0xfffff000 766#define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800 767#define MIPS1_TLB_DIRTY_BIT 0x00000400 768#define MIPS1_TLB_VALID_BIT 0x00000200 769#define MIPS1_TLB_GLOBAL_BIT 0x00000100 770 771#define MIPS3_TLB_PFN 0x3fffffc0 772#define MIPS3_TLB_ATTR_MASK 0x00000038 773#define MIPS3_TLB_ATTR_SHIFT 3 774#define MIPS3_TLB_DIRTY_BIT 0x00000004 775#define MIPS3_TLB_VALID_BIT 0x00000002 776#define MIPS3_TLB_GLOBAL_BIT 0x00000001 777 778#define MIPS1_TLB_PHYS_PAGE_SHIFT 12 779#define MIPS3_TLB_PHYS_PAGE_SHIFT 6 780#define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN 781#define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN 782#define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT 783#define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT 784 785/* 786 * MIPS3_TLB_ATTR values - coherency algorithm: 787 * 0: cacheable, noncoherent, write-through, no write allocate 788 * 1: cacheable, noncoherent, write-through, write allocate 789 * 2: uncached 790 * 3: cacheable, noncoherent, write-back (noncoherent) 791 * 4: cacheable, coherent, write-back, exclusive (exclusive) 792 * 5: cacheable, coherent, write-back, exclusive on write (sharable) 793 * 6: cacheable, coherent, write-back, update on write (update) 794 * 7: uncached, accelerated (gather STORE operations) 795 */ 796#define MIPS3_TLB_ATTR_WT 0 /* IDT */ 797#define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */ 798#define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */ 799#define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */ 800#define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */ 801#define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */ 802#define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */ 803#define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */ 804 805 806/* 807 * The high part of the TLB entry. 808 */ 809#define MIPS1_TLB_VPN 0xfffff000 810#define MIPS1_TLB_PID 0x00000fc0 811#define MIPS1_TLB_PID_SHIFT 6 812 813#define MIPS3_TLB_VPN2 0xffffe000 814#define MIPS3_TLB_ASID 0x000000ff 815 816#define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN 817#define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2 818#define MIPS3_TLB_PID MIPS3_TLB_ASID 819#define MIPS_TLB_VIRT_PAGE_SHIFT 12 820 821/* 822 * r3000: shift count to put the index in the right spot. 823 */ 824#define MIPS1_TLB_INDEX_SHIFT 8 825 826/* 827 * The first TLB that write random hits. 828 */ 829#define MIPS1_TLB_FIRST_RAND_ENTRY 8 830#define MIPS3_TLB_WIRED_UPAGES 1 831 832/* 833 * The number of process id entries. 834 */ 835#define MIPS1_TLB_NUM_PIDS 64 836#define MIPS3_TLB_NUM_ASIDS 256 837 838/* 839 * Patch codes to hide CPU design differences between MIPS1 and MIPS3. 840 */ 841 842/* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */ 843 844#if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ 845 && defined(MIPS1) /* XXX simonb must be neater! */ 846#define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT 847#define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS 848#endif 849 850#if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ 851 && !defined(MIPS1) /* XXX simonb must be neater! */ 852#define MIPS_TLB_PID_SHIFT 0 853#define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS 854#endif 855 856 857#if !defined(MIPS_TLB_PID_SHIFT) 858#define MIPS_TLB_PID_SHIFT \ 859 ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT) 860 861#define MIPS_TLB_NUM_PIDS \ 862 ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS) 863#endif 864 865/* 866 * CPU processor revision IDs for company ID == 0 (non mips32/64 chips) 867 */ 868#define MIPS_R2000 0x01 /* MIPS R2000 ISA I */ 869#define MIPS_R3000 0x02 /* MIPS R3000 ISA I */ 870#define MIPS_R6000 0x03 /* MIPS R6000 ISA II */ 871#define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */ 872#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */ 873#define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */ 874#define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */ 875#define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */ 876#define MIPS_R4200 0x0a /* NEC VR4200 ISA III */ 877#define MIPS_R4300 0x0b /* NEC VR4300 ISA III */ 878#define MIPS_R4100 0x0c /* NEC VR4100 ISA III */ 879#define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */ 880#define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */ 881#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 882#define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */ 883#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 884#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ 885#define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */ 886#define MIPS_R4650 0x22 /* QED R4650 ISA III */ 887#define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */ 888#define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */ 889#define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */ 890#define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */ 891#define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */ 892#define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */ 893#define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */ 894#define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */ 895#define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */ 896#define MIPS_TX7900 0x38 /* Toshiba TX79 ISA III+*/ 897#define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */ 898#define MIPS_R5500 0x55 /* NEC VR5500 ISA IV */ 899 900/* 901 * CPU revision IDs for some prehistoric processors. 902 */ 903 904/* For MIPS_R3000 */ 905#define MIPS_REV_R3000 0x20 906#define MIPS_REV_R3000A 0x30 907 908/* For MIPS_TX3900 */ 909#define MIPS_REV_TX3912 0x10 910#define MIPS_REV_TX3922 0x30 911#define MIPS_REV_TX3927 0x40 912 913/* For MIPS_R4000 */ 914#define MIPS_REV_R4000_A 0x00 915#define MIPS_REV_R4000_B 0x22 916#define MIPS_REV_R4000_C 0x30 917#define MIPS_REV_R4400_A 0x40 918#define MIPS_REV_R4400_B 0x50 919#define MIPS_REV_R4400_C 0x60 920 921/* For MIPS_TX4900 */ 922#define MIPS_REV_TX4927 0x22 923 924/* 925 * CPU processor revision IDs for company ID == 1 (MIPS) 926 */ 927#define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */ 928#define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */ 929#define MIPS_20Kc 0x82 /* MIPS 20Kc ISA 64 */ 930#define MIPS_4Kmp 0x83 /* MIPS 4Km/4Kp ISA 32 */ 931#define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */ 932#define MIPS_4KEmp 0x85 /* MIPS 4KEm/4KEp ISA 32 */ 933#define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */ 934#define MIPS_M4K 0x87 /* MIPS M4K ISA 32 Rel 2 */ 935#define MIPS_25Kf 0x88 /* MIPS 25Kf ISA 64 */ 936#define MIPS_5KE 0x89 /* MIPS 5KE ISA 64 Rel 2 */ 937#define MIPS_4KEc_R2 0x90 /* MIPS 4KEc_R2 ISA 32 Rel 2 */ 938#define MIPS_4KEmp_R2 0x91 /* MIPS 4KEm/4KEp_R2 ISA 32 Rel 2 */ 939#define MIPS_4KSd 0x92 /* MIPS 4KSd ISA 32 Rel 2 */ 940#define MIPS_24K 0x93 /* MIPS 24Kc/24Kf ISA 32 Rel 2 */ 941#define MIPS_34K 0x95 /* MIPS 34K ISA 32 R2 MT */ 942#define MIPS_24KE 0x96 /* MIPS 24KEc ISA 32 Rel 2 */ 943#define MIPS_74K 0x97 /* MIPS 74Kc/74Kf ISA 32 Rel 2 */ 944 945/* 946 * AMD (company ID 3) use the processor ID field to donote the CPU core 947 * revision and the company options field do donate the SOC chip type. 948 */ 949 950/* CPU processor revision IDs */ 951#define MIPS_AU_REV1 0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */ 952#define MIPS_AU_REV2 0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */ 953 954/* CPU company options IDs */ 955#define MIPS_AU1000 0x00 956#define MIPS_AU1500 0x01 957#define MIPS_AU1100 0x02 958#define MIPS_AU1550 0x03 959 960/* 961 * CPU processor revision IDs for company ID == 4 (Broadcom) 962 */ 963#define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */ 964 965/* 966 * CPU processor revision IDs for company ID == 5 (SandCraft) 967 */ 968#define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */ 969 970/* 971 * FPU processor revision ID 972 */ 973#define MIPS_SOFT 0x00 /* Software emulation ISA I */ 974#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 975#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 976#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 977#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 978#define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */ 979#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 980#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ 981 982#ifdef ENABLE_MIPS_TX3900 983#include <mips/r3900regs.h> 984#endif 985#ifdef MIPS3_5900 986#include <mips/r5900regs.h> 987#endif 988#ifdef MIPS64_SB1 989#include <mips/sb1regs.h> 990#endif 991 992#endif /* _MIPS_CPUREGS_H_ */
| 237 238/* 239 * The bits in the status register. All bits are active when set to 1. 240 * 241 * R3000 status register fields: 242 * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors. 243 * MIPS_SR_TS TLB shutdown. 244 * 245 * MIPS_SR_INT_IE Master (current) interrupt enable bit. 246 * 247 * Differences: 248 * r3k has cache control is via frobbing SR register bits, whereas the 249 * r4k cache control is via explicit instructions. 250 * r3k has a 3-entry stack of kernel/user bits, whereas the 251 * r4k has kernel/supervisor/user. 252 */ 253#define MIPS_SR_COP_USABILITY 0xf0000000 254#define MIPS_SR_COP_0_BIT 0x10000000 255#define MIPS_SR_COP_1_BIT 0x20000000 256#define MIPS_SR_COP_2_BIT 0x40000000 257 258 /* r4k and r3k differences, see below */ 259 260#define MIPS_SR_MX 0x01000000 /* MIPS64 */ 261#define MIPS_SR_PX 0x00800000 /* MIPS64 */ 262#define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */ 263#define MIPS_SR_TS 0x00200000 264#define MIPS_SR_DE 0x00010000 265 266#define MIPS_SR_INT_IE 0x00000001 267/*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ 268#define MIPS_SR_INT_MASK 0x0000ff00 269 270/* 271 * The R2000/R3000-specific status register bit definitions. 272 * all bits are active when set to 1. 273 * 274 * MIPS_SR_PARITY_ERR Parity error. 275 * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 276 * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits. 277 * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache. 278 * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory. 279 * Interrupt enable bits defined below. 280 * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 281 * MIPS_SR_INT_ENA_OLD Old interrupt enable bit. 282 * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 283 * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit. 284 * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 285 */ 286 287#define MIPS1_PARITY_ERR 0x00100000 288#define MIPS1_CACHE_MISS 0x00080000 289#define MIPS1_PARITY_ZERO 0x00040000 290#define MIPS1_SWAP_CACHES 0x00020000 291#define MIPS1_ISOL_CACHES 0x00010000 292 293#define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/ 294#define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/ 295#define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/ 296#define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/ 297#define MIPS1_SR_KU_CUR 0x00000002 /* current KU */ 298 299/* backwards compatibility */ 300#define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR 301#define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS 302#define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO 303#define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES 304#define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES 305 306#define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD 307#define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD 308#define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV 309#define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR 310#define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV 311 312/* 313 * R4000 status register bit definitons, 314 * where different from r2000/r3000. 315 */ 316#define MIPS3_SR_XX 0x80000000 317#define MIPS3_SR_RP 0x08000000 318#define MIPS3_SR_FR 0x04000000 319#define MIPS3_SR_RE 0x02000000 320 321#define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */ 322#define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */ 323#define MIPS3_SR_SR 0x00100000 324#define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */ 325#define MIPS3_SR_DIAG_CH 0x00040000 326#define MIPS3_SR_DIAG_CE 0x00020000 327#define MIPS3_SR_DIAG_PE 0x00010000 328#define MIPS3_SR_EIE 0x00010000 /* TX79/R5900 */ 329#define MIPS3_SR_KX 0x00000080 330#define MIPS3_SR_SX 0x00000040 331#define MIPS3_SR_UX 0x00000020 332#define MIPS3_SR_KSU_MASK 0x00000018 333#define MIPS3_SR_KSU_USER 0x00000010 334#define MIPS3_SR_KSU_SUPER 0x00000008 335#define MIPS3_SR_KSU_KERNEL 0x00000000 336#define MIPS3_SR_ERL 0x00000004 337#define MIPS3_SR_EXL 0x00000002 338 339#ifdef MIPS3_5900 340#undef MIPS_SR_INT_IE 341#define MIPS_SR_INT_IE 0x00010001 /* XXX */ 342#endif 343 344#define MIPS_SR_SOFT_RESET MIPS3_SR_SR 345#define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH 346#define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE 347#define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE 348#define MIPS_SR_KX MIPS3_SR_KX 349#define MIPS_SR_SX MIPS3_SR_SX 350#define MIPS_SR_UX MIPS3_SR_UX 351 352#define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK 353#define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER 354#define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER 355#define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL 356#define MIPS_SR_ERL MIPS3_SR_ERL 357#define MIPS_SR_EXL MIPS3_SR_EXL 358 359 360/* 361 * The interrupt masks. 362 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 363 */ 364#define MIPS_INT_MASK 0xff00 365#define MIPS_INT_MASK_5 0x8000 366#define MIPS_INT_MASK_4 0x4000 367#define MIPS_INT_MASK_3 0x2000 368#define MIPS_INT_MASK_2 0x1000 369#define MIPS_INT_MASK_1 0x0800 370#define MIPS_INT_MASK_0 0x0400 371#define MIPS_HARD_INT_MASK 0xfc00 372#define MIPS_SOFT_INT_MASK_1 0x0200 373#define MIPS_SOFT_INT_MASK_0 0x0100 374 375/* 376 * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can 377 * choose to enable this interrupt. 378 */ 379#if defined(MIPS3_ENABLE_CLOCK_INTR) 380#define MIPS3_INT_MASK MIPS_INT_MASK 381#define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK 382#else 383#define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5) 384#define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5) 385#endif 386 387/* 388 * The bits in the context register. 389 */ 390#define MIPS1_CNTXT_PTE_BASE 0xFFE00000 391#define MIPS1_CNTXT_BAD_VPN 0x001FFFFC 392 393#define MIPS3_CNTXT_PTE_BASE 0xFF800000 394#define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0 395 396/* 397 * Location of MIPS32 exception vectors. Most are multiplexed in 398 * the sense that further decoding is necessary (e.g. reading the 399 * CAUSE register or NMI bits in STATUS). 400 * Most interrupts go via the 401 * The INT vector is dedicated for hardware interrupts; it is 402 * only referenced if the IV bit in CAUSE is set to 1. 403 */ 404#define MIPS_VEC_RESET 0xBFC00000 /* Hard, soft, or NMI */ 405#define MIPS_VEC_EJTAG 0xBFC00480 406#define MIPS_VEC_TLB 0x80000000 407#define MIPS_VEC_XTLB 0x80000080 408#define MIPS_VEC_CACHE 0x80000100 409#define MIPS_VEC_GENERIC 0x80000180 /* Most exceptions */ 410#define MIPS_VEC_INTERRUPT 0x80000200 411 412/* 413 * The bits in the MIPS3 config register. 414 * 415 * bit 0..5: R/W, Bit 6..31: R/O 416 */ 417 418/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 419#define MIPS3_CONFIG_K0_MASK 0x00000007 420 421/* 422 * R/W Update on Store Conditional 423 * 0: Store Conditional uses coherency algorithm specified by TLB 424 * 1: Store Conditional uses cacheable coherent update on write 425 */ 426#define MIPS3_CONFIG_CU 0x00000008 427 428#define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */ 429#define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */ 430#define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \ 431 (((config) & (bit)) ? 32 : 16) 432 433#define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */ 434#define MIPS3_CONFIG_DC_SHIFT 6 435#define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */ 436#define MIPS3_CONFIG_IC_SHIFT 9 437#define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */ 438 439/* Cache size mode indication: available only on Vr41xx CPUs */ 440#define MIPS3_CONFIG_CS 0x00001000 441#define MIPS3_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */ 442#define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 443 ((base) << (((config) & (mask)) >> (shift))) 444 445/* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */ 446#define MIPS3_CONFIG_SE 0x00001000 447 448/* Block ordering: 0: sequential, 1: sub-block */ 449#define MIPS3_CONFIG_EB 0x00002000 450 451/* ECC mode - 0: ECC mode, 1: parity mode */ 452#define MIPS3_CONFIG_EM 0x00004000 453 454/* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */ 455#define MIPS3_CONFIG_BE 0x00008000 456 457/* Dirty Shared coherency state - 0: enabled, 1: disabled */ 458#define MIPS3_CONFIG_SM 0x00010000 459 460/* Secondary Cache - 0: present, 1: not present */ 461#define MIPS3_CONFIG_SC 0x00020000 462 463/* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */ 464#define MIPS3_CONFIG_EW_MASK 0x000c0000 465#define MIPS3_CONFIG_EW_SHIFT 18 466 467/* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */ 468#define MIPS3_CONFIG_SW 0x00100000 469 470/* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */ 471#define MIPS3_CONFIG_SS 0x00200000 472 473/* Secondary Cache line size */ 474#define MIPS3_CONFIG_SB_MASK 0x00c00000 475#define MIPS3_CONFIG_SB_SHIFT 22 476#define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \ 477 (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT)) 478 479/* Write back data rate */ 480#define MIPS3_CONFIG_EP_MASK 0x0f000000 481#define MIPS3_CONFIG_EP_SHIFT 24 482 483/* System clock ratio - this value is CPU dependent */ 484#define MIPS3_CONFIG_EC_MASK 0x70000000 485#define MIPS3_CONFIG_EC_SHIFT 28 486 487/* Master-Checker Mode - 1: enabled */ 488#define MIPS3_CONFIG_CM 0x80000000 489 490/* 491 * The bits in the MIPS4 config register. 492 */ 493 494/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 495#define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK 496#define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */ 497#define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */ 498#define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */ 499#define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */ 500#define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */ 501#define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */ 502#define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */ 503#define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */ 504#define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */ 505#define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */ 506#define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */ 507#define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */ 508#define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */ 509 510#define MIPS4_CONFIG_DC_SHIFT 26 511#define MIPS4_CONFIG_IC_SHIFT 29 512 513#define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 514 ((base) << (((config) & (mask)) >> (shift))) 515 516#define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \ 517 (((config) & MIPS4_CONFIG_SB) ? 128 : 64) 518 519/* 520 * Location of exception vectors. 521 * 522 * Common vectors: reset and UTLB miss. 523 */ 524#define MIPS_RESET_EXC_VEC ((intptr_t)(int32_t)0xBFC00000) 525#define MIPS_UTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000000) 526 527/* 528 * MIPS-1 general exception vector (everything else) 529 */ 530#define MIPS1_GEN_EXC_VEC ((intptr_t)(int32_t)0x80000080) 531 532/* 533 * MIPS-III exception vectors 534 */ 535#define MIPS3_XTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000080) 536#define MIPS3_CACHE_ERR_EXC_VEC ((intptr_t)(int32_t)0x80000100) 537#define MIPS3_GEN_EXC_VEC ((intptr_t)(int32_t)0x80000180) 538 539/* 540 * TX79 (R5900) exception vectors 541 */ 542#define MIPS_R5900_COUNTER_EXC_VEC 0x80000080 543#define MIPS_R5900_DEBUG_EXC_VEC 0x80000100 544 545/* 546 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector. 547 */ 548#define MIPS3_INTR_EXC_VEC 0x80000200 549 550/* 551 * Coprocessor 0 registers: 552 * 553 * v--- width for mips I,III,32,64 554 * (3=32bit, 6=64bit, i=impl dep) 555 * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index. 556 * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random. 557 * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low. 558 * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended. 559 * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context. 560 * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register. 561 * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number. 562 * 7 MIPS_COP_0_INFO ..33 Info registers 563 * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address. 564 * 9 MIPS_COP_0_COUNT .333 Count register. 565 * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high. 566 * 11 MIPS_COP_0_COMPARE .333 Compare (against Count). 567 * 12 MIPS_COP_0_STATUS 3333 Status register. 568 * 13 MIPS_COP_0_CAUSE 3333 Exception cause register. 569 * 14 MIPS_COP_0_EXC_PC 3636 Exception PC. 570 * 15 MIPS_COP_0_PRID 3333 Processor revision identifier. 571 * 16 MIPS_COP_0_CONFIG 3333 Configuration register. 572 * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1. 573 * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2. 574 * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3. 575 * 16/4 MIPS_COP_0_CONFIG4 ..33 Configuration register 4. 576 * 17 MIPS_COP_0_LLADDR .336 Load Linked Address. 577 * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register. 578 * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register. 579 * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register. 580 * 23 MIPS_COP_0_DEBUG .... Debug JTAG register. 581 * 24 MIPS_COP_0_DEPC .... DEPC JTAG register. 582 * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register. 583 * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register. 584 * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register. 585 * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr). 586 * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr). 587 * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data). 588 * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data). 589 * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr). 590 * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr). 591 * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data). 592 * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data). 593 * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register. 594 * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register. 595 */ 596 597/* Deal with inclusion from an assembly file. */ 598#if defined(_LOCORE) || defined(LOCORE) 599#define _(n) $n 600#else 601#define _(n) n 602#endif 603 604 605#define MIPS_COP_0_TLB_INDEX _(0) 606#define MIPS_COP_0_TLB_RANDOM _(1) 607 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */ 608 609#define MIPS_COP_0_TLB_CONTEXT _(4) 610 /* $5 and $6 new with MIPS-III */ 611#define MIPS_COP_0_BAD_VADDR _(8) 612#define MIPS_COP_0_TLB_HI _(10) 613#define MIPS_COP_0_STATUS _(12) 614#define MIPS_COP_0_CAUSE _(13) 615#define MIPS_COP_0_EXC_PC _(14) 616#define MIPS_COP_0_PRID _(15) 617 618/* MIPS-III */ 619#define MIPS_COP_0_TLB_LO0 _(2) 620#define MIPS_COP_0_TLB_LO1 _(3) 621 622#define MIPS_COP_0_TLB_PG_MASK _(5) 623#define MIPS_COP_0_TLB_WIRED _(6) 624 625#define MIPS_COP_0_COUNT _(9) 626#define MIPS_COP_0_COMPARE _(11) 627 628#define MIPS_COP_0_CONFIG _(16) 629#define MIPS_COP_0_LLADDR _(17) 630#define MIPS_COP_0_WATCH_LO _(18) 631#define MIPS_COP_0_WATCH_HI _(19) 632#define MIPS_COP_0_TLB_XCONTEXT _(20) 633#define MIPS_COP_0_ECC _(26) 634#define MIPS_COP_0_CACHE_ERR _(27) 635#define MIPS_COP_0_TAG_LO _(28) 636#define MIPS_COP_0_TAG_HI _(29) 637#define MIPS_COP_0_ERROR_PC _(30) 638 639/* MIPS32/64 */ 640#define MIPS_COP_0_INFO _(7) 641#define MIPS_COP_0_DEBUG _(23) 642#define MIPS_COP_0_DEPC _(24) 643#define MIPS_COP_0_PERFCNT _(25) 644#define MIPS_COP_0_DATA_LO _(28) 645#define MIPS_COP_0_DATA_HI _(29) 646#define MIPS_COP_0_DESAVE _(31) 647 648/* MIPS32 Config register definitions */ 649#define MIPS_MMU_NONE 0x00 /* No MMU present */ 650#define MIPS_MMU_TLB 0x01 /* Standard TLB */ 651#define MIPS_MMU_BAT 0x02 /* Standard BAT */ 652#define MIPS_MMU_FIXED 0x03 /* Standard fixed mapping */ 653 654#define MIPS_CONFIG0_MT_MASK 0x00000380 /* bits 9..7 MMU Type */ 655#define MIPS_CONFIG0_MT_SHIFT 7 656#define MIPS_CONFIG0_BE 0x00008000 /* data is big-endian */ 657#define MIPS_CONFIG0_VI 0x00000004 /* instruction cache is virtual */ 658 659#define MIPS_CONFIG1_TLBSZ_MASK 0x7E000000 /* bits 30..25 # tlb entries minus one */ 660#define MIPS_CONFIG1_TLBSZ_SHIFT 25 661#define MIPS_MAX_TLB_ENTRIES 128 662 663#define MIPS_CONFIG1_IS_MASK 0x01C00000 /* bits 24..22 icache sets per way */ 664#define MIPS_CONFIG1_IS_SHIFT 22 665#define MIPS_CONFIG1_IL_MASK 0x00380000 /* bits 21..19 icache line size */ 666#define MIPS_CONFIG1_IL_SHIFT 19 667#define MIPS_CONFIG1_IA_MASK 0x00070000 /* bits 18..16 icache associativity */ 668#define MIPS_CONFIG1_IA_SHIFT 16 669#define MIPS_CONFIG1_DS_MASK 0x0000E000 /* bits 15..13 dcache sets per way */ 670#define MIPS_CONFIG1_DS_SHIFT 13 671#define MIPS_CONFIG1_DL_MASK 0x00001C00 /* bits 12..10 dcache line size */ 672#define MIPS_CONFIG1_DL_SHIFT 10 673#define MIPS_CONFIG1_DA_MASK 0x00000380 /* bits 9.. 7 dcache associativity */ 674#define MIPS_CONFIG1_DA_SHIFT 7 675#define MIPS_CONFIG1_LOWBITS 0x0000007F 676#define MIPS_CONFIG1_C2 0x00000040 /* Coprocessor 2 implemented */ 677#define MIPS_CONFIG1_MD 0x00000020 /* MDMX ASE implemented (MIPS64) */ 678#define MIPS_CONFIG1_PC 0x00000010 /* Performance counters implemented */ 679#define MIPS_CONFIG1_WR 0x00000008 /* Watch registers implemented */ 680#define MIPS_CONFIG1_CA 0x00000004 /* MIPS16e ISA implemented */ 681#define MIPS_CONFIG1_EP 0x00000002 /* EJTAG implemented */ 682#define MIPS_CONFIG1_FP 0x00000001 /* FPU implemented */ 683 684#define MIPS_CONFIG4_MMUSIZEEXT 0x000000FF /* bits 7.. 0 MMU Size Extension */ 685#define MIPS_CONFIG4_MMUEXTDEF 0x0000C000 /* bits 15.14 MMU Extension Definition */ 686#define MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT 0x00004000 /* This values denotes CONFIG4 bits */ 687 688/* 689 * Values for the code field in a break instruction. 690 */ 691#define MIPS_BREAK_INSTR 0x0000000d 692#define MIPS_BREAK_VAL_MASK 0x03ff0000 693#define MIPS_BREAK_VAL_SHIFT 16 694#define MIPS_BREAK_KDB_VAL 512 695#define MIPS_BREAK_SSTEP_VAL 513 696#define MIPS_BREAK_BRKPT_VAL 514 697#define MIPS_BREAK_SOVER_VAL 515 698#define MIPS_BREAK_DDB_VAL 516 699#define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \ 700 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT)) 701#define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \ 702 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT)) 703#define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \ 704 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT)) 705#define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \ 706 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT)) 707#define MIPS_BREAK_DDB (MIPS_BREAK_INSTR | \ 708 (MIPS_BREAK_DDB_VAL << MIPS_BREAK_VAL_SHIFT)) 709 710/* 711 * Mininum and maximum cache sizes. 712 */ 713#define MIPS_MIN_CACHE_SIZE (16 * 1024) 714#define MIPS_MAX_CACHE_SIZE (256 * 1024) 715#define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */ 716 717/* 718 * The floating point version and status registers. 719 */ 720#define MIPS_FPU_ID $0 721#define MIPS_FPU_CSR $31 722 723/* 724 * The floating point coprocessor status register bits. 725 */ 726#define MIPS_FPU_ROUNDING_BITS 0x00000003 727#define MIPS_FPU_ROUND_RN 0x00000000 728#define MIPS_FPU_ROUND_RZ 0x00000001 729#define MIPS_FPU_ROUND_RP 0x00000002 730#define MIPS_FPU_ROUND_RM 0x00000003 731#define MIPS_FPU_STICKY_BITS 0x0000007c 732#define MIPS_FPU_STICKY_INEXACT 0x00000004 733#define MIPS_FPU_STICKY_UNDERFLOW 0x00000008 734#define MIPS_FPU_STICKY_OVERFLOW 0x00000010 735#define MIPS_FPU_STICKY_DIV0 0x00000020 736#define MIPS_FPU_STICKY_INVALID 0x00000040 737#define MIPS_FPU_ENABLE_BITS 0x00000f80 738#define MIPS_FPU_ENABLE_INEXACT 0x00000080 739#define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100 740#define MIPS_FPU_ENABLE_OVERFLOW 0x00000200 741#define MIPS_FPU_ENABLE_DIV0 0x00000400 742#define MIPS_FPU_ENABLE_INVALID 0x00000800 743#define MIPS_FPU_EXCEPTION_BITS 0x0003f000 744#define MIPS_FPU_EXCEPTION_INEXACT 0x00001000 745#define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000 746#define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000 747#define MIPS_FPU_EXCEPTION_DIV0 0x00008000 748#define MIPS_FPU_EXCEPTION_INVALID 0x00010000 749#define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000 750#define MIPS_FPU_COND_BIT 0x00800000 751#define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ 752#define MIPS1_FPC_MBZ_BITS 0xff7c0000 753#define MIPS3_FPC_MBZ_BITS 0xfe7c0000 754 755 756/* 757 * Constants to determine if have a floating point instruction. 758 */ 759#define MIPS_OPCODE_SHIFT 26 760#define MIPS_OPCODE_C1 0x11 761 762 763/* 764 * The low part of the TLB entry. 765 */ 766#define MIPS1_TLB_PFN 0xfffff000 767#define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800 768#define MIPS1_TLB_DIRTY_BIT 0x00000400 769#define MIPS1_TLB_VALID_BIT 0x00000200 770#define MIPS1_TLB_GLOBAL_BIT 0x00000100 771 772#define MIPS3_TLB_PFN 0x3fffffc0 773#define MIPS3_TLB_ATTR_MASK 0x00000038 774#define MIPS3_TLB_ATTR_SHIFT 3 775#define MIPS3_TLB_DIRTY_BIT 0x00000004 776#define MIPS3_TLB_VALID_BIT 0x00000002 777#define MIPS3_TLB_GLOBAL_BIT 0x00000001 778 779#define MIPS1_TLB_PHYS_PAGE_SHIFT 12 780#define MIPS3_TLB_PHYS_PAGE_SHIFT 6 781#define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN 782#define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN 783#define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT 784#define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT 785 786/* 787 * MIPS3_TLB_ATTR values - coherency algorithm: 788 * 0: cacheable, noncoherent, write-through, no write allocate 789 * 1: cacheable, noncoherent, write-through, write allocate 790 * 2: uncached 791 * 3: cacheable, noncoherent, write-back (noncoherent) 792 * 4: cacheable, coherent, write-back, exclusive (exclusive) 793 * 5: cacheable, coherent, write-back, exclusive on write (sharable) 794 * 6: cacheable, coherent, write-back, update on write (update) 795 * 7: uncached, accelerated (gather STORE operations) 796 */ 797#define MIPS3_TLB_ATTR_WT 0 /* IDT */ 798#define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */ 799#define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */ 800#define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */ 801#define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */ 802#define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */ 803#define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */ 804#define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */ 805 806 807/* 808 * The high part of the TLB entry. 809 */ 810#define MIPS1_TLB_VPN 0xfffff000 811#define MIPS1_TLB_PID 0x00000fc0 812#define MIPS1_TLB_PID_SHIFT 6 813 814#define MIPS3_TLB_VPN2 0xffffe000 815#define MIPS3_TLB_ASID 0x000000ff 816 817#define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN 818#define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2 819#define MIPS3_TLB_PID MIPS3_TLB_ASID 820#define MIPS_TLB_VIRT_PAGE_SHIFT 12 821 822/* 823 * r3000: shift count to put the index in the right spot. 824 */ 825#define MIPS1_TLB_INDEX_SHIFT 8 826 827/* 828 * The first TLB that write random hits. 829 */ 830#define MIPS1_TLB_FIRST_RAND_ENTRY 8 831#define MIPS3_TLB_WIRED_UPAGES 1 832 833/* 834 * The number of process id entries. 835 */ 836#define MIPS1_TLB_NUM_PIDS 64 837#define MIPS3_TLB_NUM_ASIDS 256 838 839/* 840 * Patch codes to hide CPU design differences between MIPS1 and MIPS3. 841 */ 842 843/* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */ 844 845#if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ 846 && defined(MIPS1) /* XXX simonb must be neater! */ 847#define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT 848#define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS 849#endif 850 851#if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ 852 && !defined(MIPS1) /* XXX simonb must be neater! */ 853#define MIPS_TLB_PID_SHIFT 0 854#define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS 855#endif 856 857 858#if !defined(MIPS_TLB_PID_SHIFT) 859#define MIPS_TLB_PID_SHIFT \ 860 ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT) 861 862#define MIPS_TLB_NUM_PIDS \ 863 ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS) 864#endif 865 866/* 867 * CPU processor revision IDs for company ID == 0 (non mips32/64 chips) 868 */ 869#define MIPS_R2000 0x01 /* MIPS R2000 ISA I */ 870#define MIPS_R3000 0x02 /* MIPS R3000 ISA I */ 871#define MIPS_R6000 0x03 /* MIPS R6000 ISA II */ 872#define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */ 873#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */ 874#define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */ 875#define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */ 876#define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */ 877#define MIPS_R4200 0x0a /* NEC VR4200 ISA III */ 878#define MIPS_R4300 0x0b /* NEC VR4300 ISA III */ 879#define MIPS_R4100 0x0c /* NEC VR4100 ISA III */ 880#define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */ 881#define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */ 882#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 883#define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */ 884#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 885#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ 886#define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */ 887#define MIPS_R4650 0x22 /* QED R4650 ISA III */ 888#define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */ 889#define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */ 890#define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */ 891#define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */ 892#define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */ 893#define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */ 894#define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */ 895#define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */ 896#define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */ 897#define MIPS_TX7900 0x38 /* Toshiba TX79 ISA III+*/ 898#define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */ 899#define MIPS_R5500 0x55 /* NEC VR5500 ISA IV */ 900 901/* 902 * CPU revision IDs for some prehistoric processors. 903 */ 904 905/* For MIPS_R3000 */ 906#define MIPS_REV_R3000 0x20 907#define MIPS_REV_R3000A 0x30 908 909/* For MIPS_TX3900 */ 910#define MIPS_REV_TX3912 0x10 911#define MIPS_REV_TX3922 0x30 912#define MIPS_REV_TX3927 0x40 913 914/* For MIPS_R4000 */ 915#define MIPS_REV_R4000_A 0x00 916#define MIPS_REV_R4000_B 0x22 917#define MIPS_REV_R4000_C 0x30 918#define MIPS_REV_R4400_A 0x40 919#define MIPS_REV_R4400_B 0x50 920#define MIPS_REV_R4400_C 0x60 921 922/* For MIPS_TX4900 */ 923#define MIPS_REV_TX4927 0x22 924 925/* 926 * CPU processor revision IDs for company ID == 1 (MIPS) 927 */ 928#define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */ 929#define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */ 930#define MIPS_20Kc 0x82 /* MIPS 20Kc ISA 64 */ 931#define MIPS_4Kmp 0x83 /* MIPS 4Km/4Kp ISA 32 */ 932#define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */ 933#define MIPS_4KEmp 0x85 /* MIPS 4KEm/4KEp ISA 32 */ 934#define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */ 935#define MIPS_M4K 0x87 /* MIPS M4K ISA 32 Rel 2 */ 936#define MIPS_25Kf 0x88 /* MIPS 25Kf ISA 64 */ 937#define MIPS_5KE 0x89 /* MIPS 5KE ISA 64 Rel 2 */ 938#define MIPS_4KEc_R2 0x90 /* MIPS 4KEc_R2 ISA 32 Rel 2 */ 939#define MIPS_4KEmp_R2 0x91 /* MIPS 4KEm/4KEp_R2 ISA 32 Rel 2 */ 940#define MIPS_4KSd 0x92 /* MIPS 4KSd ISA 32 Rel 2 */ 941#define MIPS_24K 0x93 /* MIPS 24Kc/24Kf ISA 32 Rel 2 */ 942#define MIPS_34K 0x95 /* MIPS 34K ISA 32 R2 MT */ 943#define MIPS_24KE 0x96 /* MIPS 24KEc ISA 32 Rel 2 */ 944#define MIPS_74K 0x97 /* MIPS 74Kc/74Kf ISA 32 Rel 2 */ 945 946/* 947 * AMD (company ID 3) use the processor ID field to donote the CPU core 948 * revision and the company options field do donate the SOC chip type. 949 */ 950 951/* CPU processor revision IDs */ 952#define MIPS_AU_REV1 0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */ 953#define MIPS_AU_REV2 0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */ 954 955/* CPU company options IDs */ 956#define MIPS_AU1000 0x00 957#define MIPS_AU1500 0x01 958#define MIPS_AU1100 0x02 959#define MIPS_AU1550 0x03 960 961/* 962 * CPU processor revision IDs for company ID == 4 (Broadcom) 963 */ 964#define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */ 965 966/* 967 * CPU processor revision IDs for company ID == 5 (SandCraft) 968 */ 969#define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */ 970 971/* 972 * FPU processor revision ID 973 */ 974#define MIPS_SOFT 0x00 /* Software emulation ISA I */ 975#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 976#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 977#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 978#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 979#define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */ 980#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 981#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ 982 983#ifdef ENABLE_MIPS_TX3900 984#include <mips/r3900regs.h> 985#endif 986#ifdef MIPS3_5900 987#include <mips/r5900regs.h> 988#endif 989#ifdef MIPS64_SB1 990#include <mips/sb1regs.h> 991#endif 992 993#endif /* _MIPS_CPUREGS_H_ */
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