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asm.h (203697) asm.h (204557)
1/* $NetBSD: asm.h,v 1.29 2000/12/14 21:29:51 jeffs Exp $ */
2
3/*
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell.

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28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * @(#)machAsmDefs.h 8.1 (Berkeley) 6/10/93
35 * JNPR: asm.h,v 1.10 2007/08/09 11:23:32 katta
1/* $NetBSD: asm.h,v 1.29 2000/12/14 21:29:51 jeffs Exp $ */
2
3/*
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell.

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28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * @(#)machAsmDefs.h 8.1 (Berkeley) 6/10/93
35 * JNPR: asm.h,v 1.10 2007/08/09 11:23:32 katta
36 * $FreeBSD: head/sys/mips/include/asm.h 203697 2010-02-09 06:24:43Z neel $
36 * $FreeBSD: head/sys/mips/include/asm.h 204557 2010-03-02 07:27:30Z imp $
37 */
38
39/*
40 * machAsmDefs.h --
41 *
42 * Macros used when writing assembler programs.
43 *
44 * Copyright (C) 1989 Digital Equipment Corporation.

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335/*
336 * XXX retain dialects XXX
337 */
338#define ALEAF(x) XLEAF(x)
339#define NLEAF(x) LEAF_NOPROFILE(x)
340#define NON_LEAF(x, fsize, retpc) NESTED(x, fsize, retpc)
341#define NNON_LEAF(x, fsize, retpc) NESTED_NOPROFILE(x, fsize, retpc)
342
37 */
38
39/*
40 * machAsmDefs.h --
41 *
42 * Macros used when writing assembler programs.
43 *
44 * Copyright (C) 1989 Digital Equipment Corporation.

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335/*
336 * XXX retain dialects XXX
337 */
338#define ALEAF(x) XLEAF(x)
339#define NLEAF(x) LEAF_NOPROFILE(x)
340#define NON_LEAF(x, fsize, retpc) NESTED(x, fsize, retpc)
341#define NNON_LEAF(x, fsize, retpc) NESTED_NOPROFILE(x, fsize, retpc)
342
343#if defined(__mips_o32)
344#define SZREG 4
345#else
346#define SZREG 8
347#endif
348
349#if defined(__mips_o32) || defined(__mips_o64)
350#define ALSK 7 /* stack alignment */
351#define ALMASK -7 /* stack alignment */
352#define SZFPREG 4
353#define FP_L lwc1
354#define FP_S swc1
355#else
356#define ALSK 15 /* stack alignment */
357#define ALMASK -15 /* stack alignment */
358#define SZFPREG 8
359#define FP_L ldc1
360#define FP_S sdc1
361#endif
362
343/*
344 * standard callframe {
363/*
364 * standard callframe {
345 * register_t cf_args[4]; arg0 - arg3
365 * register_t cf_pad[N]; o32/64 (N=0), n32 (N=1) n64 (N=1)
366 * register_t cf_args[4]; arg0 - arg3 (only on o32 and o64)
367 * register_t cf_gp; global pointer (only on n32 and n64)
346 * register_t cf_sp; frame pointer
347 * register_t cf_ra; return address
348 * };
349 */
368 * register_t cf_sp; frame pointer
369 * register_t cf_ra; return address
370 * };
371 */
350#define CALLFRAME_SIZ (4 * (4 + 2))
351#define CALLFRAME_SP (4 * 4)
352#define CALLFRAME_RA (4 * 5)
353#define START_FRAME CALLFRAME_SIZ
372#if defined(__mips_o32) || defined(__mips_o64)
373#define CALLFRAME_SIZ (SZREG * (4 + 2))
374#define CALLFRAME_S0 0
375#elif defined(__mips_n32) || defined(__mips_n64)
376#define CALLFRAME_SIZ (SZREG * 4)
377#define CALLFRAME_S0 (CALLFRAME_SIZ - 4 * SZREG)
378#endif
379#ifndef _KERNEL
380#define CALLFRAME_GP (CALLFRAME_SIZ - 3 * SZREG)
381#endif
382#define CALLFRAME_SP (CALLFRAME_SIZ - 2 * SZREG)
383#define CALLFRAME_RA (CALLFRAME_SIZ - 1 * SZREG)
354
355/*
356 * While it would be nice to be compatible with the SGI
357 * REG_L and REG_S macros, because they do not take parameters, it
358 * is impossible to use them with the _MIPS_SIM_ABIX32 model.
359 *
360 * These macros hide the use of mips3 instructions from the
361 * assembler to prevent the assembler from generating 64-bit style
362 * ABI calls.
363 */
384
385/*
386 * While it would be nice to be compatible with the SGI
387 * REG_L and REG_S macros, because they do not take parameters, it
388 * is impossible to use them with the _MIPS_SIM_ABIX32 model.
389 *
390 * These macros hide the use of mips3 instructions from the
391 * assembler to prevent the assembler from generating 64-bit style
392 * ABI calls.
393 */
394#if _MIPS_SZPTR == 32
395#define PTR_ADD add
396#define PTR_ADDI addi
397#define PTR_ADDU addu
398#define PTR_ADDIU addiu
399#define PTR_SUB add
400#define PTR_SUBI subi
401#define PTR_SUBU subu
402#define PTR_SUBIU subu
403#define PTR_L lw
404#define PTR_LA la
405#define PTR_S sw
406#define PTR_SLL sll
407#define PTR_SLLV sllv
408#define PTR_SRL srl
409#define PTR_SRLV srlv
410#define PTR_SRA sra
411#define PTR_SRAV srav
412#define PTR_LL ll
413#define PTR_SC sc
414#define PTR_WORD .word
415#define PTR_SCALESHIFT 2
416#else /* _MIPS_SZPTR == 64 */
417#define PTR_ADD dadd
418#define PTR_ADDI daddi
419#define PTR_ADDU daddu
420#define PTR_ADDIU daddiu
421#define PTR_SUB dadd
422#define PTR_SUBI dsubi
423#define PTR_SUBU dsubu
424#define PTR_SUBIU dsubu
425#define PTR_L ld
426#define PTR_LA dla
427#define PTR_S sd
428#define PTR_SLL dsll
429#define PTR_SLLV dsllv
430#define PTR_SRL dsrl
431#define PTR_SRLV dsrlv
432#define PTR_SRA dsra
433#define PTR_SRAV dsrav
434#define PTR_LL lld
435#define PTR_SC scd
436#define PTR_WORD .dword
437#define PTR_SCALESHIFT 3
438#endif /* _MIPS_SZPTR == 64 */
364
439
365#if !defined(_MIPS_BSD_API) || _MIPS_BSD_API == _MIPS_BSD_API_LP32
366/* #if !defined(__mips_n64) */
440#if _MIPS_SZINT == 32
441#define INT_ADD add
442#define INT_ADDI addi
443#define INT_ADDU addu
444#define INT_ADDIU addiu
445#define INT_SUB add
446#define INT_SUBI subi
447#define INT_SUBU subu
448#define INT_SUBIU subu
449#define INT_L lw
450#define INT_LA la
451#define INT_S sw
452#define INT_SLL sll
453#define INT_SLLV sllv
454#define INT_SRL srl
455#define INT_SRLV srlv
456#define INT_SRA sra
457#define INT_SRAV srav
458#define INT_LL ll
459#define INT_SC sc
460#define INT_WORD .word
461#define INT_SCALESHIFT 2
462#else
463#define INT_ADD dadd
464#define INT_ADDI daddi
465#define INT_ADDU daddu
466#define INT_ADDIU daddiu
467#define INT_SUB dadd
468#define INT_SUBI dsubi
469#define INT_SUBU dsubu
470#define INT_SUBIU dsubu
471#define INT_L ld
472#define INT_LA dla
473#define INT_S sd
474#define INT_SLL dsll
475#define INT_SLLV dsllv
476#define INT_SRL dsrl
477#define INT_SRLV dsrlv
478#define INT_SRA dsra
479#define INT_SRAV dsrav
480#define INT_LL lld
481#define INT_SC scd
482#define INT_WORD .dword
483#define INT_SCALESHIFT 3
484#endif
485
486#if _MIPS_SZLONG == 32
487#define LONG_ADD add
488#define LONG_ADDI addi
489#define LONG_ADDU addu
490#define LONG_ADDIU addiu
491#define LONG_SUB add
492#define LONG_SUBI subi
493#define LONG_SUBU subu
494#define LONG_SUBIU subu
495#define LONG_L lw
496#define LONG_LA la
497#define LONG_S sw
498#define LONG_SLL sll
499#define LONG_SLLV sllv
500#define LONG_SRL srl
501#define LONG_SRLV srlv
502#define LONG_SRA sra
503#define LONG_SRAV srav
504#define LONG_LL ll
505#define LONG_SC sc
506#define LONG_WORD .word
507#define LONG_SCALESHIFT 2
508#else
509#define LONG_ADD dadd
510#define LONG_ADDI daddi
511#define LONG_ADDU daddu
512#define LONG_ADDIU daddiu
513#define LONG_SUB dadd
514#define LONG_SUBI dsubi
515#define LONG_SUBU dsubu
516#define LONG_SUBIU dsubu
517#define LONG_L ld
518#define LONG_LA dla
519#define LONG_S sd
520#define LONG_SLL dsll
521#define LONG_SLLV dsllv
522#define LONG_SRL dsrl
523#define LONG_SRLV dsrlv
524#define LONG_SRA dsra
525#define LONG_SRAV dsrav
526#define LONG_LL lld
527#define LONG_SC scd
528#define LONG_WORD .dword
529#define LONG_SCALESHIFT 3
530#endif
531
532#if SZREG == 4
367#define REG_L lw
368#define REG_S sw
369#define REG_LI li
533#define REG_L lw
534#define REG_S sw
535#define REG_LI li
370#define REG_PROLOGUE .set push
371#define REG_EPILOGUE .set pop
372#define SZREG 4
373#define PTR_LA la
374#define PTR_ADDU addu
536#define REG_ADDU addu
537#define REG_SLL sll
538#define REG_SLLV sllv
539#define REG_SRL srl
540#define REG_SRLV srlv
541#define REG_SRA sra
542#define REG_SRAV srav
543#define REG_LL ll
544#define REG_SC sc
545#define REG_SCALESHIFT 2
375#else
376#define REG_L ld
377#define REG_S sd
378#define REG_LI dli
546#else
547#define REG_L ld
548#define REG_S sd
549#define REG_LI dli
550#define REG_ADDU daddu
551#define REG_SLL dsll
552#define REG_SLLV dsllv
553#define REG_SRL dsrl
554#define REG_SRLV dsrlv
555#define REG_SRA dsra
556#define REG_SRAV dsrav
557#define REG_LL lld
558#define REG_SC scd
559#define REG_SCALESHIFT 3
560#endif
561
562#if _MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2 || \
563 _MIPS_ISA == _MIPS_ISA_MIPS32
564#define MFC0 mfc0
565#define MTC0 mtc0
566#endif
567#if _MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4 || \
568 _MIPS_ISA == _MIPS_ISA_MIPS64
569#define MFC0 dmfc0
570#define MTC0 dmtc0
571#endif
572
573#if defined(__mips_o32) || defined(__mips_o64)
574
575#ifdef __ABICALLS__
576#define CPRESTORE(r) .cprestore r
577#define CPLOAD(r) .cpload r
578#else
579#define CPRESTORE(r) /* not needed */
580#define CPLOAD(r) /* not needed */
581#endif
582
583#define SETUP_GP \
584 .set push; \
585 .set noreorder; \
586 .cpload t9; \
587 .set pop
588#define SETUP_GPX(r) \
589 .set push; \
590 .set noreorder; \
591 move r,ra; /* save old ra */ \
592 bal 7f; \
593 nop; \
594 7: .cpload ra; \
595 move ra,r; \
596 .set pop
597#define SETUP_GPX_L(r,lbl) \
598 .set push; \
599 .set noreorder; \
600 move r,ra; /* save old ra */ \
601 bal lbl; \
602 nop; \
603 lbl: .cpload ra; \
604 move ra,r; \
605 .set pop
606#define SAVE_GP(x) .cprestore x
607
608#define SETUP_GP64(a,b) /* n32/n64 specific */
609#define SETUP_GP64_R(a,b) /* n32/n64 specific */
610#define SETUP_GPX64(a,b) /* n32/n64 specific */
611#define SETUP_GPX64_L(a,b,c) /* n32/n64 specific */
612#define RESTORE_GP64 /* n32/n64 specific */
613#define USE_ALT_CP(a) /* n32/n64 specific */
614#endif /* __mips_o32 || __mips_o64 */
615
616#if defined(__mips_o32) || defined(__mips_o64)
617#define REG_PROLOGUE .set push
618#define REG_EPILOGUE .set pop
619#endif
620#if defined(__mips_n32) || defined(__mips_n64)
379#define REG_PROLOGUE .set push ; .set mips3
380#define REG_EPILOGUE .set pop
621#define REG_PROLOGUE .set push ; .set mips3
622#define REG_EPILOGUE .set pop
381#define SZREG 8
382#define PTR_LA dla
383#define PTR_ADDU daddu
384#endif /* _MIPS_BSD_API */
623#endif
385
624
625#if defined(__mips_n32) || defined(__mips_n64)
626#define SETUP_GP /* o32 specific */
627#define SETUP_GPX(r) /* o32 specific */
628#define SETUP_GPX_L(r,lbl) /* o32 specific */
629#define SAVE_GP(x) /* o32 specific */
630#define SETUP_GP64(a,b) .cpsetup $25, a, b
631#define SETUP_GPX64(a,b) \
632 .set push; \
633 move b,ra; \
634 .set noreorder; \
635 bal 7f; \
636 nop; \
637 7: .set pop; \
638 .cpsetup ra, a, 7b; \
639 move ra,b
640#define SETUP_GPX64_L(a,b,c) \
641 .set push; \
642 move b,ra; \
643 .set noreorder; \
644 bal c; \
645 nop; \
646 c: .set pop; \
647 .cpsetup ra, a, c; \
648 move ra,b
649#define RESTORE_GP64 .cpreturn
650#define USE_ALT_CP(a) .cplocal a
651#endif /* __mips_n32 || __mips_n64 */
652
386#define mfc0_macro(data, spr) \
387 __asm __volatile ("mfc0 %0, $%1" \
388 : "=r" (data) /* outputs */ \
389 : "i" (spr)); /* inputs */
390
391#define mtc0_macro(data, spr) \
392 __asm __volatile ("mtc0 %0, $%1" \
393 : /* outputs */ \

--- 158 unchanged lines hidden --- 		653#define mfc0_macro(data, spr) \
654 __asm __volatile ("mfc0 %0, $%1" \
655 : "=r" (data) /* outputs */ \
656 : "i" (spr)); /* inputs */
657
658#define mtc0_macro(data, spr) \
659 __asm __volatile ("mtc0 %0, $%1" \
660 : /* outputs */ \

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