1/***********************license start***************
2 * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
3 * reserved.
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met:

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36 *
37 ***********************license end**************************************/
38
39/*
40 * This product includes software developed by the University of
41 * California, Berkeley and its contributors."
42 */
43
44/* $FreeBSD: head/sys/mips/cavium/octeon_pcmap_regs.h 242273 2012-10-29 00:51:53Z jmallett $ */
45
46#ifndef __OCTEON_PCMAP_REGS_H__
47#define __OCTEON_PCMAP_REGS_H__
48
49#ifndef LOCORE
50
51/*
52 * Utility inlines & macros
53 */
54
55#if defined(__mips_n64)
56#define oct_write64(a, v) (*(volatile uint64_t *)(a) = (uint64_t)(v))
57
58#define OCT_READ(n, t) \
59static inline t oct_read ## n(uintptr_t a) \
60{ \
61 volatile t *p = (volatile t *)a; \
62 return (*p); \
63}
64
65OCT_READ(64, uint64_t);
66
67#elif defined(__mips_n32) || defined(__mips_o32)
68#if defined(__mips_n32)
69static inline void oct_write64 (uint64_t csr_addr, uint64_t val64)
70{
71 __asm __volatile (
72 ".set push\n"
73 ".set mips64\n"
74 "sd %0, 0(%1)\n"
75 ".set pop\n"
76 :
77 : "r"(val64), "r"(csr_addr));
78}
79
80#define OCT_READ(n, t, insn) \
81static inline t oct_read ## n(uint64_t a) \
82{ \
83 uint64_t tmp; \
84 \
85 __asm __volatile ( \
86 ".set push\n" \
87 ".set mips64\n" \
88 insn "\t%0, 0(%1)\n" \
89 ".set pop\n" \
90 : "=r"(tmp) \
91 : "r"(a)); \
92 return ((t)tmp); \
93}
94
95OCT_READ(64, uint64_t, "ld");
96#else
97
98/*
99 * XXX
100 * Add o32 variants that load the address into a register and the result out
101 * of a register properly, and simply disable interrupts before and after and
102 * hope that we don't need to refill or modify the TLB to access the address.

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135 "sd %0, 0(%1)\n"
136 ".set pop\n"
137 : "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3)
138 : "r" (valh), "r" (vall), "r" (csr_addrh), "r" (csr_addrl));
139
140 intr_restore(sr);
141}
142
143static inline uint64_t oct_read64 (uint64_t csr_addr)
144{
145 uint32_t csr_addrh = csr_addr >> 32;
146 uint32_t csr_addrl = csr_addr;
147 uint32_t valh;
148 uint32_t vall;
149 register_t sr;
150

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170 intr_restore(sr);
171
172 return ((uint64_t)valh << 32) | vall;
173}
174#endif
175
176#endif
177
178/*
179 * octeon_machdep.c
180 *
181 * Direct to Board Support level.
182 */
183extern void octeon_reset(void);
184extern void octeon_debug_symbol(void);
185extern void octeon_ciu_reset(void);
186extern int octeon_is_simulation(void);
187#endif /* LOCORE */
188
189/*
190 * Default FLASH device (physical) base address
191 */
192#define OCTEON_FLASH_BASE_ADDR (0x1d040000ull)
193
194#endif /* !OCTEON_PCMAP_REGS_H__ */