79#include <contrib/octeon-sdk/cvmx-interrupt.h>
80#include <contrib/octeon-sdk/cvmx-version.h>
81
82#include <mips/cavium/octeon_irq.h>
83
84#if defined(__mips_n64)
85#define MAX_APP_DESC_ADDR 0xffffffffafffffff
86#else
87#define MAX_APP_DESC_ADDR 0xafffffff
88#endif
89
90#define OCTEON_CLOCK_DEFAULT (500 * 1000 * 1000)
91
92struct octeon_feature_description {
93 octeon_feature_t ofd_feature;
94 const char *ofd_string;
95};
96
97extern int *edata;
98extern int *end;
99extern char cpu_model[];
100extern char cpu_board[];
101
102static const struct octeon_feature_description octeon_feature_descriptions[] = {
103 { OCTEON_FEATURE_SAAD, "SAAD" },
104 { OCTEON_FEATURE_ZIP, "ZIP" },
105 { OCTEON_FEATURE_CRYPTO, "CRYPTO" },
106 { OCTEON_FEATURE_DORM_CRYPTO, "DORM_CRYPTO" },
107 { OCTEON_FEATURE_PCIE, "PCIE" },
108 { OCTEON_FEATURE_SRIO, "SRIO" },
109 { OCTEON_FEATURE_KEY_MEMORY, "KEY_MEMORY" },
110 { OCTEON_FEATURE_LED_CONTROLLER, "LED_CONTROLLER" },
111 { OCTEON_FEATURE_TRA, "TRA" },
112 { OCTEON_FEATURE_MGMT_PORT, "MGMT_PORT" },
113 { OCTEON_FEATURE_RAID, "RAID" },
114 { OCTEON_FEATURE_USB, "USB" },
115 { OCTEON_FEATURE_NO_WPTR, "NO_WPTR" },
116 { OCTEON_FEATURE_DFA, "DFA" },
117 { OCTEON_FEATURE_MDIO_CLAUSE_45, "MDIO_CLAUSE_45" },
118 { OCTEON_FEATURE_NPEI, "NPEI" },
119 { OCTEON_FEATURE_ILK, "ILK" },
120 { OCTEON_FEATURE_HFA, "HFA" },
121 { OCTEON_FEATURE_DFM, "DFM" },
122 { OCTEON_FEATURE_CIU2, "CIU2" },
123 { OCTEON_FEATURE_DICI_MODE, "DICI_MODE" },
124 { OCTEON_FEATURE_BIT_EXTRACTOR, "BIT_EXTRACTOR" },
125 { OCTEON_FEATURE_NAND, "NAND" },
126 { OCTEON_FEATURE_MMC, "MMC" },
127 { OCTEON_FEATURE_PKND, "PKND" },
128 { OCTEON_FEATURE_CN68XX_WQE, "CN68XX_WQE" },
129 { 0, NULL }
130};
131
132uint64_t ciu_get_en_reg_addr_new(int corenum, int intx, int enx, int ciu_ip);
133void ciu_dump_interrutps_enabled(int core_num, int intx, int enx, int ciu_ip);
134
135static uint64_t octeon_get_ticks(void);
136static unsigned octeon_get_timecount(struct timecounter *tc);
137
138static void octeon_boot_params_init(register_t ptr);
139
140static struct timecounter octeon_timecounter = {
141 octeon_get_timecount, /* get_timecount */
142 0, /* no poll_pps */
143 0xffffffffu, /* octeon_mask */
144 0, /* frequency */
145 "Octeon", /* name */
146 900, /* quality (adjusted in code) */
147};
148
149void
150platform_cpu_init()
151{
152 /* Nothing special yet */
153}
154
155/*
156 * Perform a board-level soft-reset.
157 */
158void
159platform_reset(void)
160{
161 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
162}
163
164/*
165 * octeon_debug_symbol
166 *
167 * Does nothing.
168 * Used to mark the point for simulator to begin tracing
169 */
170void
171octeon_debug_symbol(void)
172{
173}
174
175/*
176 * octeon_ciu_reset
177 *
178 * Shutdown all CIU to IP2, IP3 mappings
179 */
180void
181octeon_ciu_reset(void)
182{
183 uint64_t cvmctl;
184
185 /* Disable all CIU interrupts by default */
186 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0);
187 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0);
188 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0);
189 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0);
190
191#ifdef SMP
192 /* Enable the MBOX interrupts. */
193 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1),
194 (1ull << (OCTEON_IRQ_MBOX0 - 8)) |
195 (1ull << (OCTEON_IRQ_MBOX1 - 8)));
196#endif
197
198 /*
199 * Move the Performance Counter interrupt to OCTEON_PMC_IRQ
200 */
201 cvmctl = mips_rd_cvmctl();
202 cvmctl &= ~(7 << 7);
203 cvmctl |= (OCTEON_PMC_IRQ + 2) << 7;
204 mips_wr_cvmctl(cvmctl);
205}
206
207static void
208octeon_memory_init(void)
209{
210 vm_paddr_t phys_end;
211 int64_t addr;
212 unsigned i, j;
213
214 phys_end = round_page(MIPS_KSEG0_TO_PHYS((vm_offset_t)&end));
215
216 if (octeon_is_simulation()) {
217 /* Simulator we limit to 96 meg */
218 phys_avail[0] = phys_end;
219 phys_avail[1] = 96 << 20;
220
221 dump_avail[0] = phys_avail[0];
222 dump_avail[1] = phys_avail[1];
223
224 realmem = physmem = btoc(phys_avail[1] - phys_avail[0]);
225 return;
226 }
227
228 /*
229 * Allocate memory from bootmem 1MB at a time and merge
230 * adjacent entries.
231 */
232 i = 0;
233 while (i < PHYS_AVAIL_ENTRIES) {
234 /*
235 * If there is less than 2MB of memory available in 128-byte
236 * blocks, do not steal any more memory. We need to leave some
237 * memory for the command queues to be allocated out of.
238 */
239 if (cvmx_bootmem_available_mem(128) < 2 << 20)
240 break;
241
242 addr = cvmx_bootmem_phy_alloc(1 << 20, phys_end,
243 ~(vm_paddr_t)0, PAGE_SIZE, 0);
244 if (addr == -1)
245 break;
246
247 /*
248 * The SDK needs to be able to easily map any memory that might
249 * come to it e.g. in the form of an mbuf. Because on !n64 we
250 * can't direct-map some addresses and we don't want to manage
251 * temporary mappings within the SDK, don't feed memory that
252 * can't be direct-mapped to the kernel.
253 */
254#if !defined(__mips_n64)
255 if (!MIPS_DIRECT_MAPPABLE(addr + (1 << 20) - 1))
256 continue;
257#endif
258
259 physmem += btoc(1 << 20);
260
261 if (i > 0 && phys_avail[i - 1] == addr) {
262 phys_avail[i - 1] += 1 << 20;
263 continue;
264 }
265
266 phys_avail[i + 0] = addr;
267 phys_avail[i + 1] = addr + (1 << 20);
268
269 i += 2;
270 }
271
272 for (j = 0; j < i; j++)
273 dump_avail[j] = phys_avail[j];
274
275 realmem = physmem;
276}
277
278void
279platform_start(__register_t a0, __register_t a1, __register_t a2 __unused,
280 __register_t a3)
281{
282 const struct octeon_feature_description *ofd;
283 uint64_t platform_counter_freq;
284
285 /*
286 * XXX
287 * octeon_boot_params_init() should be called before anything else,
288 * certainly before any output; we may find out from the boot
289 * descriptor's flags that we're supposed to use the PCI or UART1
290 * consoles rather than UART0. No point doing that reorganization
291 * until we actually intercept UART_DEV_CONSOLE for the UART1 case
292 * and somehow handle the PCI console, which we lack code for
293 * entirely.
294 */
295
296 mips_postboot_fixup();
297
298 /* Initialize pcpu stuff */
299 mips_pcpu0_init();
300 mips_timer_early_init(OCTEON_CLOCK_DEFAULT);
301 cninit();
302
303 octeon_ciu_reset();
304 octeon_boot_params_init(a3);
305 /*
306 * XXX
307 * We can certainly parse command line arguments or U-Boot environment
308 * to determine whether to bootverbose / single user / ... I think
309 * stass has patches to add support for loader things to U-Boot even.
310 */
311 bootverbose = 1;
312
313 /*
314 * For some reason on the cn38xx simulator ebase register is set to
315 * 0x80001000 at bootup time. Move it back to the default, but
316 * when we move to having support for multiple executives, we need
317 * to rethink this.
318 */
319 mips_wr_ebase(0x80000000);
320
321 octeon_memory_init();
322 init_param1();
323 init_param2(physmem);
324 mips_cpu_init();
325 pmap_bootstrap();
326 mips_proc0_init();
327 mutex_init();
328 kdb_init();
329#ifdef KDB
330 if (boothowto & RB_KDB)
331 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
332#endif
333 cpu_clock = cvmx_sysinfo_get()->cpu_clock_hz;
334 platform_counter_freq = cpu_clock;
335 octeon_timecounter.tc_frequency = cpu_clock;
336 platform_timecounter = &octeon_timecounter;
337 mips_timer_init_params(platform_counter_freq, 0);
338 set_cputicker(octeon_get_ticks, cpu_clock, 0);
339
340#ifdef SMP
341 /*
342 * Clear any pending IPIs.
343 */
344 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(0), 0xffffffff);
345#endif
346
347 printf("Octeon SDK: %s\n", OCTEON_SDK_VERSION_STRING);
348 printf("Available Octeon features:");
349 for (ofd = octeon_feature_descriptions; ofd->ofd_string != NULL; ofd++)
350 if (octeon_has_feature(ofd->ofd_feature))
351 printf(" %s", ofd->ofd_string);
352 printf("\n");
353}
354
355static uint64_t
356octeon_get_ticks(void)
357{
358 uint64_t cvmcount;
359
360 CVMX_MF_CYCLE(cvmcount);
361 return (cvmcount);
362}
363
364static unsigned
365octeon_get_timecount(struct timecounter *tc)
366{
367 return ((unsigned)octeon_get_ticks());
368}
369
370static int
371sysctl_machdep_led_display(SYSCTL_HANDLER_ARGS)
372{
373 size_t buflen;
374 char buf[9];
375 int error;
376
377 if (req->newptr == NULL)
378 return (EINVAL);
379
380 if (cvmx_sysinfo_get()->led_display_base_addr == 0)
381 return (ENODEV);
382
383 /*
384 * Revision 1.x of the EBT3000 only supports 4 characters, but
385 * other devices support 8.
386 */
387 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBT3000 &&
388 cvmx_sysinfo_get()->board_rev_major == 1)
389 buflen = 4;
390 else
391 buflen = 8;
392
393 if (req->newlen > buflen)
394 return (E2BIG);
395
396 error = SYSCTL_IN(req, buf, req->newlen);
397 if (error != 0)
398 return (error);
399
400 buf[req->newlen] = '\0';
401 ebt3000_str_write(buf);
402
403 return (0);
404}
405
406SYSCTL_PROC(_machdep, OID_AUTO, led_display, CTLTYPE_STRING | CTLFLAG_WR,
407 NULL, 0, sysctl_machdep_led_display, "A",
408 "String to display on LED display");
409
410/**
411 * version of printf that works better in exception context.
412 *
413 * @param format
414 *
415 * XXX If this function weren't in cvmx-interrupt.c, we'd use the SDK version.
416 */
417void cvmx_safe_printf(const char *format, ...)
418{
419 char buffer[256];
420 char *ptr = buffer;
421 int count;
422 va_list args;
423
424 va_start(args, format);
425#ifndef __U_BOOT__
426 count = vsnprintf(buffer, sizeof(buffer), format, args);
427#else
428 count = vsprintf(buffer, format, args);
429#endif
430 va_end(args);
431
432 while (count-- > 0)
433 {
434 cvmx_uart_lsr_t lsrval;
435
436 /* Spin until there is room */
437 do
438 {
439 lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(0));
440#if !defined(CONFIG_OCTEON_SIM_SPEED)
441 if (lsrval.s.temt == 0)
442 cvmx_wait(10000); /* Just to reduce the load on the system */
443#endif
444 }
445 while (lsrval.s.temt == 0);
446
447 if (*ptr == '\n')
448 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), '\r');
449 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), *ptr++);
450 }
451}
452
453/* impSTART: This stuff should move back into the Cavium SDK */
454/*
455 ****************************************************************************************
456 *
457 * APP/BOOT DESCRIPTOR STUFF
458 *
459 ****************************************************************************************
460 */
461
462/* Define the struct that is initialized by the bootloader used by the
463 * startup code.
464 *
465 * Copyright (c) 2004, 2005, 2006 Cavium Networks.
466 *
467 * The authors hereby grant permission to use, copy, modify, distribute,
468 * and license this software and its documentation for any purpose, provided
469 * that existing copyright notices are retained in all copies and that this
470 * notice is included verbatim in any distributions. No written agreement,
471 * license, or royalty fee is required for any of the authorized uses.
472 * Modifications to this software may be copyrighted by their authors
473 * and need not follow the licensing terms described here, provided that
474 * the new terms are clearly indicated on the first page of each file where
475 * they apply.
476 */
477
478#define OCTEON_CURRENT_DESC_VERSION 6
479#define OCTEON_ARGV_MAX_ARGS (64)
480#define OCTOEN_SERIAL_LEN 20
481
482typedef struct {
483 /* Start of block referenced by assembly code - do not change! */
484 uint32_t desc_version;
485 uint32_t desc_size;
486
487 uint64_t stack_top;
488 uint64_t heap_base;
489 uint64_t heap_end;
490 uint64_t entry_point; /* Only used by bootloader */
491 uint64_t desc_vaddr;
492 /* End of This block referenced by assembly code - do not change! */
493
494 uint32_t exception_base_addr;
495 uint32_t stack_size;
496 uint32_t heap_size;
497 uint32_t argc; /* Argc count for application */
498 uint32_t argv[OCTEON_ARGV_MAX_ARGS];
499 uint32_t flags;
500 uint32_t core_mask;
501 uint32_t dram_size; /**< DRAM size in megabyes */
502 uint32_t phy_mem_desc_addr; /**< physical address of free memory descriptor block*/
503 uint32_t debugger_flags_base_addr; /**< used to pass flags from app to debugger */
504 uint32_t eclock_hz; /**< CPU clock speed, in hz */
505 uint32_t dclock_hz; /**< DRAM clock speed, in hz */
506 uint32_t spi_clock_hz; /**< SPI4 clock in hz */
507 uint16_t board_type;
508 uint8_t board_rev_major;
509 uint8_t board_rev_minor;
510 uint16_t chip_type;
511 uint8_t chip_rev_major;
512 uint8_t chip_rev_minor;
513 char board_serial_number[OCTOEN_SERIAL_LEN];
514 uint8_t mac_addr_base[6];
515 uint8_t mac_addr_count;
516 uint64_t cvmx_desc_vaddr;
517} octeon_boot_descriptor_t;
518
519cvmx_bootinfo_t *octeon_bootinfo;
520
521static octeon_boot_descriptor_t *app_desc_ptr;
522
523int
524octeon_is_simulation(void)
525{
526 switch (cvmx_sysinfo_get()->board_type) {
527 case CVMX_BOARD_TYPE_SIM:
528 return 1;
529 default:
530 return 0;
531 }
532}
533
534static void
535octeon_process_app_desc_ver_6(void)
536{
537 /* XXX Why is 0x00000000ffffffffULL a bad value? */
538 if (app_desc_ptr->cvmx_desc_vaddr == 0 ||
539 app_desc_ptr->cvmx_desc_vaddr == 0xfffffffful)
540 panic("Bad octeon_bootinfo %p", octeon_bootinfo);
541
542 octeon_bootinfo =
543 (cvmx_bootinfo_t *)(intptr_t)app_desc_ptr->cvmx_desc_vaddr;
544 octeon_bootinfo =
545 (cvmx_bootinfo_t *) ((intptr_t)octeon_bootinfo | MIPS_KSEG0_START);
546 if (octeon_bootinfo->major_version != 1)
547 panic("Incompatible CVMX descriptor from bootloader: %d.%d %p",
548 (int) octeon_bootinfo->major_version,
549 (int) octeon_bootinfo->minor_version, octeon_bootinfo);
550
551 cvmx_sysinfo_minimal_initialize(octeon_bootinfo->phy_mem_desc_addr,
552 octeon_bootinfo->board_type,
553 octeon_bootinfo->board_rev_major,
554 octeon_bootinfo->board_rev_minor,
555 octeon_bootinfo->eclock_hz);
556 memcpy(cvmx_sysinfo_get()->mac_addr_base,
557 octeon_bootinfo->mac_addr_base, 6);
558 cvmx_sysinfo_get()->mac_addr_count = octeon_bootinfo->mac_addr_count;
559 cvmx_sysinfo_get()->compact_flash_common_base_addr =
560 octeon_bootinfo->compact_flash_common_base_addr;
561 cvmx_sysinfo_get()->compact_flash_attribute_base_addr =
562 octeon_bootinfo->compact_flash_attribute_base_addr;
563 cvmx_sysinfo_get()->core_mask = octeon_bootinfo->core_mask;
564 cvmx_sysinfo_get()->led_display_base_addr =
565 octeon_bootinfo->led_display_base_addr;
566 memcpy(cvmx_sysinfo_get()->board_serial_number,
567 octeon_bootinfo->board_serial_number,
568 sizeof cvmx_sysinfo_get()->board_serial_number);
569}
570
571static void
572octeon_boot_params_init(register_t ptr)
573{
574 if (ptr == 0 || ptr >= MAX_APP_DESC_ADDR)
575 panic("app descriptor passed at invalid address %#jx",
576 (uintmax_t)ptr);
577
578 app_desc_ptr = (octeon_boot_descriptor_t *)(intptr_t)ptr;
579 if (app_desc_ptr->desc_version < 6)
580 panic("Your boot code is too old to be supported.");
581 octeon_process_app_desc_ver_6();
582
583 KASSERT(octeon_bootinfo != NULL, ("octeon_bootinfo should be set"));
584
585 if (cvmx_sysinfo_get()->led_display_base_addr != 0) {
586 /*
587 * Revision 1.x of the EBT3000 only supports 4 characters, but
588 * other devices support 8.
589 */
590 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBT3000 &&
591 cvmx_sysinfo_get()->board_rev_major == 1)
592 ebt3000_str_write("FBSD");
593 else
594 ebt3000_str_write("FreeBSD!");
595 }
596
597 if (cvmx_sysinfo_get()->phy_mem_desc_addr == (uint64_t)0)
598 panic("Your boot loader did not supply a memory descriptor.");
599 cvmx_bootmem_init(cvmx_sysinfo_get()->phy_mem_desc_addr);
600
| 80#include <contrib/octeon-sdk/cvmx-interrupt.h>
81#include <contrib/octeon-sdk/cvmx-version.h>
82
83#include <mips/cavium/octeon_irq.h>
84
85#if defined(__mips_n64)
86#define MAX_APP_DESC_ADDR 0xffffffffafffffff
87#else
88#define MAX_APP_DESC_ADDR 0xafffffff
89#endif
90
91#define OCTEON_CLOCK_DEFAULT (500 * 1000 * 1000)
92
93struct octeon_feature_description {
94 octeon_feature_t ofd_feature;
95 const char *ofd_string;
96};
97
98extern int *edata;
99extern int *end;
100extern char cpu_model[];
101extern char cpu_board[];
102
103static const struct octeon_feature_description octeon_feature_descriptions[] = {
104 { OCTEON_FEATURE_SAAD, "SAAD" },
105 { OCTEON_FEATURE_ZIP, "ZIP" },
106 { OCTEON_FEATURE_CRYPTO, "CRYPTO" },
107 { OCTEON_FEATURE_DORM_CRYPTO, "DORM_CRYPTO" },
108 { OCTEON_FEATURE_PCIE, "PCIE" },
109 { OCTEON_FEATURE_SRIO, "SRIO" },
110 { OCTEON_FEATURE_KEY_MEMORY, "KEY_MEMORY" },
111 { OCTEON_FEATURE_LED_CONTROLLER, "LED_CONTROLLER" },
112 { OCTEON_FEATURE_TRA, "TRA" },
113 { OCTEON_FEATURE_MGMT_PORT, "MGMT_PORT" },
114 { OCTEON_FEATURE_RAID, "RAID" },
115 { OCTEON_FEATURE_USB, "USB" },
116 { OCTEON_FEATURE_NO_WPTR, "NO_WPTR" },
117 { OCTEON_FEATURE_DFA, "DFA" },
118 { OCTEON_FEATURE_MDIO_CLAUSE_45, "MDIO_CLAUSE_45" },
119 { OCTEON_FEATURE_NPEI, "NPEI" },
120 { OCTEON_FEATURE_ILK, "ILK" },
121 { OCTEON_FEATURE_HFA, "HFA" },
122 { OCTEON_FEATURE_DFM, "DFM" },
123 { OCTEON_FEATURE_CIU2, "CIU2" },
124 { OCTEON_FEATURE_DICI_MODE, "DICI_MODE" },
125 { OCTEON_FEATURE_BIT_EXTRACTOR, "BIT_EXTRACTOR" },
126 { OCTEON_FEATURE_NAND, "NAND" },
127 { OCTEON_FEATURE_MMC, "MMC" },
128 { OCTEON_FEATURE_PKND, "PKND" },
129 { OCTEON_FEATURE_CN68XX_WQE, "CN68XX_WQE" },
130 { 0, NULL }
131};
132
133uint64_t ciu_get_en_reg_addr_new(int corenum, int intx, int enx, int ciu_ip);
134void ciu_dump_interrutps_enabled(int core_num, int intx, int enx, int ciu_ip);
135
136static uint64_t octeon_get_ticks(void);
137static unsigned octeon_get_timecount(struct timecounter *tc);
138
139static void octeon_boot_params_init(register_t ptr);
140
141static struct timecounter octeon_timecounter = {
142 octeon_get_timecount, /* get_timecount */
143 0, /* no poll_pps */
144 0xffffffffu, /* octeon_mask */
145 0, /* frequency */
146 "Octeon", /* name */
147 900, /* quality (adjusted in code) */
148};
149
150void
151platform_cpu_init()
152{
153 /* Nothing special yet */
154}
155
156/*
157 * Perform a board-level soft-reset.
158 */
159void
160platform_reset(void)
161{
162 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
163}
164
165/*
166 * octeon_debug_symbol
167 *
168 * Does nothing.
169 * Used to mark the point for simulator to begin tracing
170 */
171void
172octeon_debug_symbol(void)
173{
174}
175
176/*
177 * octeon_ciu_reset
178 *
179 * Shutdown all CIU to IP2, IP3 mappings
180 */
181void
182octeon_ciu_reset(void)
183{
184 uint64_t cvmctl;
185
186 /* Disable all CIU interrupts by default */
187 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0);
188 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0);
189 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0);
190 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0);
191
192#ifdef SMP
193 /* Enable the MBOX interrupts. */
194 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1),
195 (1ull << (OCTEON_IRQ_MBOX0 - 8)) |
196 (1ull << (OCTEON_IRQ_MBOX1 - 8)));
197#endif
198
199 /*
200 * Move the Performance Counter interrupt to OCTEON_PMC_IRQ
201 */
202 cvmctl = mips_rd_cvmctl();
203 cvmctl &= ~(7 << 7);
204 cvmctl |= (OCTEON_PMC_IRQ + 2) << 7;
205 mips_wr_cvmctl(cvmctl);
206}
207
208static void
209octeon_memory_init(void)
210{
211 vm_paddr_t phys_end;
212 int64_t addr;
213 unsigned i, j;
214
215 phys_end = round_page(MIPS_KSEG0_TO_PHYS((vm_offset_t)&end));
216
217 if (octeon_is_simulation()) {
218 /* Simulator we limit to 96 meg */
219 phys_avail[0] = phys_end;
220 phys_avail[1] = 96 << 20;
221
222 dump_avail[0] = phys_avail[0];
223 dump_avail[1] = phys_avail[1];
224
225 realmem = physmem = btoc(phys_avail[1] - phys_avail[0]);
226 return;
227 }
228
229 /*
230 * Allocate memory from bootmem 1MB at a time and merge
231 * adjacent entries.
232 */
233 i = 0;
234 while (i < PHYS_AVAIL_ENTRIES) {
235 /*
236 * If there is less than 2MB of memory available in 128-byte
237 * blocks, do not steal any more memory. We need to leave some
238 * memory for the command queues to be allocated out of.
239 */
240 if (cvmx_bootmem_available_mem(128) < 2 << 20)
241 break;
242
243 addr = cvmx_bootmem_phy_alloc(1 << 20, phys_end,
244 ~(vm_paddr_t)0, PAGE_SIZE, 0);
245 if (addr == -1)
246 break;
247
248 /*
249 * The SDK needs to be able to easily map any memory that might
250 * come to it e.g. in the form of an mbuf. Because on !n64 we
251 * can't direct-map some addresses and we don't want to manage
252 * temporary mappings within the SDK, don't feed memory that
253 * can't be direct-mapped to the kernel.
254 */
255#if !defined(__mips_n64)
256 if (!MIPS_DIRECT_MAPPABLE(addr + (1 << 20) - 1))
257 continue;
258#endif
259
260 physmem += btoc(1 << 20);
261
262 if (i > 0 && phys_avail[i - 1] == addr) {
263 phys_avail[i - 1] += 1 << 20;
264 continue;
265 }
266
267 phys_avail[i + 0] = addr;
268 phys_avail[i + 1] = addr + (1 << 20);
269
270 i += 2;
271 }
272
273 for (j = 0; j < i; j++)
274 dump_avail[j] = phys_avail[j];
275
276 realmem = physmem;
277}
278
279void
280platform_start(__register_t a0, __register_t a1, __register_t a2 __unused,
281 __register_t a3)
282{
283 const struct octeon_feature_description *ofd;
284 uint64_t platform_counter_freq;
285
286 /*
287 * XXX
288 * octeon_boot_params_init() should be called before anything else,
289 * certainly before any output; we may find out from the boot
290 * descriptor's flags that we're supposed to use the PCI or UART1
291 * consoles rather than UART0. No point doing that reorganization
292 * until we actually intercept UART_DEV_CONSOLE for the UART1 case
293 * and somehow handle the PCI console, which we lack code for
294 * entirely.
295 */
296
297 mips_postboot_fixup();
298
299 /* Initialize pcpu stuff */
300 mips_pcpu0_init();
301 mips_timer_early_init(OCTEON_CLOCK_DEFAULT);
302 cninit();
303
304 octeon_ciu_reset();
305 octeon_boot_params_init(a3);
306 /*
307 * XXX
308 * We can certainly parse command line arguments or U-Boot environment
309 * to determine whether to bootverbose / single user / ... I think
310 * stass has patches to add support for loader things to U-Boot even.
311 */
312 bootverbose = 1;
313
314 /*
315 * For some reason on the cn38xx simulator ebase register is set to
316 * 0x80001000 at bootup time. Move it back to the default, but
317 * when we move to having support for multiple executives, we need
318 * to rethink this.
319 */
320 mips_wr_ebase(0x80000000);
321
322 octeon_memory_init();
323 init_param1();
324 init_param2(physmem);
325 mips_cpu_init();
326 pmap_bootstrap();
327 mips_proc0_init();
328 mutex_init();
329 kdb_init();
330#ifdef KDB
331 if (boothowto & RB_KDB)
332 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
333#endif
334 cpu_clock = cvmx_sysinfo_get()->cpu_clock_hz;
335 platform_counter_freq = cpu_clock;
336 octeon_timecounter.tc_frequency = cpu_clock;
337 platform_timecounter = &octeon_timecounter;
338 mips_timer_init_params(platform_counter_freq, 0);
339 set_cputicker(octeon_get_ticks, cpu_clock, 0);
340
341#ifdef SMP
342 /*
343 * Clear any pending IPIs.
344 */
345 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(0), 0xffffffff);
346#endif
347
348 printf("Octeon SDK: %s\n", OCTEON_SDK_VERSION_STRING);
349 printf("Available Octeon features:");
350 for (ofd = octeon_feature_descriptions; ofd->ofd_string != NULL; ofd++)
351 if (octeon_has_feature(ofd->ofd_feature))
352 printf(" %s", ofd->ofd_string);
353 printf("\n");
354}
355
356static uint64_t
357octeon_get_ticks(void)
358{
359 uint64_t cvmcount;
360
361 CVMX_MF_CYCLE(cvmcount);
362 return (cvmcount);
363}
364
365static unsigned
366octeon_get_timecount(struct timecounter *tc)
367{
368 return ((unsigned)octeon_get_ticks());
369}
370
371static int
372sysctl_machdep_led_display(SYSCTL_HANDLER_ARGS)
373{
374 size_t buflen;
375 char buf[9];
376 int error;
377
378 if (req->newptr == NULL)
379 return (EINVAL);
380
381 if (cvmx_sysinfo_get()->led_display_base_addr == 0)
382 return (ENODEV);
383
384 /*
385 * Revision 1.x of the EBT3000 only supports 4 characters, but
386 * other devices support 8.
387 */
388 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBT3000 &&
389 cvmx_sysinfo_get()->board_rev_major == 1)
390 buflen = 4;
391 else
392 buflen = 8;
393
394 if (req->newlen > buflen)
395 return (E2BIG);
396
397 error = SYSCTL_IN(req, buf, req->newlen);
398 if (error != 0)
399 return (error);
400
401 buf[req->newlen] = '\0';
402 ebt3000_str_write(buf);
403
404 return (0);
405}
406
407SYSCTL_PROC(_machdep, OID_AUTO, led_display, CTLTYPE_STRING | CTLFLAG_WR,
408 NULL, 0, sysctl_machdep_led_display, "A",
409 "String to display on LED display");
410
411/**
412 * version of printf that works better in exception context.
413 *
414 * @param format
415 *
416 * XXX If this function weren't in cvmx-interrupt.c, we'd use the SDK version.
417 */
418void cvmx_safe_printf(const char *format, ...)
419{
420 char buffer[256];
421 char *ptr = buffer;
422 int count;
423 va_list args;
424
425 va_start(args, format);
426#ifndef __U_BOOT__
427 count = vsnprintf(buffer, sizeof(buffer), format, args);
428#else
429 count = vsprintf(buffer, format, args);
430#endif
431 va_end(args);
432
433 while (count-- > 0)
434 {
435 cvmx_uart_lsr_t lsrval;
436
437 /* Spin until there is room */
438 do
439 {
440 lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(0));
441#if !defined(CONFIG_OCTEON_SIM_SPEED)
442 if (lsrval.s.temt == 0)
443 cvmx_wait(10000); /* Just to reduce the load on the system */
444#endif
445 }
446 while (lsrval.s.temt == 0);
447
448 if (*ptr == '\n')
449 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), '\r');
450 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), *ptr++);
451 }
452}
453
454/* impSTART: This stuff should move back into the Cavium SDK */
455/*
456 ****************************************************************************************
457 *
458 * APP/BOOT DESCRIPTOR STUFF
459 *
460 ****************************************************************************************
461 */
462
463/* Define the struct that is initialized by the bootloader used by the
464 * startup code.
465 *
466 * Copyright (c) 2004, 2005, 2006 Cavium Networks.
467 *
468 * The authors hereby grant permission to use, copy, modify, distribute,
469 * and license this software and its documentation for any purpose, provided
470 * that existing copyright notices are retained in all copies and that this
471 * notice is included verbatim in any distributions. No written agreement,
472 * license, or royalty fee is required for any of the authorized uses.
473 * Modifications to this software may be copyrighted by their authors
474 * and need not follow the licensing terms described here, provided that
475 * the new terms are clearly indicated on the first page of each file where
476 * they apply.
477 */
478
479#define OCTEON_CURRENT_DESC_VERSION 6
480#define OCTEON_ARGV_MAX_ARGS (64)
481#define OCTOEN_SERIAL_LEN 20
482
483typedef struct {
484 /* Start of block referenced by assembly code - do not change! */
485 uint32_t desc_version;
486 uint32_t desc_size;
487
488 uint64_t stack_top;
489 uint64_t heap_base;
490 uint64_t heap_end;
491 uint64_t entry_point; /* Only used by bootloader */
492 uint64_t desc_vaddr;
493 /* End of This block referenced by assembly code - do not change! */
494
495 uint32_t exception_base_addr;
496 uint32_t stack_size;
497 uint32_t heap_size;
498 uint32_t argc; /* Argc count for application */
499 uint32_t argv[OCTEON_ARGV_MAX_ARGS];
500 uint32_t flags;
501 uint32_t core_mask;
502 uint32_t dram_size; /**< DRAM size in megabyes */
503 uint32_t phy_mem_desc_addr; /**< physical address of free memory descriptor block*/
504 uint32_t debugger_flags_base_addr; /**< used to pass flags from app to debugger */
505 uint32_t eclock_hz; /**< CPU clock speed, in hz */
506 uint32_t dclock_hz; /**< DRAM clock speed, in hz */
507 uint32_t spi_clock_hz; /**< SPI4 clock in hz */
508 uint16_t board_type;
509 uint8_t board_rev_major;
510 uint8_t board_rev_minor;
511 uint16_t chip_type;
512 uint8_t chip_rev_major;
513 uint8_t chip_rev_minor;
514 char board_serial_number[OCTOEN_SERIAL_LEN];
515 uint8_t mac_addr_base[6];
516 uint8_t mac_addr_count;
517 uint64_t cvmx_desc_vaddr;
518} octeon_boot_descriptor_t;
519
520cvmx_bootinfo_t *octeon_bootinfo;
521
522static octeon_boot_descriptor_t *app_desc_ptr;
523
524int
525octeon_is_simulation(void)
526{
527 switch (cvmx_sysinfo_get()->board_type) {
528 case CVMX_BOARD_TYPE_SIM:
529 return 1;
530 default:
531 return 0;
532 }
533}
534
535static void
536octeon_process_app_desc_ver_6(void)
537{
538 /* XXX Why is 0x00000000ffffffffULL a bad value? */
539 if (app_desc_ptr->cvmx_desc_vaddr == 0 ||
540 app_desc_ptr->cvmx_desc_vaddr == 0xfffffffful)
541 panic("Bad octeon_bootinfo %p", octeon_bootinfo);
542
543 octeon_bootinfo =
544 (cvmx_bootinfo_t *)(intptr_t)app_desc_ptr->cvmx_desc_vaddr;
545 octeon_bootinfo =
546 (cvmx_bootinfo_t *) ((intptr_t)octeon_bootinfo | MIPS_KSEG0_START);
547 if (octeon_bootinfo->major_version != 1)
548 panic("Incompatible CVMX descriptor from bootloader: %d.%d %p",
549 (int) octeon_bootinfo->major_version,
550 (int) octeon_bootinfo->minor_version, octeon_bootinfo);
551
552 cvmx_sysinfo_minimal_initialize(octeon_bootinfo->phy_mem_desc_addr,
553 octeon_bootinfo->board_type,
554 octeon_bootinfo->board_rev_major,
555 octeon_bootinfo->board_rev_minor,
556 octeon_bootinfo->eclock_hz);
557 memcpy(cvmx_sysinfo_get()->mac_addr_base,
558 octeon_bootinfo->mac_addr_base, 6);
559 cvmx_sysinfo_get()->mac_addr_count = octeon_bootinfo->mac_addr_count;
560 cvmx_sysinfo_get()->compact_flash_common_base_addr =
561 octeon_bootinfo->compact_flash_common_base_addr;
562 cvmx_sysinfo_get()->compact_flash_attribute_base_addr =
563 octeon_bootinfo->compact_flash_attribute_base_addr;
564 cvmx_sysinfo_get()->core_mask = octeon_bootinfo->core_mask;
565 cvmx_sysinfo_get()->led_display_base_addr =
566 octeon_bootinfo->led_display_base_addr;
567 memcpy(cvmx_sysinfo_get()->board_serial_number,
568 octeon_bootinfo->board_serial_number,
569 sizeof cvmx_sysinfo_get()->board_serial_number);
570}
571
572static void
573octeon_boot_params_init(register_t ptr)
574{
575 if (ptr == 0 || ptr >= MAX_APP_DESC_ADDR)
576 panic("app descriptor passed at invalid address %#jx",
577 (uintmax_t)ptr);
578
579 app_desc_ptr = (octeon_boot_descriptor_t *)(intptr_t)ptr;
580 if (app_desc_ptr->desc_version < 6)
581 panic("Your boot code is too old to be supported.");
582 octeon_process_app_desc_ver_6();
583
584 KASSERT(octeon_bootinfo != NULL, ("octeon_bootinfo should be set"));
585
586 if (cvmx_sysinfo_get()->led_display_base_addr != 0) {
587 /*
588 * Revision 1.x of the EBT3000 only supports 4 characters, but
589 * other devices support 8.
590 */
591 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBT3000 &&
592 cvmx_sysinfo_get()->board_rev_major == 1)
593 ebt3000_str_write("FBSD");
594 else
595 ebt3000_str_write("FreeBSD!");
596 }
597
598 if (cvmx_sysinfo_get()->phy_mem_desc_addr == (uint64_t)0)
599 panic("Your boot loader did not supply a memory descriptor.");
600 cvmx_bootmem_init(cvmx_sysinfo_get()->phy_mem_desc_addr);
601
|
601 printf("Boot Descriptor Ver: %u -> %u/%u",
602 app_desc_ptr->desc_version, octeon_bootinfo->major_version,
603 octeon_bootinfo->minor_version);
604 printf(" CPU clock: %uMHz Core Mask: %#x\n",
605 cvmx_sysinfo_get()->cpu_clock_hz / 1000000,
606 cvmx_sysinfo_get()->core_mask);
607 printf(" Board Type: %u Revision: %u/%u\n",
608 cvmx_sysinfo_get()->board_type,
609 cvmx_sysinfo_get()->board_rev_major,
610 cvmx_sysinfo_get()->board_rev_minor);
611
612 printf(" Mac Address %02X.%02X.%02X.%02X.%02X.%02X (%d)\n",
613 octeon_bootinfo->mac_addr_base[0],
614 octeon_bootinfo->mac_addr_base[1],
615 octeon_bootinfo->mac_addr_base[2],
616 octeon_bootinfo->mac_addr_base[3],
617 octeon_bootinfo->mac_addr_base[4],
618 octeon_bootinfo->mac_addr_base[5],
619 octeon_bootinfo->mac_addr_count);
620
621#if defined(OCTEON_BOARD_CAPK_0100ND)
622 strcpy(cpu_board, "CAPK-0100ND");
623 if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_CN3010_EVB_HS5) {
624 printf("Compiled for CAPK-0100ND, but board type is %s\n",
625 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type));
626 strcat(cpu_board, " hardwired, but type is ");
627 strcat(cpu_board,
628 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type));
629 }
630#else
631 strcpy(cpu_board,
632 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type));
633 printf("Board: %s\n", cpu_board);
634#endif
635 strcpy(cpu_model, octeon_model_get_string(cvmx_get_proc_id()));
636 printf("Model: %s\n", cpu_model);
637 printf("Serial number: %s\n", cvmx_sysinfo_get()->board_serial_number);
638}
639/* impEND: This stuff should move back into the Cavium SDK */
| 606 printf("Boot Descriptor Ver: %u -> %u/%u",
607 app_desc_ptr->desc_version, octeon_bootinfo->major_version,
608 octeon_bootinfo->minor_version);
609 printf(" CPU clock: %uMHz Core Mask: %#x\n",
610 cvmx_sysinfo_get()->cpu_clock_hz / 1000000,
611 cvmx_sysinfo_get()->core_mask);
612 printf(" Board Type: %u Revision: %u/%u\n",
613 cvmx_sysinfo_get()->board_type,
614 cvmx_sysinfo_get()->board_rev_major,
615 cvmx_sysinfo_get()->board_rev_minor);
616
617 printf(" Mac Address %02X.%02X.%02X.%02X.%02X.%02X (%d)\n",
618 octeon_bootinfo->mac_addr_base[0],
619 octeon_bootinfo->mac_addr_base[1],
620 octeon_bootinfo->mac_addr_base[2],
621 octeon_bootinfo->mac_addr_base[3],
622 octeon_bootinfo->mac_addr_base[4],
623 octeon_bootinfo->mac_addr_base[5],
624 octeon_bootinfo->mac_addr_count);
625
626#if defined(OCTEON_BOARD_CAPK_0100ND)
627 strcpy(cpu_board, "CAPK-0100ND");
628 if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_CN3010_EVB_HS5) {
629 printf("Compiled for CAPK-0100ND, but board type is %s\n",
630 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type));
631 strcat(cpu_board, " hardwired, but type is ");
632 strcat(cpu_board,
633 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type));
634 }
635#else
636 strcpy(cpu_board,
637 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type));
638 printf("Board: %s\n", cpu_board);
639#endif
640 strcpy(cpu_model, octeon_model_get_string(cvmx_get_proc_id()));
641 printf("Model: %s\n", cpu_model);
642 printf("Serial number: %s\n", cvmx_sysinfo_get()->board_serial_number);
643}
644/* impEND: This stuff should move back into the Cavium SDK */
|