| ia64_cpu.h (94373) | ia64_cpu.h (96912) |
|---|---|
| 1/*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/ia64/include/ia64_cpu.h 94373 2002-04-10 19:22:45Z dfr $ | 26 * $FreeBSD: head/sys/ia64/include/ia64_cpu.h 96912 2002-05-19 04:42:19Z marcel $ |
| 27 */ 28 29#ifndef _MACHINE_IA64_CPU_H_ 30#define _MACHINE_IA64_CPU_H_ 31 32/* 33 * Definition of PSR and IPSR bits. 34 */ --- 108 unchanged lines hidden (view full) --- 143#define IA32_EXCEPTION_ALIGNMENT_CHECK 17 144#define IA32_EXCEPTION_STREAMING_SIMD 19 145 146#define IA32_INTERCEPT_INSTRUCTION 0 147#define IA32_INTERCEPT_GATE 1 148#define IA32_INTERCEPT_SYSTEM_FLAG 2 149#define IA32_INTERCEPT_LOCK 4 150 | 27 */ 28 29#ifndef _MACHINE_IA64_CPU_H_ 30#define _MACHINE_IA64_CPU_H_ 31 32/* 33 * Definition of PSR and IPSR bits. 34 */ --- 108 unchanged lines hidden (view full) --- 143#define IA32_EXCEPTION_ALIGNMENT_CHECK 17 144#define IA32_EXCEPTION_STREAMING_SIMD 19 145 146#define IA32_INTERCEPT_INSTRUCTION 0 147#define IA32_INTERCEPT_GATE 1 148#define IA32_INTERCEPT_SYSTEM_FLAG 2 149#define IA32_INTERCEPT_LOCK 4 150 |
| 151/* 152 * Manipulating region bits of an address. 153 */ 154#define IA64_RR_BASE(n) (((u_int64_t) (n)) << 61) 155#define IA64_RR_MASK(x) ((x) & ((1L << 61) - 1)) 156 157#define IA64_PHYS_TO_RR6(x) ((x) | IA64_RR_BASE(6)) 158#define IA64_PHYS_TO_RR7(x) ((x) | IA64_RR_BASE(7)) 159 | |
| 160#ifndef LOCORE 161 162/* 163 * Various special ia64 instructions. 164 */ 165 166/* 167 * Memory Fence. --- 245 unchanged lines hidden --- | 151#ifndef LOCORE 152 153/* 154 * Various special ia64 instructions. 155 */ 156 157/* 158 * Memory Fence. --- 245 unchanged lines hidden --- |