1/*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 *
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26 * $FreeBSD: head/sys/ia64/include/ia64_cpu.h 94373 2002-04-10 19:22:45Z dfr $
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26 * $FreeBSD: head/sys/ia64/include/ia64_cpu.h 96912 2002-05-19 04:42:19Z marcel $ |
27 */ 28 29#ifndef _MACHINE_IA64_CPU_H_ 30#define _MACHINE_IA64_CPU_H_ 31 32/* 33 * Definition of PSR and IPSR bits. 34 */ 35#define IA64_PSR_BE 0x0000000000000002 36#define IA64_PSR_UP 0x0000000000000004 37#define IA64_PSR_AC 0x0000000000000008 38#define IA64_PSR_MFL 0x0000000000000010 39#define IA64_PSR_MFH 0x0000000000000020 40#define IA64_PSR_IC 0x0000000000002000 41#define IA64_PSR_I 0x0000000000004000 42#define IA64_PSR_PK 0x0000000000008000 43#define IA64_PSR_DT 0x0000000000020000 44#define IA64_PSR_DFL 0x0000000000040000 45#define IA64_PSR_DFH 0x0000000000080000 46#define IA64_PSR_SP 0x0000000000100000 47#define IA64_PSR_PP 0x0000000000200000 48#define IA64_PSR_DI 0x0000000000400000 49#define IA64_PSR_SI 0x0000000000800000 50#define IA64_PSR_DB 0x0000000001000000 51#define IA64_PSR_LP 0x0000000002000000 52#define IA64_PSR_TB 0x0000000004000000 53#define IA64_PSR_RT 0x0000000008000000 54#define IA64_PSR_CPL 0x0000000300000000 55#define IA64_PSR_CPL_KERN 0x0000000000000000 56#define IA64_PSR_CPL_1 0x0000000100000000 57#define IA64_PSR_CPL_2 0x0000000200000000 58#define IA64_PSR_CPL_USER 0x0000000300000000 59#define IA64_PSR_IS 0x0000000400000000 60#define IA64_PSR_MC 0x0000000800000000 61#define IA64_PSR_IT 0x0000001000000000 62#define IA64_PSR_ID 0x0000002000000000 63#define IA64_PSR_DA 0x0000004000000000 64#define IA64_PSR_DD 0x0000008000000000 65#define IA64_PSR_SS 0x0000010000000000 66#define IA64_PSR_RI 0x0000060000000000 67#define IA64_PSR_RI_0 0x0000000000000000 68#define IA64_PSR_RI_1 0x0000020000000000 69#define IA64_PSR_RI_2 0x0000040000000000 70#define IA64_PSR_ED 0x0000080000000000 71#define IA64_PSR_BN 0x0000100000000000 72#define IA64_PSR_IA 0x0000200000000000 73 74/* 75 * Definition of ISR bits. 76 */ 77#define IA64_ISR_CODE 0x000000000000ffff 78#define IA64_ISR_VECTOR 0x0000000000ff0000 79#define IA64_ISR_X 0x0000000100000000 80#define IA64_ISR_W 0x0000000200000000 81#define IA64_ISR_R 0x0000000400000000 82#define IA64_ISR_NA 0x0000000800000000 83#define IA64_ISR_SP 0x0000001000000000 84#define IA64_ISR_RS 0x0000002000000000 85#define IA64_ISR_IR 0x0000004000000000 86#define IA64_ISR_NI 0x0000008000000000 87#define IA64_ISR_SO 0x0000010000000000 88#define IA64_ISR_EI 0x0000060000000000 89#define IA64_ISR_EI_0 0x0000000000000000 90#define IA64_ISR_EI_1 0x0000020000000000 91#define IA64_ISR_EI_2 0x0000040000000000 92#define IA64_ISR_ED 0x0000080000000000 93 94/* 95 * Vector numbers for various ia64 interrupts. 96 */ 97#define IA64_VEC_VHPT 0 98#define IA64_VEC_ITLB 1 99#define IA64_VEC_DTLB 2 100#define IA64_VEC_ALT_ITLB 3 101#define IA64_VEC_ALT_DTLB 4 102#define IA64_VEC_NESTED_DTLB 5 103#define IA64_VEC_IKEY_MISS 6 104#define IA64_VEC_DKEY_MISS 7 105#define IA64_VEC_DIRTY_BIT 8 106#define IA64_VEC_INST_ACCESS 9 107#define IA64_VEC_DATA_ACCESS 10 108#define IA64_VEC_BREAK 11 109#define IA64_VEC_EXT_INTR 12 110#define IA64_VEC_PAGE_NOT_PRESENT 20 111#define IA64_VEC_KEY_PERMISSION 21 112#define IA64_VEC_INST_ACCESS_RIGHTS 22 113#define IA64_VEC_DATA_ACCESS_RIGHTS 23 114#define IA64_VEC_GENERAL_EXCEPTION 24 115#define IA64_VEC_DISABLED_FP 25 116#define IA64_VEC_NAT_CONSUMPTION 26 117#define IA64_VEC_SPECULATION 27 118#define IA64_VEC_DEBUG 29 119#define IA64_VEC_UNALIGNED_REFERENCE 30 120#define IA64_VEC_UNSUPP_DATA_REFERENCE 31 121#define IA64_VEC_FLOATING_POINT_FAULT 32 122#define IA64_VEC_FLOATING_POINT_TRAP 33 123#define IA64_VEC_LOWER_PRIVILEGE_TRANSFER 34 124#define IA64_VEC_TAKEN_BRANCH_TRAP 35 125#define IA64_VEC_SINGLE_STEP_TRAP 36 126#define IA64_VEC_IA32_EXCEPTION 45 127#define IA64_VEC_IA32_INTERCEPT 46 128#define IA64_VEC_IA32_INTERRUPT 47 129 130/* 131 * IA-32 exceptions. 132 */ 133#define IA32_EXCEPTION_DIVIDE 0 134#define IA32_EXCEPTION_DEBUG 1 135#define IA32_EXCEPTION_BREAK 3 136#define IA32_EXCEPTION_OVERFLOW 4 137#define IA32_EXCEPTION_BOUND 5 138#define IA32_EXCEPTION_DNA 7 139#define IA32_EXCEPTION_NOT_PRESENT 11 140#define IA32_EXCEPTION_STACK_FAULT 12 141#define IA32_EXCEPTION_GPFAULT 13 142#define IA32_EXCEPTION_FPERROR 16 143#define IA32_EXCEPTION_ALIGNMENT_CHECK 17 144#define IA32_EXCEPTION_STREAMING_SIMD 19 145 146#define IA32_INTERCEPT_INSTRUCTION 0 147#define IA32_INTERCEPT_GATE 1 148#define IA32_INTERCEPT_SYSTEM_FLAG 2 149#define IA32_INTERCEPT_LOCK 4 150
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151/*
152 * Manipulating region bits of an address.
153 */
154#define IA64_RR_BASE(n) (((u_int64_t) (n)) << 61)
155#define IA64_RR_MASK(x) ((x) & ((1L << 61) - 1))
156
157#define IA64_PHYS_TO_RR6(x) ((x) | IA64_RR_BASE(6))
158#define IA64_PHYS_TO_RR7(x) ((x) | IA64_RR_BASE(7))
159
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151#ifndef LOCORE 152 153/* 154 * Various special ia64 instructions. 155 */ 156 157/* 158 * Memory Fence. 159 */ 160static __inline void 161ia64_mf(void) 162{ 163 __asm __volatile("mf"); 164} 165 166static __inline void 167ia64_mf_a(void) 168{ 169 __asm __volatile("mf.a"); 170} 171 172/* 173 * Flush Cache. 174 */ 175static __inline void 176ia64_fc(u_int64_t va) 177{ 178 __asm __volatile("fc %0" :: "r"(va)); 179} 180 181/* 182 * Sync instruction stream. 183 */ 184static __inline void 185ia64_sync_i(void) 186{ 187 __asm __volatile("sync.i"); 188} 189 190/* 191 * Calculate address in VHPT for va. 192 */ 193static __inline u_int64_t 194ia64_thash(u_int64_t va) 195{ 196 u_int64_t result; 197 __asm __volatile("thash %0=%1" : "=r" (result) : "r" (va)); 198 return result; 199} 200 201/* 202 * Calculate VHPT tag for va. 203 */ 204static __inline u_int64_t 205ia64_ttag(u_int64_t va) 206{ 207 u_int64_t result; 208 __asm __volatile("ttag %0=%1" : "=r" (result) : "r" (va)); 209 return result; 210} 211 212/* 213 * Convert virtual address to physical. 214 */ 215static __inline u_int64_t 216ia64_tpa(u_int64_t va) 217{ 218 u_int64_t result; 219 __asm __volatile("tpa %0=%1" : "=r" (result) : "r" (va)); 220 return result; 221} 222 223/* 224 * Generate a ptc.e instruction. 225 */ 226static __inline void 227ia64_ptc_e(u_int64_t v) 228{ 229 __asm __volatile("ptc.e %0;; srlz.d;;" :: "r"(v)); 230} 231 232/* 233 * Generate a ptc.g instruction. 234 */ 235static __inline void 236ia64_ptc_g(u_int64_t va, u_int64_t log2size) 237{ 238 __asm __volatile("ptc.g %0,%1;; srlz.d;;" :: "r"(va), "r"(log2size)); 239} 240 241/* 242 * Generate a ptc.ga instruction. 243 */ 244static __inline void 245ia64_ptc_ga(u_int64_t va, u_int64_t log2size) 246{ 247 __asm __volatile("ptc.ga %0,%1;; srlz.d;;" :: "r"(va), "r"(log2size)); 248} 249 250/* 251 * Generate a ptc.l instruction. 252 */ 253static __inline void 254ia64_ptc_l(u_int64_t va, u_int64_t log2size) 255{ 256 __asm __volatile("ptc.l %0,%1;; srlz.d;;" :: "r"(va), "r"(log2size)); 257} 258 259/* 260 * Read the value of psr. 261 */ 262static __inline u_int64_t 263ia64_get_psr(void) 264{ 265 u_int64_t result; 266 __asm __volatile("mov %0=psr;;" : "=r" (result)); 267 return result; 268} 269 270/* 271 * Define accessors for application registers. 272 */ 273 274#define IA64_AR(name) \ 275 \ 276static __inline u_int64_t \ 277ia64_get_##name(void) \ 278{ \ 279 u_int64_t result; \ 280 __asm __volatile("mov %0=ar." #name : "=r" (result)); \ 281 return result; \ 282} \ 283 \ 284static __inline void \ 285ia64_set_##name(u_int64_t v) \ 286{ \ 287 __asm __volatile("mov ar." #name "=%0" :: "r" (v)); \ 288} 289 290IA64_AR(k0) 291IA64_AR(k1) 292IA64_AR(k2) 293IA64_AR(k3) 294IA64_AR(k4) 295IA64_AR(k5) 296IA64_AR(k6) 297IA64_AR(k7) 298 299IA64_AR(rsc) 300IA64_AR(bsp) 301IA64_AR(bspstore) 302IA64_AR(rnat) 303 304IA64_AR(fcr) 305 306IA64_AR(eflag) 307IA64_AR(csd) 308IA64_AR(ssd) 309IA64_AR(cflg) 310IA64_AR(fsr) 311IA64_AR(fir) 312IA64_AR(fdr) 313 314IA64_AR(ccv) 315 316IA64_AR(unat) 317 318IA64_AR(fpsr) 319 320IA64_AR(itc) 321 322IA64_AR(pfs) 323IA64_AR(lc) 324IA64_AR(ec) 325 326/* 327 * Define accessors for control registers. 328 */ 329 330#define IA64_CR(name) \ 331 \ 332static __inline u_int64_t \ 333ia64_get_##name(void) \ 334{ \ 335 u_int64_t result; \ 336 __asm __volatile("mov %0=cr." #name : "=r" (result)); \ 337 return result; \ 338} \ 339 \ 340static __inline void \ 341ia64_set_##name(u_int64_t v) \ 342{ \ 343 __asm __volatile("mov cr." #name "=%0" :: "r" (v)); \ 344} 345 346IA64_CR(dcr) 347IA64_CR(itm) 348IA64_CR(iva) 349 350IA64_CR(pta) 351 352IA64_CR(ipsr) 353IA64_CR(isr) 354 355IA64_CR(iip) 356IA64_CR(ifa) 357IA64_CR(itir) 358IA64_CR(iipa) 359IA64_CR(ifs) 360IA64_CR(iim) 361IA64_CR(iha) 362 363IA64_CR(lid) 364IA64_CR(ivr) 365IA64_CR(tpr) 366IA64_CR(eoi) 367IA64_CR(irr0) 368IA64_CR(irr1) 369IA64_CR(irr2) 370IA64_CR(irr3) 371IA64_CR(itv) 372IA64_CR(pmv) 373IA64_CR(cmcv) 374 375IA64_CR(lrr0) 376IA64_CR(lrr1) 377 378/* 379 * Write a region register. 380 */ 381static __inline void 382ia64_set_rr(u_int64_t rrbase, u_int64_t v) 383{ 384 __asm __volatile("mov rr[%0]=%1;; srlz.d;;" 385 :: "r"(rrbase), "r"(v) : "memory"); 386} 387 388/* 389 * Read a CPUID register. 390 */ 391static __inline u_int64_t 392ia64_get_cpuid(int i) 393{ 394 u_int64_t result; 395 __asm __volatile("mov %0=cpuid[%1]" 396 : "=r" (result) : "r"(i)); 397 return result; 398} 399 400#endif 401 402#endif /* _MACHINE_IA64_CPU_H_ */ 403
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