bus.h (113350) | bus.h (114208) |
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1/* $NetBSD: bus.h,v 1.12 1997/10/01 08:25:15 fvdl Exp $ */ 2 3/*- 4 * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, --- 53 unchanged lines hidden (view full) --- 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 */ | 1/* $NetBSD: bus.h,v 1.12 1997/10/01 08:25:15 fvdl Exp $ */ 2 3/*- 4 * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, --- 53 unchanged lines hidden (view full) --- 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 */ |
70/* $FreeBSD: head/sys/ia64/include/bus.h 113350 2003-04-10 23:50:06Z mux $ */ | 70/* $FreeBSD: head/sys/ia64/include/bus.h 114208 2003-04-29 09:50:03Z marcel $ */ |
71 72#ifndef _MACHINE_BUS_H_ 73#define _MACHINE_BUS_H_ 74 | 71 72#ifndef _MACHINE_BUS_H_ 73#define _MACHINE_BUS_H_ 74 |
75/* 76 * Platform notes: 77 * o We don't use the _MACHINE_BUS_PIO_H_ and _MACHINE_BUS_MEMIO_H_ 78 * macros to conditionally compile for I/O port, memory mapped I/O 79 * or both. It's a micro-optimization that is not worth the pain 80 * because there is no I/O port space. I/O ports are emulated by 81 * doing memory mapped I/O in a special memory range. The address 82 * translation is slightly magic for I/O port accesses, but it does 83 * not warrant the overhead. 84 * 85 */ 86#define _MACHINE_BUS_MEMIO_H_ 87#define _MACHINE_BUS_PIO_H_ 88 |
|
75#include <machine/cpufunc.h> 76 77/* | 89#include <machine/cpufunc.h> 90 91/* |
78 * To remain compatible with NetBSD's interface, default to both memio and 79 * pio when neither of them is defined. 80 */ 81#if !defined(_MACHINE_BUS_PIO_H_) && !defined(_IA64_BUS_MEMIO_H_) 82#define _MACHINE_BUS_PIO_H_ 83#define _MACHINE_BUS_MEMIO_H_ 84#endif 85 86/* | |
87 * Values for the ia64 bus space tag, not to be used directly by MI code. 88 */ 89#define IA64_BUS_SPACE_IO 0 /* space is i/o space */ 90#define IA64_BUS_SPACE_MEM 1 /* space is mem space */ 91 92/* 93 * Bus address and size types 94 */ --- 10 unchanged lines hidden (view full) --- 105#define BUS_SPACE_UNRESTRICTED (~0) 106 107/* 108 * Access methods for bus resources and address space. 109 */ 110typedef int bus_space_tag_t; 111typedef u_long bus_space_handle_t; 112 | 92 * Values for the ia64 bus space tag, not to be used directly by MI code. 93 */ 94#define IA64_BUS_SPACE_IO 0 /* space is i/o space */ 95#define IA64_BUS_SPACE_MEM 1 /* space is mem space */ 96 97/* 98 * Bus address and size types 99 */ --- 10 unchanged lines hidden (view full) --- 110#define BUS_SPACE_UNRESTRICTED (~0) 111 112/* 113 * Access methods for bus resources and address space. 114 */ 115typedef int bus_space_tag_t; 116typedef u_long bus_space_handle_t; 117 |
118 |
|
113/* 114 * Map a region of device bus space into CPU virtual address space. 115 */ | 119/* 120 * Map a region of device bus space into CPU virtual address space. 121 */ |
116 | |
117#define BUS_SPACE_MAP_CACHEABLE 0x01 118#define BUS_SPACE_MAP_LINEAR 0x02 119 | 122#define BUS_SPACE_MAP_CACHEABLE 0x01 123#define BUS_SPACE_MAP_LINEAR 0x02 124 |
120int bus_space_map(bus_space_tag_t t, bus_addr_t addr, bus_size_t size, 121 int flags, bus_space_handle_t *bshp); | 125int 126bus_space_map(bus_space_tag_t bst, bus_addr_t addr, bus_size_t size, int flags, 127 bus_space_handle_t *bshp); |
122 | 128 |
129 |
|
123/* 124 * Unmap a region of device bus space. 125 */ | 130/* 131 * Unmap a region of device bus space. 132 */ |
126 | |
127static __inline void | 133static __inline void |
128bus_space_unmap(bus_space_tag_t t __unused, bus_space_handle_t bsh __unused, 129 bus_size_t size __unused) | 134bus_space_unmap(bus_space_tag_t bst __unused, bus_space_handle_t bsh __unused, 135 bus_size_t size __unused) |
130{ 131} 132 | 136{ 137} 138 |
139 |
|
133/* 134 * Get a new handle for a subregion of an already-mapped area of bus space. 135 */ | 140/* 141 * Get a new handle for a subregion of an already-mapped area of bus space. 142 */ |
136 | |
137static __inline int | 143static __inline int |
138bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh, 139 bus_size_t offset, bus_size_t size, 140 bus_space_handle_t *nbshp) | 144bus_space_subregion(bus_space_tag_t bst, bus_space_handle_t bsh, 145 bus_size_t ofs, bus_size_t size, bus_space_handle_t *nbshp) |
141{ | 146{ |
142 *nbshp = bsh + offset; | 147 *nbshp = bsh + ofs; |
143 return (0); 144} 145 | 148 return (0); 149} 150 |
151 |
|
146/* 147 * Allocate a region of memory that is accessible to devices in bus space. 148 */ | 152/* 153 * Allocate a region of memory that is accessible to devices in bus space. 154 */ |
155int 156bus_space_alloc(bus_space_tag_t bst, bus_addr_t rstart, bus_addr_t rend, 157 bus_size_t size, bus_size_t align, bus_size_t boundary, int flags, 158 bus_addr_t *addrp, bus_space_handle_t *bshp); |
|
149 | 159 |
150int bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart, 151 bus_addr_t rend, bus_size_t size, bus_size_t align, 152 bus_size_t boundary, int flags, bus_addr_t *addrp, 153 bus_space_handle_t *bshp); | |
154 155/* 156 * Free a region of bus space accessible memory. 157 */ | 160 161/* 162 * Free a region of bus space accessible memory. 163 */ |
164void 165bus_space_free(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t size); |
|
158 | 166 |
159void bus_space_free(bus_space_tag_t t, bus_space_handle_t bsh, 160 bus_size_t size); | |
161 | 167 |
162#if defined(_MACHINE_BUS_PIO_H_) || defined(_MACHINE_BUS_MEMIO_H_) 163 | |
164/* | 168/* |
165 * Read a 1, 2, 4, or 8 byte quantity from bus space 166 * described by tag/handle/offset. | 169 * Bus read/write barrier method. |
167 */ | 170 */ |
168static __inline u_int8_t bus_space_read_1(bus_space_tag_t tag, 169 bus_space_handle_t handle, 170 bus_size_t offset); | 171#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */ 172#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */ |
171 | 173 |
172static __inline u_int16_t bus_space_read_2(bus_space_tag_t tag, 173 bus_space_handle_t handle, 174 bus_size_t offset); | 174static __inline void 175bus_space_barrier(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t ofs, 176 bus_size_t size, int flags) 177{ 178 ia64_mf_a(); 179 ia64_mf(); 180} |
175 | 181 |
176static __inline u_int32_t bus_space_read_4(bus_space_tag_t tag, 177 bus_space_handle_t handle, 178 bus_size_t offset); | |
179 | 182 |
180static __inline u_int8_t 181bus_space_read_1(bus_space_tag_t tag, bus_space_handle_t handle, 182 bus_size_t offset) | 183/* 184 * Read 1 unit of data from bus space described by the tag, handle and ofs 185 * tuple. A unit of data can be 1 byte, 2 bytes, 4 bytes or 8 bytes. The 186 * data is returned. 187 */ 188static __inline uint8_t 189bus_space_read_1(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t ofs) |
183{ | 190{ |
184#if defined (_MACHINE_BUS_PIO_H_) 185#if defined (_MACHINE_BUS_MEMIO_H_) 186 if (tag == IA64_BUS_SPACE_IO) 187#endif 188 return (inb(handle + offset)); 189#endif 190#if defined (_MACHINE_BUS_MEMIO_H_) 191 return (readb(handle + offset)); 192#endif | 191 uint8_t __volatile *bsp; 192 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 193 __MEMIO_ADDR(bsh + ofs); 194 return (*bsp); |
193} 194 | 195} 196 |
195static __inline u_int16_t 196bus_space_read_2(bus_space_tag_t tag, bus_space_handle_t handle, 197 bus_size_t offset) | 197static __inline uint16_t 198bus_space_read_2(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t ofs) |
198{ | 199{ |
199#if defined(_MACHINE_BUS_PIO_H_) 200#if defined(_MACHINE_BUS_MEMIO_H_) 201 if (tag == IA64_BUS_SPACE_IO) 202#endif 203 return (inw(handle + offset)); 204#endif 205#if defined(_MACHINE_BUS_MEMIO_H_) 206 return (readw(handle + offset)); 207#endif | 200 uint16_t __volatile *bsp; 201 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 202 __MEMIO_ADDR(bsh + ofs); 203 return (*bsp); |
208} 209 | 204} 205 |
210static __inline u_int32_t 211bus_space_read_4(bus_space_tag_t tag, bus_space_handle_t handle, 212 bus_size_t offset) | 206static __inline uint32_t 207bus_space_read_4(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t ofs) |
213{ | 208{ |
214#if defined(_MACHINE_BUS_PIO_H_) 215#if defined(_MACHINE_BUS_MEMIO_H_) 216 if (tag == IA64_BUS_SPACE_IO) 217#endif 218 return (inl(handle + offset)); 219#endif 220#if defined(_MACHINE_BUS_MEMIO_H_) 221 return (readl(handle + offset)); 222#endif | 209 uint32_t __volatile *bsp; 210 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 211 __MEMIO_ADDR(bsh + ofs); 212 return (*bsp); |
223} 224 | 213} 214 |
225#if 0 /* Cause a link error for bus_space_read_8 */ 226#define bus_space_read_8(t, h, o) !!! bus_space_read_8 unimplemented !!! 227#endif | 215static __inline uint64_t 216bus_space_read_8(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t ofs) 217{ 218 uint64_t __volatile *bsp; 219 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 220 __MEMIO_ADDR(bsh + ofs); 221 return (*bsp); 222} |
228 | 223 |
224 |
|
229/* | 225/* |
230 * Read `count' 1, 2, 4, or 8 byte quantities from bus space 231 * described by tag/handle/offset and copy into buffer provided. | 226 * Write 1 unit of data to bus space described by the tag, handle and ofs 227 * tuple. A unit of data can be 1 byte, 2 bytes, 4 bytes or 8 bytes. The 228 * data is passed by value. |
232 */ | 229 */ |
233static __inline void bus_space_read_multi_1(bus_space_tag_t tag, 234 bus_space_handle_t bsh, 235 bus_size_t offset, u_int8_t *addr, 236 size_t count); | 230static __inline void 231bus_space_write_1(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t ofs, 232 uint8_t val) 233{ 234 uint8_t __volatile *bsp; 235 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 236 __MEMIO_ADDR(bsh + ofs); 237 *bsp = val; 238} |
237 | 239 |
238static __inline void bus_space_read_multi_2(bus_space_tag_t tag, 239 bus_space_handle_t bsh, 240 bus_size_t offset, u_int16_t *addr, 241 size_t count); 242 243static __inline void bus_space_read_multi_4(bus_space_tag_t tag, 244 bus_space_handle_t bsh, 245 bus_size_t offset, u_int32_t *addr, 246 size_t count); 247 | |
248static __inline void | 240static __inline void |
249bus_space_read_multi_1(bus_space_tag_t tag, bus_space_handle_t bsh, 250 bus_size_t offset, u_int8_t *addr, size_t count) | 241bus_space_write_2(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t ofs, 242 uint16_t val) |
251{ | 243{ |
252#if defined(_MACHINE_BUS_PIO_H_) 253#if defined(_MACHINE_BUS_MEMIO_H_) 254 if (tag == IA64_BUS_SPACE_IO) 255#endif 256 while (count--) 257 *addr++ = inb(bsh + offset); 258#endif 259#if defined(_MACHINE_BUS_MEMIO_H_) 260#if defined(_MACHINE_BUS_PIO_H_) 261 else 262#endif 263 while (count--) 264 *addr++ = readb(bsh + offset); 265#endif | 244 uint16_t __volatile *bsp; 245 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 246 __MEMIO_ADDR(bsh + ofs); 247 *bsp = val; |
266} 267 268static __inline void | 248} 249 250static __inline void |
269bus_space_read_multi_2(bus_space_tag_t tag, bus_space_handle_t bsh, 270 bus_size_t offset, u_int16_t *addr, size_t count) | 251bus_space_write_4(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t ofs, 252 uint32_t val) |
271{ | 253{ |
272 bus_addr_t baddr = bsh + offset; 273#if defined(_MACHINE_BUS_PIO_H_) 274#if defined(_MACHINE_BUS_MEMIO_H_) 275 if (tag == IA64_BUS_SPACE_IO) 276#endif 277 while (count--) 278 *addr++ = inw(baddr); 279#endif 280#if defined(_MACHINE_BUS_MEMIO_H_) 281#if defined(_MACHINE_BUS_PIO_H_) 282 else 283#endif 284 while (count--) 285 *addr++ = readw(baddr); 286#endif | 254 uint32_t __volatile *bsp; 255 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 256 __MEMIO_ADDR(bsh + ofs); 257 *bsp = val; |
287} 288 289static __inline void | 258} 259 260static __inline void |
290bus_space_read_multi_4(bus_space_tag_t tag, bus_space_handle_t bsh, 291 bus_size_t offset, u_int32_t *addr, size_t count) | 261bus_space_write_8(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t ofs, 262 uint64_t val) |
292{ | 263{ |
293 bus_addr_t baddr = bsh + offset; 294#if defined(_MACHINE_BUS_PIO_H_) 295#if defined(_MACHINE_BUS_MEMIO_H_) 296 if (tag == IA64_BUS_SPACE_IO) 297#endif 298 while (count--) 299 *addr++ = inl(baddr); 300#endif 301#if defined(_MACHINE_BUS_MEMIO_H_) 302#if defined(_MACHINE_BUS_PIO_H_) 303 else 304#endif 305 while (count--) 306 *addr++ = readl(baddr); 307#endif | 264 uint64_t __volatile *bsp; 265 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 266 __MEMIO_ADDR(bsh + ofs); 267 *bsp = val; |
308} 309 | 268} 269 |
310#if 0 /* Cause a link error for bus_space_read_multi_8 */ 311#define bus_space_read_multi_8 !!! bus_space_read_multi_8 unimplemented !!! 312#endif | |
313 314/* | 270 271/* |
315 * Read `count' 1, 2, 4, or 8 byte quantities from bus space 316 * described by tag/handle and starting at `offset' and copy into 317 * buffer provided. | 272 * Read count units of data from bus space described by the tag, handle and 273 * ofs tuple. A unit of data can be 1 byte, 2 bytes, 4 bytes or 8 bytes. The 274 * data is returned in the buffer passed by reference. |
318 */ | 275 */ |
319static __inline void bus_space_read_region_1(bus_space_tag_t tag, 320 bus_space_handle_t bsh, 321 bus_size_t offset, u_int8_t *addr, 322 size_t count); | 276static __inline void 277bus_space_read_multi_1(bus_space_tag_t bst, bus_space_handle_t bsh, 278 bus_size_t ofs, uint8_t *bufp, size_t count) 279{ 280 uint8_t __volatile *bsp; 281 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 282 __MEMIO_ADDR(bsh + ofs); 283 while (count-- > 0) 284 *bufp++ = *bsp; 285} |
323 | 286 |
324static __inline void bus_space_read_region_2(bus_space_tag_t tag, 325 bus_space_handle_t bsh, 326 bus_size_t offset, u_int16_t *addr, 327 size_t count); 328 329static __inline void bus_space_read_region_4(bus_space_tag_t tag, 330 bus_space_handle_t bsh, 331 bus_size_t offset, u_int32_t *addr, 332 size_t count); 333 334 | |
335static __inline void | 287static __inline void |
336bus_space_read_region_1(bus_space_tag_t tag, bus_space_handle_t bsh, 337 bus_size_t offset, u_int8_t *addr, size_t count) | 288bus_space_read_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh, 289 bus_size_t ofs, uint16_t *bufp, size_t count) |
338{ | 290{ |
339 bus_addr_t baddr = bsh + offset; 340#if defined(_MACHINE_BUS_PIO_H_) 341#if defined(_MACHINE_BUS_MEMIO_H_) 342 if (tag == IA64_BUS_SPACE_IO) 343#endif 344 while (count--) { 345 *addr++ = inb(baddr); 346 baddr += 1; 347 } 348#endif 349#if defined(_MACHINE_BUS_MEMIO_H_) 350#if defined(_MACHINE_BUS_PIO_H_) 351 else 352#endif 353 while (count--) { 354 *addr++ = readb(baddr); 355 baddr += 1; 356 } 357#endif | 291 uint16_t __volatile *bsp; 292 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 293 __MEMIO_ADDR(bsh + ofs); 294 while (count-- > 0) 295 *bufp++ = *bsp; |
358} 359 360static __inline void | 296} 297 298static __inline void |
361bus_space_read_region_2(bus_space_tag_t tag, bus_space_handle_t bsh, 362 bus_size_t offset, u_int16_t *addr, size_t count) | 299bus_space_read_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh, 300 bus_size_t ofs, uint32_t *bufp, size_t count) |
363{ | 301{ |
364 bus_addr_t baddr = bsh + offset; 365#if defined(_MACHINE_BUS_PIO_H_) 366#if defined(_MACHINE_BUS_MEMIO_H_) 367 if (tag == IA64_BUS_SPACE_IO) 368#endif 369 while (count--) { 370 *addr++ = inw(baddr); 371 baddr += 2; 372 } 373#endif 374#if defined(_MACHINE_BUS_MEMIO_H_) 375#if defined(_MACHINE_BUS_PIO_H_) 376 else 377#endif 378 while (count--) { 379 *addr++ = readw(baddr); 380 baddr += 2; 381 } 382#endif | 302 uint32_t __volatile *bsp; 303 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 304 __MEMIO_ADDR(bsh + ofs); 305 while (count-- > 0) 306 *bufp++ = *bsp; |
383} 384 385static __inline void | 307} 308 309static __inline void |
386bus_space_read_region_4(bus_space_tag_t tag, bus_space_handle_t bsh, 387 bus_size_t offset, u_int32_t *addr, size_t count) | 310bus_space_read_multi_8(bus_space_tag_t bst, bus_space_handle_t bsh, 311 bus_size_t ofs, uint64_t *bufp, size_t count) |
388{ | 312{ |
389 bus_addr_t baddr = bsh + offset; 390#if defined(_MACHINE_BUS_PIO_H_) 391#if defined(_MACHINE_BUS_MEMIO_H_) 392 if (tag == IA64_BUS_SPACE_IO) 393#endif 394 while (count--) { 395 *addr++ = inl(baddr); 396 baddr += 4; 397 } 398#endif 399#if defined(_MACHINE_BUS_MEMIO_H_) 400#if defined(_MACHINE_BUS_PIO_H_) 401 else 402#endif 403 while (count--) { 404 *addr++ = readb(baddr); 405 baddr += 4; 406 } 407#endif | 313 uint64_t __volatile *bsp; 314 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 315 __MEMIO_ADDR(bsh + ofs); 316 while (count-- > 0) 317 *bufp++ = *bsp; |
408} 409 | 318} 319 |
410#if 0 /* Cause a link error for bus_space_read_region_8 */ 411#define bus_space_read_region_8 !!! bus_space_read_region_8 unimplemented !!! 412#endif | |
413 414/* | 320 321/* |
415 * Write the 1, 2, 4, or 8 byte value `value' to bus space 416 * described by tag/handle/offset. | 322 * Write count units of data to bus space described by the tag, handle and 323 * ofs tuple. A unit of data can be 1 byte, 2 bytes, 4 bytes or 8 bytes. The 324 * data is read from the buffer passed by reference. |
417 */ | 325 */ |
326static __inline void 327bus_space_write_multi_1(bus_space_tag_t bst, bus_space_handle_t bsh, 328 bus_size_t ofs, const uint8_t *bufp, size_t count) 329{ 330 uint8_t __volatile *bsp; 331 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 332 __MEMIO_ADDR(bsh + ofs); 333 while (count-- > 0) 334 *bsp = *bufp++; 335} |
|
418 | 336 |
419static __inline void bus_space_write_1(bus_space_tag_t tag, 420 bus_space_handle_t bsh, 421 bus_size_t offset, u_int8_t value); 422 423static __inline void bus_space_write_2(bus_space_tag_t tag, 424 bus_space_handle_t bsh, 425 bus_size_t offset, u_int16_t value); 426 427static __inline void bus_space_write_4(bus_space_tag_t tag, 428 bus_space_handle_t bsh, 429 bus_size_t offset, u_int32_t value); 430 | |
431static __inline void | 337static __inline void |
432bus_space_write_1(bus_space_tag_t tag, bus_space_handle_t bsh, 433 bus_size_t offset, u_int8_t value) | 338bus_space_write_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh, 339 bus_size_t ofs, const uint16_t *bufp, size_t count) |
434{ | 340{ |
435#if defined(_MACHINE_BUS_PIO_H_) 436#if defined(_MACHINE_BUS_MEMIO_H_) 437 if (tag == IA64_BUS_SPACE_IO) 438#endif 439 outb(bsh + offset, value); 440#endif 441#if defined(_MACHINE_BUS_MEMIO_H_) 442#if defined(_MACHINE_BUS_PIO_H_) 443 else 444#endif 445 writeb(bsh + offset, value); 446#endif | 341 uint16_t __volatile *bsp; 342 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 343 __MEMIO_ADDR(bsh + ofs); 344 while (count-- > 0) 345 *bsp = *bufp++; |
447} 448 449static __inline void | 346} 347 348static __inline void |
450bus_space_write_2(bus_space_tag_t tag, bus_space_handle_t bsh, 451 bus_size_t offset, u_int16_t value) | 349bus_space_write_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh, 350 bus_size_t ofs, const uint32_t *bufp, size_t count) |
452{ | 351{ |
453#if defined(_MACHINE_BUS_PIO_H_) 454#if defined(_MACHINE_BUS_MEMIO_H_) 455 if (tag == IA64_BUS_SPACE_IO) 456#endif 457 outw(bsh + offset, value); 458#endif 459#if defined(_MACHINE_BUS_MEMIO_H_) 460#if defined(_MACHINE_BUS_PIO_H_) 461 else 462#endif 463 writew(bsh + offset, value); 464#endif | 352 uint32_t __volatile *bsp; 353 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 354 __MEMIO_ADDR(bsh + ofs); 355 while (count-- > 0) 356 *bsp = *bufp++; |
465} 466 467static __inline void | 357} 358 359static __inline void |
468bus_space_write_4(bus_space_tag_t tag, bus_space_handle_t bsh, 469 bus_size_t offset, u_int32_t value) | 360bus_space_write_multi_8(bus_space_tag_t bst, bus_space_handle_t bsh, 361 bus_size_t ofs, const uint64_t *bufp, size_t count) |
470{ | 362{ |
471#if defined(_MACHINE_BUS_PIO_H_) 472#if defined(_MACHINE_BUS_MEMIO_H_) 473 if (tag == IA64_BUS_SPACE_IO) 474#endif 475 outl(bsh + offset, value); 476#endif 477#if defined(_MACHINE_BUS_MEMIO_H_) 478#if defined(_MACHINE_BUS_PIO_H_) 479 else 480#endif 481 writel(bsh + offset, value); 482#endif | 363 uint64_t __volatile *bsp; 364 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 365 __MEMIO_ADDR(bsh + ofs); 366 while (count-- > 0) 367 *bsp = *bufp++; |
483} 484 | 368} 369 |
485#if 0 /* Cause a link error for bus_space_write_8 */ 486#define bus_space_write_8 !!! bus_space_write_8 not implemented !!! 487#endif | |
488 489/* | 370 371/* |
490 * Write `count' 1, 2, 4, or 8 byte quantities from the buffer 491 * provided to bus space described by tag/handle/offset. | 372 * Read count units of data from bus space described by the tag, handle and 373 * ofs tuple. A unit of data can be 1 byte, 2 bytes, 4 bytes or 8 bytes. The 374 * data is written to the buffer passed by reference and read from successive 375 * bus space addresses. Access is unordered. |
492 */ | 376 */ |
377static __inline void 378bus_space_read_region_1(bus_space_tag_t bst, bus_space_handle_t bsh, 379 bus_size_t ofs, uint8_t *bufp, size_t count) 380{ 381 uint8_t __volatile *bsp; 382 while (count-- > 0) { 383 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 384 __MEMIO_ADDR(bsh + ofs); 385 *bufp++ = *bsp; 386 ofs += 1; 387 } 388} |
|
493 | 389 |
494static __inline void bus_space_write_multi_1(bus_space_tag_t tag, 495 bus_space_handle_t bsh, 496 bus_size_t offset, 497 const u_int8_t *addr, 498 size_t count); 499static __inline void bus_space_write_multi_2(bus_space_tag_t tag, 500 bus_space_handle_t bsh, 501 bus_size_t offset, 502 const u_int16_t *addr, 503 size_t count); 504 505static __inline void bus_space_write_multi_4(bus_space_tag_t tag, 506 bus_space_handle_t bsh, 507 bus_size_t offset, 508 const u_int32_t *addr, 509 size_t count); 510 | |
511static __inline void | 390static __inline void |
512bus_space_write_multi_1(bus_space_tag_t tag, bus_space_handle_t bsh, 513 bus_size_t offset, const u_int8_t *addr, size_t count) | 391bus_space_read_region_2(bus_space_tag_t bst, bus_space_handle_t bsh, 392 bus_size_t ofs, uint16_t *bufp, size_t count) |
514{ | 393{ |
515 bus_addr_t baddr = bsh + offset; 516#if defined(_MACHINE_BUS_PIO_H_) 517#if defined(_MACHINE_BUS_MEMIO_H_) 518 if (tag == IA64_BUS_SPACE_IO) 519#endif 520 while (count--) 521 outb(baddr, *addr++); 522#endif 523#if defined(_MACHINE_BUS_MEMIO_H_) 524#if defined(_MACHINE_BUS_PIO_H_) 525 else 526#endif 527 while (count--) 528 writeb(baddr, *addr++); 529#endif | 394 uint16_t __volatile *bsp; 395 while (count-- > 0) { 396 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 397 __MEMIO_ADDR(bsh + ofs); 398 *bufp++ = *bsp; 399 ofs += 2; 400 } |
530} 531 532static __inline void | 401} 402 403static __inline void |
533bus_space_write_multi_2(bus_space_tag_t tag, bus_space_handle_t bsh, 534 bus_size_t offset, const u_int16_t *addr, size_t count) | 404bus_space_read_region_4(bus_space_tag_t bst, bus_space_handle_t bsh, 405 bus_size_t ofs, uint32_t *bufp, size_t count) |
535{ | 406{ |
536 bus_addr_t baddr = bsh + offset; 537#if defined(_MACHINE_BUS_PIO_H_) 538#if defined(_MACHINE_BUS_MEMIO_H_) 539 if (tag == IA64_BUS_SPACE_IO) 540#endif 541 while (count--) 542 outw(baddr, *addr++); 543#endif 544#if defined(_MACHINE_BUS_MEMIO_H_) 545#if defined(_MACHINE_BUS_PIO_H_) 546 else 547#endif 548 while (count--) 549 writew(baddr, *addr++); 550#endif | 407 uint32_t __volatile *bsp; 408 while (count-- > 0) { 409 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 410 __MEMIO_ADDR(bsh + ofs); 411 *bufp++ = *bsp; 412 ofs += 4; 413 } |
551} 552 553static __inline void | 414} 415 416static __inline void |
554bus_space_write_multi_4(bus_space_tag_t tag, bus_space_handle_t bsh, 555 bus_size_t offset, const u_int32_t *addr, size_t count) | 417bus_space_read_region_8(bus_space_tag_t bst, bus_space_handle_t bsh, 418 bus_size_t ofs, uint64_t *bufp, size_t count) |
556{ | 419{ |
557 bus_addr_t baddr = bsh + offset; 558#if defined(_MACHINE_BUS_PIO_H_) 559#if defined(_MACHINE_BUS_MEMIO_H_) 560 if (tag == IA64_BUS_SPACE_IO) 561#endif 562 while (count--) 563 outl(baddr, *addr++); 564#endif 565#if defined(_MACHINE_BUS_MEMIO_H_) 566#if defined(_MACHINE_BUS_PIO_H_) 567 else 568#endif 569 while (count--) 570 writel(baddr, *addr++); 571#endif | 420 uint64_t __volatile *bsp; 421 while (count-- > 0) { 422 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 423 __MEMIO_ADDR(bsh + ofs); 424 *bufp++ = *bsp; 425 ofs += 8; 426 } |
572} 573 | 427} 428 |
574#if 0 /* Cause a link error for bus_space_write_multi_8 */ 575#define bus_space_write_multi_8(t, h, o, a, c) \ 576 !!! bus_space_write_multi_8 unimplemented !!! 577#endif | |
578 579/* | 429 430/* |
580 * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided 581 * to bus space described by tag/handle starting at `offset'. | 431 * Write count units of data from bus space described by the tag, handle and 432 * ofs tuple. A unit of data can be 1 byte, 2 bytes, 4 bytes or 8 bytes. The 433 * data is read from the buffer passed by reference and written to successive 434 * bus space addresses. Access is unordered. |
582 */ | 435 */ |
436static __inline void 437bus_space_write_region_1(bus_space_tag_t bst, bus_space_handle_t bsh, 438 bus_size_t ofs, const uint8_t *bufp, size_t count) 439{ 440 uint8_t __volatile *bsp; 441 while (count-- > 0) { 442 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 443 __MEMIO_ADDR(bsh + ofs); 444 *bsp = *bufp++; 445 ofs += 1; 446 } 447} |
|
583 | 448 |
584static __inline void bus_space_write_region_1(bus_space_tag_t tag, 585 bus_space_handle_t bsh, 586 bus_size_t offset, 587 const u_int8_t *addr, 588 size_t count); 589static __inline void bus_space_write_region_2(bus_space_tag_t tag, 590 bus_space_handle_t bsh, 591 bus_size_t offset, 592 const u_int16_t *addr, 593 size_t count); 594static __inline void bus_space_write_region_4(bus_space_tag_t tag, 595 bus_space_handle_t bsh, 596 bus_size_t offset, 597 const u_int32_t *addr, 598 size_t count); 599 | |
600static __inline void | 449static __inline void |
601bus_space_write_region_1(bus_space_tag_t tag, bus_space_handle_t bsh, 602 bus_size_t offset, const u_int8_t *addr, size_t count) | 450bus_space_write_region_2(bus_space_tag_t bst, bus_space_handle_t bsh, 451 bus_size_t ofs, const uint16_t *bufp, size_t count) |
603{ | 452{ |
604 bus_addr_t baddr = bsh + offset; 605#if defined(_MACHINE_BUS_PIO_H_) 606#if defined(_MACHINE_BUS_MEMIO_H_) 607 if (tag == IA64_BUS_SPACE_IO) 608#endif 609 while (count--) { 610 outb(baddr, *addr++); 611 baddr += 1; 612 } 613#endif 614#if defined(_MACHINE_BUS_MEMIO_H_) 615#if defined(_MACHINE_BUS_PIO_H_) 616 else 617#endif 618 while (count--) { 619 writeb(baddr, *addr++); 620 baddr += 1; 621 } 622#endif | 453 uint16_t __volatile *bsp; 454 while (count-- > 0) { 455 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 456 __MEMIO_ADDR(bsh + ofs); 457 *bsp = *bufp++; 458 ofs += 2; 459 } |
623} 624 625static __inline void | 460} 461 462static __inline void |
626bus_space_write_region_2(bus_space_tag_t tag, bus_space_handle_t bsh, 627 bus_size_t offset, const u_int16_t *addr, size_t count) | 463bus_space_write_region_4(bus_space_tag_t bst, bus_space_handle_t bsh, 464 bus_size_t ofs, const uint32_t *bufp, size_t count) |
628{ | 465{ |
629 bus_addr_t baddr = bsh + offset; 630#if defined(_MACHINE_BUS_PIO_H_) 631#if defined(_MACHINE_BUS_MEMIO_H_) 632 if (tag == IA64_BUS_SPACE_IO) 633#endif 634 while (count--) { 635 outw(baddr, *addr++); 636 baddr += 2; 637 } 638#endif 639#if defined(_MACHINE_BUS_MEMIO_H_) 640#if defined(_MACHINE_BUS_PIO_H_) 641 else 642#endif 643 while (count--) { 644 writew(baddr, *addr++); 645 baddr += 2; 646 } 647#endif | 466 uint32_t __volatile *bsp; 467 while (count-- > 0) { 468 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 469 __MEMIO_ADDR(bsh + ofs); 470 *bsp = *bufp++; 471 ofs += 4; 472 } |
648} 649 650static __inline void | 473} 474 475static __inline void |
651bus_space_write_region_4(bus_space_tag_t tag, bus_space_handle_t bsh, 652 bus_size_t offset, const u_int32_t *addr, size_t count) | 476bus_space_write_region_8(bus_space_tag_t bst, bus_space_handle_t bsh, 477 bus_size_t ofs, const uint64_t *bufp, size_t count) |
653{ | 478{ |
654 bus_addr_t baddr = bsh + offset; 655#if defined(_MACHINE_BUS_PIO_H_) 656#if defined(_MACHINE_BUS_MEMIO_H_) 657 if (tag == IA64_BUS_SPACE_IO) 658#endif 659 while (count--) { 660 outl(baddr, *addr++); 661 baddr += 4; 662 } 663#endif 664#if defined(_MACHINE_BUS_MEMIO_H_) 665#if defined(_MACHINE_BUS_PIO_H_) 666 else 667#endif 668 while (count--) { 669 writel(baddr, *addr++); 670 baddr += 4; 671 } 672#endif | 479 uint64_t __volatile *bsp; 480 while (count-- > 0) { 481 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 482 __MEMIO_ADDR(bsh + ofs); 483 *bsp = *bufp++; 484 ofs += 8; 485 } |
673} 674 | 486} 487 |
675#if 0 /* Cause a link error for bus_space_write_region_8 */ 676#define bus_space_write_region_8 \ 677 !!! bus_space_write_region_8 unimplemented !!! 678#endif | |
679 680/* | 488 489/* |
681 * Write the 1, 2, 4, or 8 byte value `val' to bus space described 682 * by tag/handle/offset `count' times. | 490 * Write count units of data from bus space described by the tag, handle and 491 * ofs tuple. A unit of data can be 1 byte, 2 bytes, 4 bytes or 8 bytes. The 492 * data is passed by value. Writes are unordered. |
683 */ | 493 */ |
684 685static __inline void bus_space_set_multi_1(bus_space_tag_t tag, 686 bus_space_handle_t bsh, 687 bus_size_t offset, 688 u_int8_t value, size_t count); 689static __inline void bus_space_set_multi_2(bus_space_tag_t tag, 690 bus_space_handle_t bsh, 691 bus_size_t offset, 692 u_int16_t value, size_t count); 693static __inline void bus_space_set_multi_4(bus_space_tag_t tag, 694 bus_space_handle_t bsh, 695 bus_size_t offset, 696 u_int32_t value, size_t count); 697 | |
698static __inline void | 494static __inline void |
699bus_space_set_multi_1(bus_space_tag_t tag, bus_space_handle_t bsh, 700 bus_size_t offset, u_int8_t value, size_t count) | 495bus_space_set_multi_1(bus_space_tag_t bst, bus_space_handle_t bsh, 496 bus_size_t ofs, uint8_t val, size_t count) |
701{ | 497{ |
702 bus_addr_t addr = bsh + offset; 703 704#if defined(_MACHINE_BUS_PIO_H_) 705#if defined(_MACHINE_BUS_MEMIO_H_) 706 if (tag == IA64_BUS_SPACE_IO) 707#endif 708 while (count--) 709 outb(addr, value); 710#endif 711#if defined(_MACHINE_BUS_MEMIO_H_) 712#if defined(_MACHINE_BUS_PIO_H_) 713 else 714#endif 715 while (count--) 716 writeb(addr, value); 717#endif | 498 uint8_t __volatile *bsp; 499 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 500 __MEMIO_ADDR(bsh + ofs); 501 while (count-- > 0) 502 *bsp = val; |
718} 719 720static __inline void | 503} 504 505static __inline void |
721bus_space_set_multi_2(bus_space_tag_t tag, bus_space_handle_t bsh, 722 bus_size_t offset, u_int16_t value, size_t count) | 506bus_space_set_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh, 507 bus_size_t ofs, uint16_t val, size_t count) |
723{ | 508{ |
724 bus_addr_t addr = bsh + offset; 725 726#if defined(_MACHINE_BUS_PIO_H_) 727#if defined(_MACHINE_BUS_MEMIO_H_) 728 if (tag == IA64_BUS_SPACE_IO) 729#endif 730 while (count--) 731 outw(addr, value); 732#endif 733#if defined(_MACHINE_BUS_MEMIO_H_) 734#if defined(_MACHINE_BUS_PIO_H_) 735 else 736#endif 737 while (count--) 738 writew(addr, value); 739#endif | 509 uint16_t __volatile *bsp; 510 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 511 __MEMIO_ADDR(bsh + ofs); 512 while (count-- > 0) 513 *bsp = val; |
740} 741 742static __inline void | 514} 515 516static __inline void |
743bus_space_set_multi_4(bus_space_tag_t tag, bus_space_handle_t bsh, 744 bus_size_t offset, u_int32_t value, size_t count) | 517bus_space_set_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh, 518 bus_size_t ofs, uint32_t val, size_t count) |
745{ | 519{ |
746 bus_addr_t addr = bsh + offset; | 520 uint32_t __volatile *bsp; 521 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 522 __MEMIO_ADDR(bsh + ofs); 523 while (count-- > 0) 524 *bsp = val; 525} |
747 | 526 |
748#if defined(_MACHINE_BUS_PIO_H_) 749#if defined(_MACHINE_BUS_MEMIO_H_) 750 if (tag == IA64_BUS_SPACE_IO) 751#endif 752 while (count--) 753 outl(addr, value); 754#endif 755#if defined(_MACHINE_BUS_MEMIO_H_) 756#if defined(_MACHINE_BUS_PIO_H_) 757 else 758#endif 759 while (count--) 760 writel(addr, value); 761#endif | 527static __inline void 528bus_space_set_multi_8(bus_space_tag_t bst, bus_space_handle_t bsh, 529 bus_size_t ofs, uint64_t val, size_t count) 530{ 531 uint64_t __volatile *bsp; 532 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 533 __MEMIO_ADDR(bsh + ofs); 534 while (count-- > 0) 535 *bsp = val; |
762} 763 | 536} 537 |
764#if 0 /* Cause a link error for bus_space_set_multi_8 */ 765#define bus_space_set_multi_8 !!! bus_space_set_multi_8 unimplemented !!! 766#endif | |
767 768/* | 538 539/* |
769 * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described 770 * by tag/handle starting at `offset'. | 540 * Write count units of data from bus space described by the tag, handle and 541 * ofs tuple. A unit of data can be 1 byte, 2 bytes, 4 bytes or 8 bytes. The 542 * data is passed by value and written to successive bus space addresses. 543 * Writes are unordered. |
771 */ | 544 */ |
772 773static __inline void bus_space_set_region_1(bus_space_tag_t tag, 774 bus_space_handle_t bsh, 775 bus_size_t offset, u_int8_t value, 776 size_t count); 777static __inline void bus_space_set_region_2(bus_space_tag_t tag, 778 bus_space_handle_t bsh, 779 bus_size_t offset, u_int16_t value, 780 size_t count); 781static __inline void bus_space_set_region_4(bus_space_tag_t tag, 782 bus_space_handle_t bsh, 783 bus_size_t offset, u_int32_t value, 784 size_t count); 785 | |
786static __inline void | 545static __inline void |
787bus_space_set_region_1(bus_space_tag_t tag, bus_space_handle_t bsh, 788 bus_size_t offset, u_int8_t value, size_t count) | 546bus_space_set_region_1(bus_space_tag_t bst, bus_space_handle_t bsh, 547 bus_size_t ofs, uint8_t val, size_t count) |
789{ | 548{ |
790 bus_addr_t addr = bsh + offset; 791 792#if defined(_MACHINE_BUS_PIO_H_) 793#if defined(_MACHINE_BUS_MEMIO_H_) 794 if (tag == IA64_BUS_SPACE_IO) 795#endif 796 for (; count != 0; count--, addr++) 797 outb(addr, value); 798#endif 799#if defined(_MACHINE_BUS_MEMIO_H_) 800#if defined(_MACHINE_BUS_PIO_H_) 801 else 802#endif 803 for (; count != 0; count--, addr++) 804 writeb(addr, value); 805#endif | 549 uint8_t __volatile *bsp; 550 while (count-- > 0) { 551 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 552 __MEMIO_ADDR(bsh + ofs); 553 *bsp = val; 554 ofs += 1; 555 } |
806} 807 808static __inline void | 556} 557 558static __inline void |
809bus_space_set_region_2(bus_space_tag_t tag, bus_space_handle_t bsh, 810 bus_size_t offset, u_int16_t value, size_t count) | 559bus_space_set_region_2(bus_space_tag_t bst, bus_space_handle_t bsh, 560 bus_size_t ofs, uint16_t val, size_t count) |
811{ | 561{ |
812 bus_addr_t addr = bsh + offset; 813 814#if defined(_MACHINE_BUS_PIO_H_) 815#if defined(_MACHINE_BUS_MEMIO_H_) 816 if (tag == IA64_BUS_SPACE_IO) 817#endif 818 for (; count != 0; count--, addr += 2) 819 outw(addr, value); 820#endif 821#if defined(_MACHINE_BUS_MEMIO_H_) 822#if defined(_MACHINE_BUS_PIO_H_) 823 else 824#endif 825 for (; count != 0; count--, addr += 2) 826 writew(addr, value); 827#endif | 562 uint16_t __volatile *bsp; 563 while (count-- > 0) { 564 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 565 __MEMIO_ADDR(bsh + ofs); 566 *bsp = val; 567 ofs += 2; 568 } |
828} 829 830static __inline void | 569} 570 571static __inline void |
831bus_space_set_region_4(bus_space_tag_t tag, bus_space_handle_t bsh, 832 bus_size_t offset, u_int32_t value, size_t count) | 572bus_space_set_region_4(bus_space_tag_t bst, bus_space_handle_t bsh, 573 bus_size_t ofs, uint32_t val, size_t count) |
833{ | 574{ |
834 bus_addr_t addr = bsh + offset; | 575 uint32_t __volatile *bsp; 576 while (count-- > 0) { 577 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 578 __MEMIO_ADDR(bsh + ofs); 579 *bsp = val; 580 ofs += 4; 581 } 582} |
835 | 583 |
836#if defined(_MACHINE_BUS_PIO_H_) 837#if defined(_MACHINE_BUS_MEMIO_H_) 838 if (tag == IA64_BUS_SPACE_IO) 839#endif 840 for (; count != 0; count--, addr += 4) 841 outl(addr, value); 842#endif 843#if defined(_MACHINE_BUS_MEMIO_H_) 844#if defined(_MACHINE_BUS_PIO_H_) 845 else 846#endif 847 for (; count != 0; count--, addr += 4) 848 writel(addr, value); 849#endif | 584static __inline void 585bus_space_set_region_8(bus_space_tag_t bst, bus_space_handle_t bsh, 586 bus_size_t ofs, uint64_t val, size_t count) 587{ 588 uint64_t __volatile *bsp; 589 while (count-- > 0) { 590 bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) : 591 __MEMIO_ADDR(bsh + ofs); 592 *bsp = val; 593 ofs += 8; 594 } |
850} 851 | 595} 596 |
852#if 0 /* Cause a link error for bus_space_set_region_8 */ 853#define bus_space_set_region_8 !!! bus_space_set_region_8 unimplemented !!! 854#endif | |
855 856/* | 597 598/* |
857 * Copy `count' 1, 2, 4, or 8 byte values from bus space starting 858 * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2. | 599 * Copy count units of data from bus space described by the tag and the first 600 * handle and ofs pair to bus space described by the tag and the second handle 601 * and ofs pair. A unit of data can be 1 byte, 2 bytes, 4 bytes or 8 bytes. 602 * The data is read from successive bus space addresses and also written to 603 * successive bus space addresses. Both reads and writes are unordered. |
859 */ | 604 */ |
860 861static __inline void bus_space_copy_region_1(bus_space_tag_t tag, 862 bus_space_handle_t bsh1, 863 bus_size_t off1, 864 bus_space_handle_t bsh2, 865 bus_size_t off2, size_t count); 866 867static __inline void bus_space_copy_region_2(bus_space_tag_t tag, 868 bus_space_handle_t bsh1, 869 bus_size_t off1, 870 bus_space_handle_t bsh2, 871 bus_size_t off2, size_t count); 872 873static __inline void bus_space_copy_region_4(bus_space_tag_t tag, 874 bus_space_handle_t bsh1, 875 bus_size_t off1, 876 bus_space_handle_t bsh2, 877 bus_size_t off2, size_t count); 878 | |
879static __inline void | 605static __inline void |
880bus_space_copy_region_1(bus_space_tag_t tag, bus_space_handle_t bsh1, 881 bus_size_t off1, bus_space_handle_t bsh2, 882 bus_size_t off2, size_t count) | 606bus_space_copy_region_1(bus_space_tag_t bst, bus_space_handle_t bsh1, 607 bus_size_t ofs1, bus_space_handle_t bsh2, bus_size_t ofs2, size_t count) |
883{ | 608{ |
884 bus_addr_t addr1 = bsh1 + off1; 885 bus_addr_t addr2 = bsh2 + off2; 886 887#if defined(_MACHINE_BUS_PIO_H_) 888#if defined(_MACHINE_BUS_MEMIO_H_) 889 if (tag == IA64_BUS_SPACE_IO) 890#endif 891 { 892 if (addr1 >= addr2) { 893 /* src after dest: copy forward */ 894 for (; count != 0; count--, addr1++, addr2++) 895 outb(addr2, inb(addr1)); 896 } else { 897 /* dest after src: copy backwards */ 898 for (addr1 += (count - 1), addr2 += (count - 1); 899 count != 0; count--, addr1--, addr2--) 900 outb(addr2, inb(addr1)); | 609 bus_addr_t dst, src; 610 uint8_t __volatile *dstp, *srcp; 611 src = bsh1 + ofs1; 612 dst = bsh2 + ofs2; 613 if (dst > src) { 614 src += count - 1; 615 dst += count - 1; 616 while (count-- > 0) { 617 if (bst == IA64_BUS_SPACE_IO) { 618 srcp = __PIO_ADDR(src); 619 dstp = __PIO_ADDR(dst); 620 } else { 621 srcp = __MEMIO_ADDR(src); 622 dstp = __MEMIO_ADDR(dst); 623 } 624 *dstp = *srcp; 625 src -= 1; 626 dst -= 1; |
901 } | 627 } |
902 } 903#endif 904#if defined(_MACHINE_BUS_MEMIO_H_) 905#if defined(_MACHINE_BUS_PIO_H_) 906 else 907#endif 908 { 909 if (addr1 >= addr2) { 910 /* src after dest: copy forward */ 911 for (; count != 0; count--, addr1++, addr2++) 912 writeb(addr2, readb(addr1)); 913 } else { 914 /* dest after src: copy backwards */ 915 for (addr1 += (count - 1), addr2 += (count - 1); 916 count != 0; count--, addr1--, addr2--) 917 writeb(addr2, readb(addr1)); | 628 } else { 629 while (count-- > 0) { 630 if (bst == IA64_BUS_SPACE_IO) { 631 srcp = __PIO_ADDR(src); 632 dstp = __PIO_ADDR(dst); 633 } else { 634 srcp = __MEMIO_ADDR(src); 635 dstp = __MEMIO_ADDR(dst); 636 } 637 *dstp = *srcp; 638 src += 1; 639 dst += 1; |
918 } 919 } | 640 } 641 } |
920#endif | |
921} 922 923static __inline void | 642} 643 644static __inline void |
924bus_space_copy_region_2(bus_space_tag_t tag, bus_space_handle_t bsh1, 925 bus_size_t off1, bus_space_handle_t bsh2, 926 bus_size_t off2, size_t count) | 645bus_space_copy_region_2(bus_space_tag_t bst, bus_space_handle_t bsh1, 646 bus_size_t ofs1, bus_space_handle_t bsh2, bus_size_t ofs2, size_t count) |
927{ | 647{ |
928 bus_addr_t addr1 = bsh1 + off1; 929 bus_addr_t addr2 = bsh2 + off2; 930 931#if defined(_MACHINE_BUS_PIO_H_) 932#if defined(_MACHINE_BUS_MEMIO_H_) 933 if (tag == IA64_BUS_SPACE_IO) 934#endif 935 { 936 if (addr1 >= addr2) { 937 /* src after dest: copy forward */ 938 for (; count != 0; count--, addr1 += 2, addr2 += 2) 939 outw(addr2, inw(addr1)); 940 } else { 941 /* dest after src: copy backwards */ 942 for (addr1 += 2 * (count - 1), addr2 += 2 * (count - 1); 943 count != 0; count--, addr1 -= 2, addr2 -= 2) 944 outw(addr2, inw(addr1)); | 648 bus_addr_t dst, src; 649 uint16_t __volatile *dstp, *srcp; 650 src = bsh1 + ofs1; 651 dst = bsh2 + ofs2; 652 if (dst > src) { 653 src += (count - 1) << 1; 654 dst += (count - 1) << 1; 655 while (count-- > 0) { 656 if (bst == IA64_BUS_SPACE_IO) { 657 srcp = __PIO_ADDR(src); 658 dstp = __PIO_ADDR(dst); 659 } else { 660 srcp = __MEMIO_ADDR(src); 661 dstp = __MEMIO_ADDR(dst); 662 } 663 *dstp = *srcp; 664 src -= 2; 665 dst -= 2; |
945 } | 666 } |
946 } 947#endif 948#if defined(_MACHINE_BUS_MEMIO_H_) 949#if defined(_MACHINE_BUS_PIO_H_) 950 else 951#endif 952 { 953 if (addr1 >= addr2) { 954 /* src after dest: copy forward */ 955 for (; count != 0; count--, addr1 += 2, addr2 += 2) 956 writew(addr2, readw(addr1)); 957 } else { 958 /* dest after src: copy backwards */ 959 for (addr1 += 2 * (count - 1), addr2 += 2 * (count - 1); 960 count != 0; count--, addr1 -= 2, addr2 -= 2) 961 writew(addr2, readw(addr1)); | 667 } else { 668 while (count-- > 0) { 669 if (bst == IA64_BUS_SPACE_IO) { 670 srcp = __PIO_ADDR(src); 671 dstp = __PIO_ADDR(dst); 672 } else { 673 srcp = __MEMIO_ADDR(src); 674 dstp = __MEMIO_ADDR(dst); 675 } 676 *dstp = *srcp; 677 src += 2; 678 dst += 2; |
962 } 963 } | 679 } 680 } |
964#endif | |
965} 966 967static __inline void | 681} 682 683static __inline void |
968bus_space_copy_region_4(bus_space_tag_t tag, bus_space_handle_t bsh1, 969 bus_size_t off1, bus_space_handle_t bsh2, 970 bus_size_t off2, size_t count) | 684bus_space_copy_region_4(bus_space_tag_t bst, bus_space_handle_t bsh1, 685 bus_size_t ofs1, bus_space_handle_t bsh2, bus_size_t ofs2, size_t count) |
971{ | 686{ |
972 bus_addr_t addr1 = bsh1 + off1; 973 bus_addr_t addr2 = bsh2 + off2; 974 975#if defined(_MACHINE_BUS_PIO_H_) 976#if defined(_MACHINE_BUS_MEMIO_H_) 977 if (tag == IA64_BUS_SPACE_IO) 978#endif 979 { 980 if (addr1 >= addr2) { 981 /* src after dest: copy forward */ 982 for (; count != 0; count--, addr1 += 4, addr2 += 4) 983 outl(addr2, inl(addr1)); 984 } else { 985 /* dest after src: copy backwards */ 986 for (addr1 += 4 * (count - 1), addr2 += 4 * (count - 1); 987 count != 0; count--, addr1 -= 4, addr2 -= 4) 988 outl(addr2, inl(addr1)); | 687 bus_addr_t dst, src; 688 uint32_t __volatile *dstp, *srcp; 689 src = bsh1 + ofs1; 690 dst = bsh2 + ofs2; 691 if (dst > src) { 692 src += (count - 1) << 2; 693 dst += (count - 1) << 2; 694 while (count-- > 0) { 695 if (bst == IA64_BUS_SPACE_IO) { 696 srcp = __PIO_ADDR(src); 697 dstp = __PIO_ADDR(dst); 698 } else { 699 srcp = __MEMIO_ADDR(src); 700 dstp = __MEMIO_ADDR(dst); 701 } 702 *dstp = *srcp; 703 src -= 4; 704 dst -= 4; |
989 } | 705 } |
706 } else { 707 while (count-- > 0) { 708 if (bst == IA64_BUS_SPACE_IO) { 709 srcp = __PIO_ADDR(src); 710 dstp = __PIO_ADDR(dst); 711 } else { 712 srcp = __MEMIO_ADDR(src); 713 dstp = __MEMIO_ADDR(dst); 714 } 715 *dstp = *srcp; 716 src += 4; 717 dst += 4; 718 } |
|
990 } | 719 } |
991#endif 992#if defined(_MACHINE_BUS_MEMIO_H_) 993#if defined(_MACHINE_BUS_PIO_H_) 994 else 995#endif 996 { 997 if (addr1 >= addr2) { 998 /* src after dest: copy forward */ 999 for (; count != 0; count--, addr1 += 4, addr2 += 4) 1000 writel(addr2, readl(addr1)); 1001 } else { 1002 /* dest after src: copy backwards */ 1003 for (addr1 += 4 * (count - 1), addr2 += 4 * (count - 1); 1004 count != 0; count--, addr1 -= 4, addr2 -= 4) 1005 writel(addr2, readl(addr1)); | 720} 721 722static __inline void 723bus_space_copy_region_8(bus_space_tag_t bst, bus_space_handle_t bsh1, 724 bus_size_t ofs1, bus_space_handle_t bsh2, bus_size_t ofs2, size_t count) 725{ 726 bus_addr_t dst, src; 727 uint64_t __volatile *dstp, *srcp; 728 src = bsh1 + ofs1; 729 dst = bsh2 + ofs2; 730 if (dst > src) { 731 src += (count - 1) << 3; 732 dst += (count - 1) << 3; 733 while (count-- > 0) { 734 if (bst == IA64_BUS_SPACE_IO) { 735 srcp = __PIO_ADDR(src); 736 dstp = __PIO_ADDR(dst); 737 } else { 738 srcp = __MEMIO_ADDR(src); 739 dstp = __MEMIO_ADDR(dst); 740 } 741 *dstp = *srcp; 742 src -= 8; 743 dst -= 8; |
1006 } | 744 } |
745 } else { 746 while (count-- > 0) { 747 if (bst == IA64_BUS_SPACE_IO) { 748 srcp = __PIO_ADDR(src); 749 dstp = __PIO_ADDR(dst); 750 } else { 751 srcp = __MEMIO_ADDR(src); 752 dstp = __MEMIO_ADDR(dst); 753 } 754 *dstp = *srcp; 755 src += 8; 756 dst += 8; 757 } |
|
1007 } | 758 } |
1008#endif | |
1009} 1010 | 759} 760 |
761 |
|
1011/* 1012 * Stream accesses are the same as normal accesses on ia64; there are no 1013 * supported bus systems with an endianess different from the host one. 1014 */ | 762/* 763 * Stream accesses are the same as normal accesses on ia64; there are no 764 * supported bus systems with an endianess different from the host one. 765 */ |
1015#define bus_space_read_stream_1(t, h, o) bus_space_read_1((t), (h), (o)) 1016#define bus_space_read_stream_2(t, h, o) bus_space_read_2((t), (h), (o)) 1017#define bus_space_read_stream_4(t, h, o) bus_space_read_4((t), (h), (o)) | 766#define bus_space_read_stream_1(t, h, o) \ 767 bus_space_read_1(t, h, o) 768#define bus_space_read_stream_2(t, h, o) \ 769 bus_space_read_2(t, h, o) 770#define bus_space_read_stream_4(t, h, o) \ 771 bus_space_read_4(t, h, o) 772#define bus_space_read_stream_8(t, h, o) \ 773 bus_space_read_8(t, h, o) |
1018 | 774 |
1019#define bus_space_read_multi_stream_1(t, h, o, a, c) \ 1020 bus_space_read_multi_1((t), (h), (o), (a), (c)) 1021#define bus_space_read_multi_stream_2(t, h, o, a, c) \ 1022 bus_space_read_multi_2((t), (h), (o), (a), (c)) 1023#define bus_space_read_multi_stream_4(t, h, o, a, c) \ 1024 bus_space_read_multi_4((t), (h), (o), (a), (c)) | 775#define bus_space_read_multi_stream_1(t, h, o, a, c) \ 776 bus_space_read_multi_1(t, h, o, a, c) 777#define bus_space_read_multi_stream_2(t, h, o, a, c) \ 778 bus_space_read_multi_2(t, h, o, a, c) 779#define bus_space_read_multi_stream_4(t, h, o, a, c) \ 780 bus_space_read_multi_4(t, h, o, a, c) 781#define bus_space_read_multi_stream_8(t, h, o, a, c) \ 782 bus_space_read_multi_8(t, h, o, a, c) |
1025 | 783 |
1026#define bus_space_write_stream_1(t, h, o, v) \ 1027 bus_space_write_1((t), (h), (o), (v)) 1028#define bus_space_write_stream_2(t, h, o, v) \ 1029 bus_space_write_2((t), (h), (o), (v)) 1030#define bus_space_write_stream_4(t, h, o, v) \ 1031 bus_space_write_4((t), (h), (o), (v)) | 784#define bus_space_write_stream_1(t, h, o, v) \ 785 bus_space_write_1(t, h, o, v) 786#define bus_space_write_stream_2(t, h, o, v) \ 787 bus_space_write_2(t, h, o, v) 788#define bus_space_write_stream_4(t, h, o, v) \ 789 bus_space_write_4(t, h, o, v) 790#define bus_space_write_stream_8(t, h, o, v) \ 791 bus_space_write_8(t, h, o, v) |
1032 | 792 |
1033#define bus_space_write_multi_stream_1(t, h, o, a, c) \ 1034 bus_space_write_multi_1((t), (h), (o), (a), (c)) 1035#define bus_space_write_multi_stream_2(t, h, o, a, c) \ 1036 bus_space_write_multi_2((t), (h), (o), (a), (c)) 1037#define bus_space_write_multi_stream_4(t, h, o, a, c) \ 1038 bus_space_write_multi_4((t), (h), (o), (a), (c)) | 793#define bus_space_write_multi_stream_1(t, h, o, a, c) \ 794 bus_space_write_multi_1(t, h, o, a, c) 795#define bus_space_write_multi_stream_2(t, h, o, a, c) \ 796 bus_space_write_multi_2(t, h, o, a, c) 797#define bus_space_write_multi_stream_4(t, h, o, a, c) \ 798 bus_space_write_multi_4(t, h, o, a, c) 799#define bus_space_write_multi_stream_8(t, h, o, a, c) \ 800 bus_space_write_multi_8(t, h, o, a, c) |
1039 | 801 |
1040#define bus_space_set_multi_stream_1(t, h, o, v, c) \ 1041 bus_space_set_multi_1((t), (h), (o), (v), (c)) 1042#define bus_space_set_multi_stream_2(t, h, o, v, c) \ 1043 bus_space_set_multi_2((t), (h), (o), (v), (c)) 1044#define bus_space_set_multi_stream_4(t, h, o, v, c) \ 1045 bus_space_set_multi_4((t), (h), (o), (v), (c)) | 802#define bus_space_set_multi_stream_1(t, h, o, v, c) \ 803 bus_space_set_multi_1(t, h, o, v, c) 804#define bus_space_set_multi_stream_2(t, h, o, v, c) \ 805 bus_space_set_multi_2(t, h, o, v, c) 806#define bus_space_set_multi_stream_4(t, h, o, v, c) \ 807 bus_space_set_multi_4(t, h, o, v, c) 808#define bus_space_set_multi_stream_8(t, h, o, v, c) \ 809 bus_space_set_multi_8(t, h, o, v, c) |
1046 | 810 |
1047#define bus_space_read_region_stream_1(t, h, o, a, c) \ 1048 bus_space_read_region_1((t), (h), (o), (a), (c)) 1049#define bus_space_read_region_stream_2(t, h, o, a, c) \ 1050 bus_space_read_region_2((t), (h), (o), (a), (c)) 1051#define bus_space_read_region_stream_4(t, h, o, a, c) \ 1052 bus_space_read_region_4((t), (h), (o), (a), (c)) | 811#define bus_space_read_region_stream_1(t, h, o, a, c) \ 812 bus_space_read_region_1(t, h, o, a, c) 813#define bus_space_read_region_stream_2(t, h, o, a, c) \ 814 bus_space_read_region_2(t, h, o, a, c) 815#define bus_space_read_region_stream_4(t, h, o, a, c) \ 816 bus_space_read_region_4(t, h, o, a, c) 817#define bus_space_read_region_stream_8(t, h, o, a, c) \ 818 bus_space_read_region_8(t, h, o, a, c) |
1053 | 819 |
1054#define bus_space_write_region_stream_1(t, h, o, a, c) \ 1055 bus_space_write_region_1((t), (h), (o), (a), (c)) 1056#define bus_space_write_region_stream_2(t, h, o, a, c) \ 1057 bus_space_write_region_2((t), (h), (o), (a), (c)) 1058#define bus_space_write_region_stream_4(t, h, o, a, c) \ 1059 bus_space_write_region_4((t), (h), (o), (a), (c)) | 820#define bus_space_write_region_stream_1(t, h, o, a, c) \ 821 bus_space_write_region_1(t, h, o, a, c) 822#define bus_space_write_region_stream_2(t, h, o, a, c) \ 823 bus_space_write_region_2(t, h, o, a, c) 824#define bus_space_write_region_stream_4(t, h, o, a, c) \ 825 bus_space_write_region_4(t, h, o, a, c) 826#define bus_space_write_region_stream_8(t, h, o, a, c) \ 827 bus_space_write_region_8(t, h, o, a, c) |
1060 | 828 |
1061#define bus_space_set_region_stream_1(t, h, o, v, c) \ 1062 bus_space_set_region_1((t), (h), (o), (v), (c)) 1063#define bus_space_set_region_stream_2(t, h, o, v, c) \ 1064 bus_space_set_region_2((t), (h), (o), (v), (c)) 1065#define bus_space_set_region_stream_4(t, h, o, v, c) \ 1066 bus_space_set_region_4((t), (h), (o), (v), (c)) | 829#define bus_space_set_region_stream_1(t, h, o, v, c) \ 830 bus_space_set_region_1(t, h, o, v, c) 831#define bus_space_set_region_stream_2(t, h, o, v, c) \ 832 bus_space_set_region_2(t, h, o, v, c) 833#define bus_space_set_region_stream_4(t, h, o, v, c) \ 834 bus_space_set_region_4(t, h, o, v, c) 835#define bus_space_set_region_stream_8(t, h, o, v, c) \ 836 bus_space_set_region_8(t, h, o, v, c) |
1067 | 837 |
1068#define bus_space_copy_region_stream_1(t, h1, o1, h2, o2, c) \ 1069 bus_space_copy_region_1((t), (h1), (o1), (h2), (o2), (c)) 1070#define bus_space_copy_region_stream_2(t, h1, o1, h2, o2, c) \ 1071 bus_space_copy_region_2((t), (h1), (o1), (h2), (o2), (c)) 1072#define bus_space_copy_region_stream_4(t, h1, o1, h2, o2, c) \ 1073 bus_space_copy_region_4((t), (h1), (o1), (h2), (o2), (c)) | 838#define bus_space_copy_region_stream_1(t, h1, o1, h2, o2, c) \ 839 bus_space_copy_region_1(t, h1, o1, h2, o2, c) 840#define bus_space_copy_region_stream_2(t, h1, o1, h2, o2, c) \ 841 bus_space_copy_region_2(t, h1, o1, h2, o2, c) 842#define bus_space_copy_region_stream_4(t, h1, o1, h2, o2, c) \ 843 bus_space_copy_region_4(t, h1, o1, h2, o2, c) 844#define bus_space_copy_region_stream_8(t, h1, o1, h2, o2, c) \ 845 bus_space_copy_region_8(t, h1, o1, h2, o2, c) |
1074 | 846 |
1075#endif /* defined(_MACHINE_BUS_PIO_H_) || defined(_MACHINE_BUS_MEMIO_H_) */ | |
1076 | 847 |
1077#if 0 /* Cause a link error for bus_space_copy_8 */ 1078#define bus_space_copy_region_8 !!! bus_space_copy_region_8 unimplemented !!! 1079#endif 1080 | |
1081/* | 848/* |
1082 * Bus read/write barrier methods. 1083 * 1084 * void bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t bsh, 1085 * bus_size_t offset, bus_size_t len, int flags); 1086 * 1087 */ 1088#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */ 1089#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */ 1090 1091static __inline void 1092bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t bsh, 1093 bus_size_t offset, bus_size_t len, int flags) 1094{ 1095 ia64_mf(); 1096} 1097 1098/* | |
1099 * Flags used in various bus DMA methods. 1100 */ 1101#define BUS_DMA_WAITOK 0x00 /* safe to sleep (pseudo-flag) */ 1102#define BUS_DMA_NOWAIT 0x01 /* not safe to sleep */ 1103#define BUS_DMA_ALLOCNOW 0x02 /* perform resource allocation now */ 1104#define BUS_DMAMEM_NOSYNC 0x04 /* map memory to not require sync */ 1105#define BUS_DMA_ISA 0x10 /* map memory for ISA dma */ 1106#define BUS_DMA_BUS2 0x20 /* placeholders for bus functions... */ --- 15 unchanged lines hidden (view full) --- 1122/* 1123 * bus_dma_tag_t 1124 * 1125 * A machine-dependent opaque type describing the characteristics 1126 * of how to perform DMA mappings. This structure encapsultes 1127 * information concerning address and alignment restrictions, number 1128 * of S/G segments, amount of data per S/G segment, etc. 1129 */ | 849 * Flags used in various bus DMA methods. 850 */ 851#define BUS_DMA_WAITOK 0x00 /* safe to sleep (pseudo-flag) */ 852#define BUS_DMA_NOWAIT 0x01 /* not safe to sleep */ 853#define BUS_DMA_ALLOCNOW 0x02 /* perform resource allocation now */ 854#define BUS_DMAMEM_NOSYNC 0x04 /* map memory to not require sync */ 855#define BUS_DMA_ISA 0x10 /* map memory for ISA dma */ 856#define BUS_DMA_BUS2 0x20 /* placeholders for bus functions... */ --- 15 unchanged lines hidden (view full) --- 872/* 873 * bus_dma_tag_t 874 * 875 * A machine-dependent opaque type describing the characteristics 876 * of how to perform DMA mappings. This structure encapsultes 877 * information concerning address and alignment restrictions, number 878 * of S/G segments, amount of data per S/G segment, etc. 879 */ |
1130typedef struct bus_dma_tag *bus_dma_tag_t; | 880typedef struct bus_dma_tag *bus_dma_tag_t; |
1131 1132/* 1133 * bus_dmamap_t 1134 * 1135 * DMA mapping instance information. 1136 */ | 881 882/* 883 * bus_dmamap_t 884 * 885 * DMA mapping instance information. 886 */ |
1137typedef struct bus_dmamap *bus_dmamap_t; | 887typedef struct bus_dmamap *bus_dmamap_t; |
1138 1139/* 1140 * bus_dma_segment_t 1141 * 1142 * Describes a single contiguous DMA transaction. Values 1143 * are suitable for programming into DMA registers. 1144 */ 1145typedef struct bus_dma_segment { --- 9 unchanged lines hidden (view full) --- 1155 1156/* 1157 * Allocate a device specific dma_tag encapsulating the constraints of 1158 * the parent tag in addition to other restrictions specified: 1159 * 1160 * alignment: alignment for segments. 1161 * boundary: Boundary that segments cannot cross. 1162 * lowaddr: Low restricted address that cannot appear in a mapping. | 888 889/* 890 * bus_dma_segment_t 891 * 892 * Describes a single contiguous DMA transaction. Values 893 * are suitable for programming into DMA registers. 894 */ 895typedef struct bus_dma_segment { --- 9 unchanged lines hidden (view full) --- 905 906/* 907 * Allocate a device specific dma_tag encapsulating the constraints of 908 * the parent tag in addition to other restrictions specified: 909 * 910 * alignment: alignment for segments. 911 * boundary: Boundary that segments cannot cross. 912 * lowaddr: Low restricted address that cannot appear in a mapping. |
1163 * highaddr: High restricted address that cannot appear in a mapping. | 913 * highaddr: High restricted addr. that cannot appear in a mapping. |
1164 * filtfunc: An optional function to further test if an address 1165 * within the range of lowaddr and highaddr cannot appear 1166 * in a mapping. 1167 * filtfuncarg: An argument that will be passed to filtfunc in addition 1168 * to the address to test. 1169 * maxsize: Maximum mapping size supported by this tag. 1170 * nsegments: Number of discontinuities allowed in maps. 1171 * maxsegsz: Maximum size of a segment in the map. 1172 * flags: Bus DMA flags. 1173 * dmat: A pointer to set to a valid dma tag should the return 1174 * value of this function indicate success. 1175 */ 1176/* XXX Should probably allow specification of alignment */ 1177int bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignemnt, | 914 * filtfunc: An optional function to further test if an address 915 * within the range of lowaddr and highaddr cannot appear 916 * in a mapping. 917 * filtfuncarg: An argument that will be passed to filtfunc in addition 918 * to the address to test. 919 * maxsize: Maximum mapping size supported by this tag. 920 * nsegments: Number of discontinuities allowed in maps. 921 * maxsegsz: Maximum size of a segment in the map. 922 * flags: Bus DMA flags. 923 * dmat: A pointer to set to a valid dma tag should the return 924 * value of this function indicate success. 925 */ 926/* XXX Should probably allow specification of alignment */ 927int bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignemnt, |
1178 bus_size_t boundary, bus_addr_t lowaddr, 1179 bus_addr_t highaddr, bus_dma_filter_t *filtfunc, 1180 void *filtfuncarg, bus_size_t maxsize, int nsegments, 1181 bus_size_t maxsegsz, int flags, bus_dma_tag_t *dmat); | 928 bus_size_t boundary, bus_addr_t lowaddr, bus_addr_t highaddr, 929 bus_dma_filter_t *filtfunc, void *filtfuncarg, bus_size_t maxsize, 930 int nsegments, bus_size_t maxsegsz, int flags, bus_dma_tag_t *dmat); |
1182 1183int bus_dma_tag_destroy(bus_dma_tag_t dmat); 1184 1185/* 1186 * Allocate a handle for mapping from kva/uva/physical 1187 * address space into bus device space. 1188 */ 1189int bus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp); --- 5 unchanged lines hidden (view full) --- 1195int bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map); 1196 1197/* 1198 * Allocate a piece of memory that can be efficiently mapped into 1199 * bus device space based on the constraints lited in the dma tag. 1200 * A dmamap to for use with dmamap_load is also allocated. 1201 */ 1202int bus_dmamem_alloc(bus_dma_tag_t dmat, void** vaddr, int flags, | 931 932int bus_dma_tag_destroy(bus_dma_tag_t dmat); 933 934/* 935 * Allocate a handle for mapping from kva/uva/physical 936 * address space into bus device space. 937 */ 938int bus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp); --- 5 unchanged lines hidden (view full) --- 944int bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map); 945 946/* 947 * Allocate a piece of memory that can be efficiently mapped into 948 * bus device space based on the constraints lited in the dma tag. 949 * A dmamap to for use with dmamap_load is also allocated. 950 */ 951int bus_dmamem_alloc(bus_dma_tag_t dmat, void** vaddr, int flags, |
1203 bus_dmamap_t *mapp); | 952 bus_dmamap_t *mapp); |
1204 1205/* 1206 * Free a piece of memory and it's allociated dmamap, that was allocated 1207 * via bus_dmamem_alloc. 1208 */ 1209void bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map); 1210 1211/* 1212 * A function that processes a successfully loaded dma map or an error 1213 * from a delayed load map. 1214 */ 1215typedef void bus_dmamap_callback_t(void *, bus_dma_segment_t *, int, int); 1216 1217/* 1218 * Map the buffer buf into bus space using the dmamap map. 1219 */ 1220int bus_dmamap_load(bus_dma_tag_t dmat, bus_dmamap_t map, void *buf, | 953 954/* 955 * Free a piece of memory and it's allociated dmamap, that was allocated 956 * via bus_dmamem_alloc. 957 */ 958void bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map); 959 960/* 961 * A function that processes a successfully loaded dma map or an error 962 * from a delayed load map. 963 */ 964typedef void bus_dmamap_callback_t(void *, bus_dma_segment_t *, int, int); 965 966/* 967 * Map the buffer buf into bus space using the dmamap map. 968 */ 969int bus_dmamap_load(bus_dma_tag_t dmat, bus_dmamap_t map, void *buf, |
1221 bus_size_t buflen, bus_dmamap_callback_t *callback, 1222 void *callback_arg, int flags); | 970 bus_size_t buflen, bus_dmamap_callback_t *callback, void *callback_arg, 971 int flags); |
1223 1224/* 1225 * Like bus_dmamap_callback but includes map size in bytes. This is 1226 * defined as a separate interface to maintain compatiiblity for users 1227 * of bus_dmamap_callback_t--at some point these interfaces should be merged. 1228 */ | 972 973/* 974 * Like bus_dmamap_callback but includes map size in bytes. This is 975 * defined as a separate interface to maintain compatiiblity for users 976 * of bus_dmamap_callback_t--at some point these interfaces should be merged. 977 */ |
1229typedef void bus_dmamap_callback2_t(void *, bus_dma_segment_t *, int, bus_size_t, int); | 978typedef void bus_dmamap_callback2_t(void *, bus_dma_segment_t *, int, 979 bus_size_t, int); 980 |
1230/* 1231 * Like bus_dmamap_load but for mbufs. Note the use of the 1232 * bus_dmamap_callback2_t interface. 1233 */ 1234int bus_dmamap_load_mbuf(bus_dma_tag_t dmat, bus_dmamap_t map, | 981/* 982 * Like bus_dmamap_load but for mbufs. Note the use of the 983 * bus_dmamap_callback2_t interface. 984 */ 985int bus_dmamap_load_mbuf(bus_dma_tag_t dmat, bus_dmamap_t map, |
1235 struct mbuf *mbuf, 1236 bus_dmamap_callback2_t *callback, void *callback_arg, 1237 int flags); | 986 struct mbuf *mbuf, bus_dmamap_callback2_t *callback, void *callback_arg, 987 int flags); 988 |
1238/* 1239 * Like bus_dmamap_load but for uios. Note the use of the 1240 * bus_dmamap_callback2_t interface. 1241 */ | 989/* 990 * Like bus_dmamap_load but for uios. Note the use of the 991 * bus_dmamap_callback2_t interface. 992 */ |
1242int bus_dmamap_load_uio(bus_dma_tag_t dmat, bus_dmamap_t map, 1243 struct uio *ui, 1244 bus_dmamap_callback2_t *callback, void *callback_arg, 1245 int flags); | 993int bus_dmamap_load_uio(bus_dma_tag_t dmat, bus_dmamap_t map, struct uio *ui, 994 bus_dmamap_callback2_t *callback, void *callback_arg, int flags); |
1246 1247/* 1248 * Perform a syncronization operation on the given map. 1249 */ 1250void _bus_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, int); | 995 996/* 997 * Perform a syncronization operation on the given map. 998 */ 999void _bus_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, int); |
1251#define bus_dmamap_sync(dmat, dmamap, op) \ 1252 if ((dmamap) != NULL) \ 1253 _bus_dmamap_sync(dmat, dmamap, op) | 1000static __inline void 1001bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t dmamap, int op) 1002{ 1003 if ((dmamap) != NULL) 1004 _bus_dmamap_sync(dmat, dmamap, op); 1005} |
1254 1255/* 1256 * Release the mapping held by map. 1257 */ 1258void _bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map); | 1006 1007/* 1008 * Release the mapping held by map. 1009 */ 1010void _bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map); |
1259#define bus_dmamap_unload(dmat, dmamap) \ 1260 if ((dmamap) != NULL) \ 1261 _bus_dmamap_unload(dmat, dmamap) | 1011static __inline void 1012bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t dmamap) 1013{ 1014 if ((dmamap) != NULL) 1015 _bus_dmamap_unload(dmat, dmamap); 1016} |
1262 1263#endif /* _MACHINE_BUS_H_ */ | 1017 1018#endif /* _MACHINE_BUS_H_ */ |