| pmc_mdep.h (145337) | pmc_mdep.h (145615) |
|---|---|
| 1/*- 2 * Copyright (c) 2003, Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 2003, Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/i386/include/pmc_mdep.h 145337 2005-04-20 20:22:33Z marcel $ | 26 * $FreeBSD: head/sys/i386/include/pmc_mdep.h 145615 2005-04-28 08:13:19Z jkoshy $ |
| 27 */ 28 29/* Machine dependent interfaces */ 30 31#ifndef _MACHINE_PMC_MDEP_H 32#define _MACHINE_PMC_MDEP_H 1 33 34#include <machine/cpufunc.h> --- 83 unchanged lines hidden (view full) --- 118#define P4_ESCR_USR P4_ESCR_T0_USR 119#define P4_ESCR_VALID_BITS (P4_ESCR_EVENT_SELECT_MASK | \ 120 P4_ESCR_EVENT_MASK_MASK | P4_ESCR_TAG_VALUE_MASK | \ 121 P4_ESCR_TAG_ENABLE | P4_ESCR_T0_OS | P4_ESCR_T0_USR | P4_ESCR_T1_OS \ 122 P4_ESCR_T1_USR) 123 124#define P4_PERFCTR_MASK 0xFFFFFFFFFFLL /* 40 bits */ 125 | 27 */ 28 29/* Machine dependent interfaces */ 30 31#ifndef _MACHINE_PMC_MDEP_H 32#define _MACHINE_PMC_MDEP_H 1 33 34#include <machine/cpufunc.h> --- 83 unchanged lines hidden (view full) --- 118#define P4_ESCR_USR P4_ESCR_T0_USR 119#define P4_ESCR_VALID_BITS (P4_ESCR_EVENT_SELECT_MASK | \ 120 P4_ESCR_EVENT_MASK_MASK | P4_ESCR_TAG_VALUE_MASK | \ 121 P4_ESCR_TAG_ENABLE | P4_ESCR_T0_OS | P4_ESCR_T0_USR | P4_ESCR_T1_OS \ 122 P4_ESCR_T1_USR) 123 124#define P4_PERFCTR_MASK 0xFFFFFFFFFFLL /* 40 bits */ 125 |
| 126#define P4_CCCR_MSR_FIRST 0x360 /* MSR_BPU_CCCR0 */ 127#define P4_PERFCTR_MSR_FIRST 0x300 /* MSR_BPU_COUNTER0 */ 128 |
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| 126/* Intel PPro, Celeron, P-II, P-III, Pentium-M PMCS */ 127 128#define P6_NPMCS 3 /* 1 TSC + 2 PMCs */ 129 130#define P6_EVSEL_CMASK_MASK 0xFF000000 131#define P6_EVSEL_TO_CMASK(C) (((C) & 0xFF) << 24) 132#define P6_EVSEL_INV (1 << 23) 133#define P6_EVSEL_EN (1 << 22) --- 52 unchanged lines hidden --- | 129/* Intel PPro, Celeron, P-II, P-III, Pentium-M PMCS */ 130 131#define P6_NPMCS 3 /* 1 TSC + 2 PMCs */ 132 133#define P6_EVSEL_CMASK_MASK 0xFF000000 134#define P6_EVSEL_TO_CMASK(C) (((C) & 0xFF) << 24) 135#define P6_EVSEL_INV (1 << 23) 136#define P6_EVSEL_EN (1 << 22) --- 52 unchanged lines hidden --- |