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cpufunc.h (97139) cpufunc.h (99862)
1/*-
2 * Copyright (c) 1993 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
1/*-
2 * Copyright (c) 1993 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * $FreeBSD: head/sys/i386/include/cpufunc.h 97139 2002-05-22 20:32:39Z jhb $
33 * $FreeBSD: head/sys/i386/include/cpufunc.h 99862 2002-07-12 07:56:11Z peter $
34 */
35
36/*
37 * Functions to provide access to special i386 instructions.
38 * This in included in sys/systm.h, and that file should be
39 * used in preference to this.
40 */
41

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232}
233
234static __inline void
235invd(void)
236{
237 __asm __volatile("invd");
238}
239
34 */
35
36/*
37 * Functions to provide access to special i386 instructions.
38 * This in included in sys/systm.h, and that file should be
39 * used in preference to this.
40 */
41

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232}
233
234static __inline void
235invd(void)
236{
237 __asm __volatile("invd");
238}
239
240#if defined(SMP) && defined(_KERNEL)
241
242/*
243 * When using APIC IPI's, invlpg() is not simply the invlpg instruction
244 * (this is a bug) and the inlining cost is prohibitive since the call
245 * executes into the IPI transmission system.
246 */
247void invlpg(u_int addr);
248void invltlb(void);
249
250static __inline void
251cpu_invlpg(void *addr)
252{
253 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
254}
255
256static __inline void
257cpu_invltlb(void)
258{
259 u_int temp;
260 /*
261 * This should be implemented as load_cr3(rcr3()) when load_cr3()
262 * is inlined.
263 */
264 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3" : "=r" (temp)
265 : : "memory");
266#if defined(SWTCH_OPTIM_STATS)
267 ++tlb_flush_count;
268#endif
269}
270
271#else /* !(SMP && _KERNEL) */
272
273static __inline void
274invlpg(u_int addr)
275{
276 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
277}
278
279static __inline void
280invltlb(void)
281{
282 u_int temp;
283 /*
284 * This should be implemented as load_cr3(rcr3()) when load_cr3()
285 * is inlined.
286 */
287 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3" : "=r" (temp)
288 : : "memory");
289#ifdef SWTCH_OPTIM_STATS
290 ++tlb_flush_count;
291#endif
292}
293
294#endif /* SMP && _KERNEL */
295
296static __inline u_short
297inw(u_int port)
298{
299 u_short data;
300
301 __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
302 return (data);
303}

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359
360static __inline void
361ia32_pause(void)
362{
363 __asm __volatile("pause");
364}
365
366static __inline u_int
240static __inline u_short
241inw(u_int port)
242{
243 u_short data;
244
245 __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
246 return (data);
247}

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303
304static __inline void
305ia32_pause(void)
306{
307 __asm __volatile("pause");
308}
309
310static __inline u_int
367rcr2(void)
368{
369 u_int data;
370
371 __asm __volatile("movl %%cr2,%0" : "=r" (data));
372 return (data);
373}
374
375static __inline u_int
376read_eflags(void)
377{
378 u_int ef;
379
380 __asm __volatile("pushfl; popl %0" : "=r" (ef));
381 return (ef);
382}
383

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421}
422
423static __inline void
424wrmsr(u_int msr, u_int64_t newval)
425{
426 __asm __volatile("wrmsr" : : "A" (newval), "c" (msr));
427}
428
311read_eflags(void)
312{
313 u_int ef;
314
315 __asm __volatile("pushfl; popl %0" : "=r" (ef));
316 return (ef);
317}
318

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356}
357
358static __inline void
359wrmsr(u_int msr, u_int64_t newval)
360{
361 __asm __volatile("wrmsr" : : "A" (newval), "c" (msr));
362}
363
364static __inline void
365load_cr0(u_int data)
366{
367
368 __asm __volatile("movl %0,%%cr0" : : "r" (data));
369}
370
429static __inline u_int
371static __inline u_int
372rcr0(void)
373{
374 u_int data;
375
376 __asm __volatile("movl %%cr0,%0" : "=r" (data));
377 return (data);
378}
379
380static __inline u_int
381rcr2(void)
382{
383 u_int data;
384
385 __asm __volatile("movl %%cr2,%0" : "=r" (data));
386 return (data);
387}
388
389static __inline void
390load_cr3(u_int data)
391{
392
393 __asm __volatile("movl %0,%%cr3" : : "r" (data) : "memory");
394#if defined(SWTCH_OPTIM_STATS)
395 ++tlb_flush_count;
396#endif
397}
398
399static __inline u_int
400rcr3(void)
401{
402 u_int data;
403
404 __asm __volatile("movl %%cr3,%0" : "=r" (data));
405 return (data);
406}
407
408static __inline void
409load_cr4(u_int data)
410{
411 __asm __volatile("movl %0,%%cr4" : : "r" (data));
412}
413
414static __inline u_int
415rcr4(void)
416{
417 u_int data;
418
419 __asm __volatile("movl %%cr4,%0" : "=r" (data));
420 return (data);
421}
422
423/*
424 * Global TLB flush (except for thise for pages marked PG_G)
425 */
426static __inline void
427invltlb(void)
428{
429
430 load_cr3(rcr3());
431}
432
433/*
434 * TLB flush for an individual page (even if it has PG_G).
435 * Only works on 486+ CPUs (i386 does not have PG_G).
436 */
437static __inline void
438invlpg(u_int addr)
439{
440
441 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
442}
443
444static __inline u_int
430rfs(void)
431{
432 u_int sel;
433 __asm __volatile("movl %%fs,%0" : "=rm" (sel));
434 return (sel);
435}
436
437static __inline u_int

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582 write_eflags(eflags);
583}
584
585#else /* !__GNUC__ */
586
587int breakpoint(void);
588u_int bsfl(u_int mask);
589u_int bsrl(u_int mask);
445rfs(void)
446{
447 u_int sel;
448 __asm __volatile("movl %%fs,%0" : "=rm" (sel));
449 return (sel);
450}
451
452static __inline u_int

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597 write_eflags(eflags);
598}
599
600#else /* !__GNUC__ */
601
602int breakpoint(void);
603u_int bsfl(u_int mask);
604u_int bsrl(u_int mask);
605void cpu_invlpg(u_int addr);
606void cpu_invlpg_range(u_int start, u_int end);
590void disable_intr(void);
591void do_cpuid(u_int ax, u_int *p);
592void enable_intr(void);
593u_char inb(u_int port);
594u_int inl(u_int port);
595void insb(u_int port, void *addr, size_t cnt);
596void insl(u_int port, void *addr, size_t cnt);
597void insw(u_int port, void *addr, size_t cnt);
598void invd(void);
599void invlpg(u_int addr);
607void disable_intr(void);
608void do_cpuid(u_int ax, u_int *p);
609void enable_intr(void);
610u_char inb(u_int port);
611u_int inl(u_int port);
612void insb(u_int port, void *addr, size_t cnt);
613void insl(u_int port, void *addr, size_t cnt);
614void insw(u_int port, void *addr, size_t cnt);
615void invd(void);
616void invlpg(u_int addr);
617void invlpg_range(u_int start, u_int end);
600void invltlb(void);
601u_short inw(u_int port);
618void invltlb(void);
619u_short inw(u_int port);
620void load_cr0(u_int cr0);
621void load_cr3(u_int cr3);
622void load_cr4(u_int cr4);
623void load_fs(u_int sel);
624void load_gs(u_int sel);
602void outb(u_int port, u_char data);
603void outl(u_int port, u_int data);
604void outsb(u_int port, void *addr, size_t cnt);
605void outsl(u_int port, void *addr, size_t cnt);
606void outsw(u_int port, void *addr, size_t cnt);
607void outw(u_int port, u_short data);
608void ia32_pause(void);
625void outb(u_int port, u_char data);
626void outl(u_int port, u_int data);
627void outsb(u_int port, void *addr, size_t cnt);
628void outsl(u_int port, void *addr, size_t cnt);
629void outsw(u_int port, void *addr, size_t cnt);
630void outw(u_int port, u_short data);
631void ia32_pause(void);
632u_int rcr0(void);
609u_int rcr2(void);
633u_int rcr2(void);
634u_int rcr3(void);
635u_int rcr4(void);
636u_int rfs(void);
637u_int rgs(void);
610u_int64_t rdmsr(u_int msr);
611u_int64_t rdpmc(u_int pmc);
612u_int64_t rdtsc(void);
613u_int read_eflags(void);
614void wbinvd(void);
615void write_eflags(u_int ef);
616void wrmsr(u_int msr, u_int64_t newval);
638u_int64_t rdmsr(u_int msr);
639u_int64_t rdpmc(u_int pmc);
640u_int64_t rdtsc(void);
641u_int read_eflags(void);
642void wbinvd(void);
643void write_eflags(u_int ef);
644void wrmsr(u_int msr, u_int64_t newval);
617u_int rfs(void);
618u_int rgs(void);
619void load_fs(u_int sel);
620void load_gs(u_int sel);
621u_int rdr0(void);
622void load_dr0(u_int dr0);
623u_int rdr1(void);
624void load_dr1(u_int dr1);
625u_int rdr2(void);
626void load_dr2(u_int dr2);
627u_int rdr3(void);
628void load_dr3(u_int dr3);

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634void load_dr6(u_int dr6);
635u_int rdr7(void);
636void load_dr7(u_int dr7);
637register_t intr_disable(void);
638void intr_restore(register_t ef);
639
640#endif /* __GNUC__ */
641
645u_int rdr0(void);
646void load_dr0(u_int dr0);
647u_int rdr1(void);
648void load_dr1(u_int dr1);
649u_int rdr2(void);
650void load_dr2(u_int dr2);
651u_int rdr3(void);
652void load_dr3(u_int dr3);

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658void load_dr6(u_int dr6);
659u_int rdr7(void);
660void load_dr7(u_int dr7);
661register_t intr_disable(void);
662void intr_restore(register_t ef);
663
664#endif /* __GNUC__ */
665
642void load_cr0(u_int cr0);
643void load_cr3(u_int cr3);
644void load_cr4(u_int cr4);
645void ltr(u_short sel);
666void ltr(u_short sel);
646u_int rcr0(void);
647u_int rcr3(void);
648u_int rcr4(void);
649void reset_dbregs(void);
650
651__END_DECLS
652
653#endif /* !_MACHINE_CPUFUNC_H_ */
667void reset_dbregs(void);
668
669__END_DECLS
670
671#endif /* !_MACHINE_CPUFUNC_H_ */