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machdep.c (211924) machdep.c (212541)
1/*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz.
8 *

--- 24 unchanged lines hidden (view full) ---

33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
38 */
39
40#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz.
8 *

--- 24 unchanged lines hidden (view full) ---

33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
38 */
39
40#include <sys/cdefs.h>
41__FBSDID("$FreeBSD: head/sys/i386/i386/machdep.c 211924 2010-08-28 08:03:29Z rpaulo $");
41__FBSDID("$FreeBSD: head/sys/i386/i386/machdep.c 212541 2010-09-13 07:25:35Z mav $");
42
43#include "opt_apic.h"
44#include "opt_atalk.h"
45#include "opt_compat.h"
46#include "opt_cpu.h"
47#include "opt_ddb.h"
48#include "opt_inet.h"
49#include "opt_ipx.h"

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1170 * subtract 0.5% of the total. Empirical testing has shown that
1171 * overhead in DELAY() works out to approximately this value.
1172 */
1173 tsc2 -= tsc1;
1174 *rate = tsc2 * 1000 - tsc2 * 5;
1175 return (0);
1176}
1177
42
43#include "opt_apic.h"
44#include "opt_atalk.h"
45#include "opt_compat.h"
46#include "opt_cpu.h"
47#include "opt_ddb.h"
48#include "opt_inet.h"
49#include "opt_ipx.h"

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1170 * subtract 0.5% of the total. Empirical testing has shown that
1171 * overhead in DELAY() works out to approximately this value.
1172 */
1173 tsc2 -= tsc1;
1174 *rate = tsc2 * 1000 - tsc2 * 5;
1175 return (0);
1176}
1177
1178
1179void (*cpu_idle_hook)(void) = NULL; /* ACPI idle hook. */
1180
1181#ifdef XEN
1182
1183void
1184cpu_halt(void)
1185{
1186 HYPERVISOR_shutdown(SHUTDOWN_poweroff);
1187}
1188

--- 14 unchanged lines hidden (view full) ---

1203 */
1204void
1205cpu_halt(void)
1206{
1207 for (;;)
1208 __asm__ ("hlt");
1209}
1210
1178#ifdef XEN
1179
1180void
1181cpu_halt(void)
1182{
1183 HYPERVISOR_shutdown(SHUTDOWN_poweroff);
1184}
1185

--- 14 unchanged lines hidden (view full) ---

1200 */
1201void
1202cpu_halt(void)
1203{
1204 for (;;)
1205 __asm__ ("hlt");
1206}
1207
1208#endif
1209
1210void (*cpu_idle_hook)(void) = NULL; /* ACPI idle hook. */
1211static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */
1212static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */
1213TUNABLE_INT("machdep.idle_mwait", &idle_mwait);
1214SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RW, &idle_mwait,
1215 0, "Use MONITOR/MWAIT for short idle");
1216
1217#define STATE_RUNNING 0x0
1218#define STATE_MWAIT 0x1
1219#define STATE_SLEEPING 0x2
1220
1211static void
1221static void
1212cpu_idle_hlt(int busy)
1222cpu_idle_acpi(int busy)
1213{
1223{
1214 /*
1215 * we must absolutely guarentee that hlt is the next instruction
1216 * after sti or we introduce a timing window.
1217 */
1224 int *state;
1225
1226 state = (int *)PCPU_PTR(monitorbuf);
1227 *state = STATE_SLEEPING;
1218 disable_intr();
1228 disable_intr();
1219 if (sched_runnable())
1229 if (sched_runnable())
1220 enable_intr();
1230 enable_intr();
1231 else if (cpu_idle_hook)
1232 cpu_idle_hook();
1221 else
1222 __asm __volatile("sti; hlt");
1233 else
1234 __asm __volatile("sti; hlt");
1235 *state = STATE_RUNNING;
1223}
1236}
1224#endif
1225
1237
1238#ifndef XEN
1226static void
1239static void
1227cpu_idle_acpi(int busy)
1240cpu_idle_hlt(int busy)
1228{
1241{
1242 int *state;
1243
1244 state = (int *)PCPU_PTR(monitorbuf);
1245 *state = STATE_SLEEPING;
1246 /*
1247 * We must absolutely guarentee that hlt is the next instruction
1248 * after sti or we introduce a timing window.
1249 */
1229 disable_intr();
1250 disable_intr();
1230 if (sched_runnable())
1251 if (sched_runnable())
1231 enable_intr();
1252 enable_intr();
1232 else if (cpu_idle_hook)
1233 cpu_idle_hook();
1234 else
1235 __asm __volatile("sti; hlt");
1253 else
1254 __asm __volatile("sti; hlt");
1255 *state = STATE_RUNNING;
1236}
1256}
1257#endif
1237
1258
1238static int cpu_ident_amdc1e = 0;
1259/*
1260 * MWAIT cpu power states. Lower 4 bits are sub-states.
1261 */
1262#define MWAIT_C0 0xf0
1263#define MWAIT_C1 0x00
1264#define MWAIT_C2 0x10
1265#define MWAIT_C3 0x20
1266#define MWAIT_C4 0x30
1239
1267
1240static int
1241cpu_probe_amdc1e(void)
1242{
1243#ifdef DEV_APIC
1244 int i;
1268static void
1269cpu_idle_mwait(int busy)
1270{
1271 int *state;
1245
1272
1246 /*
1247 * Forget it, if we're not using local APIC timer.
1248 */
1249 if (resource_disabled("apic", 0) ||
1250 (resource_int_value("apic", 0, "clock", &i) == 0 && i == 0))
1251 return (0);
1273 state = (int *)PCPU_PTR(monitorbuf);
1274 *state = STATE_MWAIT;
1275 if (!sched_runnable()) {
1276 cpu_monitor(state, 0, 0);
1277 if (*state == STATE_MWAIT)
1278 cpu_mwait(0, MWAIT_C1);
1279 }
1280 *state = STATE_RUNNING;
1281}
1252
1282
1253 /*
1254 * Detect the presence of C1E capability mostly on latest
1255 * dual-cores (or future) k8 family.
1256 */
1257 if (cpu_vendor_id == CPU_VENDOR_AMD &&
1258 (cpu_id & 0x00000f00) == 0x00000f00 &&
1259 (cpu_id & 0x0fff0000) >= 0x00040000) {
1260 cpu_ident_amdc1e = 1;
1261 return (1);
1283static void
1284cpu_idle_spin(int busy)
1285{
1286 int *state;
1287 int i;
1288
1289 state = (int *)PCPU_PTR(monitorbuf);
1290 *state = STATE_RUNNING;
1291 for (i = 0; i < 1000; i++) {
1292 if (sched_runnable())
1293 return;
1294 cpu_spinwait();
1262 }
1295 }
1263#endif
1264 return (0);
1265}
1266
1267/*
1268 * C1E renders the local APIC timer dead, so we disable it by
1269 * reading the Interrupt Pending Message register and clearing
1270 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
1271 *
1272 * Reference:
1273 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors"
1274 * #32559 revision 3.00+
1275 */
1276#define MSR_AMDK8_IPM 0xc0010055
1277#define AMDK8_SMIONCMPHALT (1ULL << 27)
1278#define AMDK8_C1EONCMPHALT (1ULL << 28)
1279#define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT)
1280
1281static void
1296}
1297
1298/*
1299 * C1E renders the local APIC timer dead, so we disable it by
1300 * reading the Interrupt Pending Message register and clearing
1301 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
1302 *
1303 * Reference:
1304 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors"
1305 * #32559 revision 3.00+
1306 */
1307#define MSR_AMDK8_IPM 0xc0010055
1308#define AMDK8_SMIONCMPHALT (1ULL << 27)
1309#define AMDK8_C1EONCMPHALT (1ULL << 28)
1310#define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT)
1311
1312static void
1282cpu_idle_amdc1e(int busy)
1313cpu_probe_amdc1e(void)
1283{
1284
1314{
1315
1285 disable_intr();
1286 if (sched_runnable())
1287 enable_intr();
1288 else {
1289 uint64_t msr;
1290
1291 msr = rdmsr(MSR_AMDK8_IPM);
1292 if (msr & AMDK8_CMPHALT)
1293 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT);
1294
1295 if (cpu_idle_hook)
1296 cpu_idle_hook();
1297 else
1298 __asm __volatile("sti; hlt");
1316 /*
1317 * Detect the presence of C1E capability mostly on latest
1318 * dual-cores (or future) k8 family.
1319 */
1320 if (cpu_vendor_id == CPU_VENDOR_AMD &&
1321 (cpu_id & 0x00000f00) == 0x00000f00 &&
1322 (cpu_id & 0x0fff0000) >= 0x00040000) {
1323 cpu_ident_amdc1e = 1;
1299 }
1300}
1301
1324 }
1325}
1326
1302static void
1303cpu_idle_spin(int busy)
1304{
1305 return;
1306}
1307
1308#ifdef XEN
1309void (*cpu_idle_fn)(int) = cpu_idle_hlt;
1310#else
1311void (*cpu_idle_fn)(int) = cpu_idle_acpi;
1312#endif
1313
1314void
1315cpu_idle(int busy)
1316{
1327#ifdef XEN
1328void (*cpu_idle_fn)(int) = cpu_idle_hlt;
1329#else
1330void (*cpu_idle_fn)(int) = cpu_idle_acpi;
1331#endif
1332
1333void
1334cpu_idle(int busy)
1335{
1336 uint64_t msr;
1337
1338 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
1339 busy, curcpu);
1317#if defined(SMP) && !defined(XEN)
1318 if (mp_grab_cpu_hlt())
1319 return;
1320#endif
1340#if defined(SMP) && !defined(XEN)
1341 if (mp_grab_cpu_hlt())
1342 return;
1343#endif
1321 cpu_idle_fn(busy);
1322}
1344 /* If we are busy - try to use fast methods. */
1345 if (busy) {
1346 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) {
1347 cpu_idle_mwait(busy);
1348 goto out;
1349 }
1350 }
1323
1351
1324/*
1325 * mwait cpu power states. Lower 4 bits are sub-states.
1326 */
1327#define MWAIT_C0 0xf0
1328#define MWAIT_C1 0x00
1329#define MWAIT_C2 0x10
1330#define MWAIT_C3 0x20
1331#define MWAIT_C4 0x30
1352#ifndef XEN
1353 /* If we have time - switch timers into idle mode. */
1354 if (!busy) {
1355 critical_enter();
1356 cpu_idleclock();
1357 }
1358#endif
1332
1359
1333#define MWAIT_DISABLED 0x0
1334#define MWAIT_WOKEN 0x1
1335#define MWAIT_WAITING 0x2
1360 /* Apply AMD APIC timer C1E workaround. */
1361 if (cpu_ident_amdc1e
1362#ifndef XEN
1363 && cpu_disable_deep_sleep
1364#endif
1365 ) {
1366 msr = rdmsr(MSR_AMDK8_IPM);
1367 if (msr & AMDK8_CMPHALT)
1368 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT);
1369 }
1336
1370
1337static void
1338cpu_idle_mwait(int busy)
1339{
1340 int *mwait;
1371 /* Call main idle method. */
1372 cpu_idle_fn(busy);
1341
1373
1342 mwait = (int *)PCPU_PTR(monitorbuf);
1343 *mwait = MWAIT_WAITING;
1344 if (sched_runnable())
1345 return;
1346 cpu_monitor(mwait, 0, 0);
1347 if (*mwait == MWAIT_WAITING)
1348 cpu_mwait(0, MWAIT_C1);
1349}
1350
1351static void
1352cpu_idle_mwait_hlt(int busy)
1353{
1354 int *mwait;
1355
1356 mwait = (int *)PCPU_PTR(monitorbuf);
1357 if (busy == 0) {
1358 *mwait = MWAIT_DISABLED;
1359 cpu_idle_hlt(busy);
1360 return;
1374#ifndef XEN
1375 /* Switch timers mack into active mode. */
1376 if (!busy) {
1377 cpu_activeclock();
1378 critical_exit();
1361 }
1379 }
1362 *mwait = MWAIT_WAITING;
1363 if (sched_runnable())
1364 return;
1365 cpu_monitor(mwait, 0, 0);
1366 if (*mwait == MWAIT_WAITING)
1367 cpu_mwait(0, MWAIT_C1);
1380#endif
1381out:
1382 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
1383 busy, curcpu);
1368}
1369
1370int
1371cpu_idle_wakeup(int cpu)
1372{
1373 struct pcpu *pcpu;
1384}
1385
1386int
1387cpu_idle_wakeup(int cpu)
1388{
1389 struct pcpu *pcpu;
1374 int *mwait;
1390 int *state;
1375
1391
1376 if (cpu_idle_fn == cpu_idle_spin)
1377 return (1);
1378 if (cpu_idle_fn != cpu_idle_mwait && cpu_idle_fn != cpu_idle_mwait_hlt)
1379 return (0);
1380 pcpu = pcpu_find(cpu);
1392 pcpu = pcpu_find(cpu);
1381 mwait = (int *)pcpu->pc_monitorbuf;
1393 state = (int *)pcpu->pc_monitorbuf;
1382 /*
1383 * This doesn't need to be atomic since missing the race will
1384 * simply result in unnecessary IPIs.
1385 */
1394 /*
1395 * This doesn't need to be atomic since missing the race will
1396 * simply result in unnecessary IPIs.
1397 */
1386 if (cpu_idle_fn == cpu_idle_mwait_hlt && *mwait == MWAIT_DISABLED)
1398 if (*state == STATE_SLEEPING)
1387 return (0);
1399 return (0);
1388 *mwait = MWAIT_WOKEN;
1389
1400 if (*state == STATE_MWAIT)
1401 *state = STATE_RUNNING;
1390 return (1);
1391}
1392
1393/*
1394 * Ordered by speed/power consumption.
1395 */
1396struct {
1397 void *id_fn;
1398 char *id_name;
1399} idle_tbl[] = {
1400 { cpu_idle_spin, "spin" },
1401 { cpu_idle_mwait, "mwait" },
1402 return (1);
1403}
1404
1405/*
1406 * Ordered by speed/power consumption.
1407 */
1408struct {
1409 void *id_fn;
1410 char *id_name;
1411} idle_tbl[] = {
1412 { cpu_idle_spin, "spin" },
1413 { cpu_idle_mwait, "mwait" },
1402 { cpu_idle_mwait_hlt, "mwait_hlt" },
1403 { cpu_idle_amdc1e, "amdc1e" },
1404 { cpu_idle_hlt, "hlt" },
1405 { cpu_idle_acpi, "acpi" },
1406 { NULL, NULL }
1407};
1408
1409static int
1410idle_sysctl_available(SYSCTL_HANDLER_ARGS)
1411{
1412 char *avail, *p;
1413 int error;
1414 int i;
1415
1416 avail = malloc(256, M_TEMP, M_WAITOK);
1417 p = avail;
1418 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
1419 if (strstr(idle_tbl[i].id_name, "mwait") &&
1420 (cpu_feature2 & CPUID2_MON) == 0)
1421 continue;
1414 { cpu_idle_hlt, "hlt" },
1415 { cpu_idle_acpi, "acpi" },
1416 { NULL, NULL }
1417};
1418
1419static int
1420idle_sysctl_available(SYSCTL_HANDLER_ARGS)
1421{
1422 char *avail, *p;
1423 int error;
1424 int i;
1425
1426 avail = malloc(256, M_TEMP, M_WAITOK);
1427 p = avail;
1428 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
1429 if (strstr(idle_tbl[i].id_name, "mwait") &&
1430 (cpu_feature2 & CPUID2_MON) == 0)
1431 continue;
1422 if (strcmp(idle_tbl[i].id_name, "amdc1e") == 0 &&
1423 cpu_ident_amdc1e == 0)
1432 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
1433 cpu_idle_hook == NULL)
1424 continue;
1425 p += sprintf(p, "%s, ", idle_tbl[i].id_name);
1426 }
1427 error = sysctl_handle_string(oidp, avail, 0, req);
1428 free(avail, M_TEMP);
1429 return (error);
1430}
1431
1434 continue;
1435 p += sprintf(p, "%s, ", idle_tbl[i].id_name);
1436 }
1437 error = sysctl_handle_string(oidp, avail, 0, req);
1438 free(avail, M_TEMP);
1439 return (error);
1440}
1441
1442SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD,
1443 0, 0, idle_sysctl_available, "A", "list of available idle functions");
1444
1432static int
1433idle_sysctl(SYSCTL_HANDLER_ARGS)
1434{
1435 char buf[16];
1436 int error;
1437 char *p;
1438 int i;
1439

--- 7 unchanged lines hidden (view full) ---

1447 strncpy(buf, p, sizeof(buf));
1448 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
1449 if (error != 0 || req->newptr == NULL)
1450 return (error);
1451 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
1452 if (strstr(idle_tbl[i].id_name, "mwait") &&
1453 (cpu_feature2 & CPUID2_MON) == 0)
1454 continue;
1445static int
1446idle_sysctl(SYSCTL_HANDLER_ARGS)
1447{
1448 char buf[16];
1449 int error;
1450 char *p;
1451 int i;
1452

--- 7 unchanged lines hidden (view full) ---

1460 strncpy(buf, p, sizeof(buf));
1461 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
1462 if (error != 0 || req->newptr == NULL)
1463 return (error);
1464 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
1465 if (strstr(idle_tbl[i].id_name, "mwait") &&
1466 (cpu_feature2 & CPUID2_MON) == 0)
1467 continue;
1455 if (strcmp(idle_tbl[i].id_name, "amdc1e") == 0 &&
1456 cpu_ident_amdc1e == 0)
1468 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
1469 cpu_idle_hook == NULL)
1457 continue;
1458 if (strcmp(idle_tbl[i].id_name, buf))
1459 continue;
1460 cpu_idle_fn = idle_tbl[i].id_fn;
1461 return (0);
1462 }
1463 return (EINVAL);
1464}
1465
1470 continue;
1471 if (strcmp(idle_tbl[i].id_name, buf))
1472 continue;
1473 cpu_idle_fn = idle_tbl[i].id_fn;
1474 return (0);
1475 }
1476 return (EINVAL);
1477}
1478
1466SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD,
1467 0, 0, idle_sysctl_available, "A", "list of available idle functions");
1468
1469SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0,
1470 idle_sysctl, "A", "currently selected idle function");
1471
1472/*
1473 * Reset registers to default values on exec.
1474 */
1475void
1476exec_setregs(struct thread *td, struct image_params *imgp, u_long stack)

--- 1213 unchanged lines hidden (view full) ---

2690#else
2691 thread0.td_pcb->pcb_cr3 = (int)IdlePTD;
2692#endif
2693 thread0.td_pcb->pcb_ext = 0;
2694 thread0.td_frame = &proc0_tf;
2695 thread0.td_pcb->pcb_fsd = PCPU_GET(fsgs_gdt)[0];
2696 thread0.td_pcb->pcb_gsd = PCPU_GET(fsgs_gdt)[1];
2697
1479SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0,
1480 idle_sysctl, "A", "currently selected idle function");
1481
1482/*
1483 * Reset registers to default values on exec.
1484 */
1485void
1486exec_setregs(struct thread *td, struct image_params *imgp, u_long stack)

--- 1213 unchanged lines hidden (view full) ---

2700#else
2701 thread0.td_pcb->pcb_cr3 = (int)IdlePTD;
2702#endif
2703 thread0.td_pcb->pcb_ext = 0;
2704 thread0.td_frame = &proc0_tf;
2705 thread0.td_pcb->pcb_fsd = PCPU_GET(fsgs_gdt)[0];
2706 thread0.td_pcb->pcb_gsd = PCPU_GET(fsgs_gdt)[1];
2707
2698 if (cpu_probe_amdc1e())
2699 cpu_idle_fn = cpu_idle_amdc1e;
2708 cpu_probe_amdc1e();
2700}
2701
2702#else
2703void
2704init386(first)
2705 int first;
2706{
2707 struct gate_descriptor *gdp;

--- 257 unchanged lines hidden (view full) ---

2965#ifdef PAE
2966 thread0.td_pcb->pcb_cr3 = (int)IdlePDPT;
2967#else
2968 thread0.td_pcb->pcb_cr3 = (int)IdlePTD;
2969#endif
2970 thread0.td_pcb->pcb_ext = 0;
2971 thread0.td_frame = &proc0_tf;
2972
2709}
2710
2711#else
2712void
2713init386(first)
2714 int first;
2715{
2716 struct gate_descriptor *gdp;

--- 257 unchanged lines hidden (view full) ---

2974#ifdef PAE
2975 thread0.td_pcb->pcb_cr3 = (int)IdlePDPT;
2976#else
2977 thread0.td_pcb->pcb_cr3 = (int)IdlePTD;
2978#endif
2979 thread0.td_pcb->pcb_ext = 0;
2980 thread0.td_frame = &proc0_tf;
2981
2973 if (cpu_probe_amdc1e())
2974 cpu_idle_fn = cpu_idle_amdc1e;
2982 cpu_probe_amdc1e();
2975}
2976#endif
2977
2978void
2979cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size)
2980{
2981
2982 pcpu->pc_acpi_id = 0xffffffff;

--- 737 unchanged lines hidden --- 		2983}
2984#endif
2985
2986void
2987cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size)
2988{
2989
2990 pcpu->pc_acpi_id = 0xffffffff;

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