| if_xereg.h (55723) | if_xereg.h (121099) |
|---|---|
| 1/*- 2 * Copyright (c) 1998, 1999 Scott Mitchell 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 10 unchanged lines hidden (view full) --- 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $Id: if_xereg.h,v 1.5 1999/05/20 21:53:58 scott Exp $ | 1/*- 2 * Copyright (c) 1998, 1999 Scott Mitchell 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 10 unchanged lines hidden (view full) --- 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $Id: if_xereg.h,v 1.5 1999/05/20 21:53:58 scott Exp $ |
| 27 * $FreeBSD: head/sys/dev/xe/if_xereg.h 55723 2000-01-10 08:05:53Z imp $ | 27 * $FreeBSD: head/sys/dev/xe/if_xereg.h 121099 2003-10-14 22:51:35Z rsm $ |
| 28 */ 29#ifndef DEV_XE_IF_XEREG_H 30#define DEV_XE_IF_XEREG_H 31 32/* 33 * Register definitions for Xircom PCMCIA Ethernet controllers, based on 34 * Rev. B of the "Dingo" 10/100 controller used in Xircom CEM56 and RealPort 35 * Ethernet/modem cards. The Dingo can be configured to be register --- 242 unchanged lines hidden (view full) --- 278#define XE_IMR0 0x0c /* Interrupt mask register 0 */ 279#define XE_IMR1 0x0d /* Interrupt mask register 1 (CE2 only) */ 280#define XE_ECR 0x0e /* Ethernet configuration register */ 281 282/* XE_IMR0 bits */ 283#define XE_IMR0_TX_OVERFLOW 0x01 /* Masks for bits in ISR */ 284#define XE_IMR0_TX_PACKET 0x02 285#define XE_IMR0_MAC_INTR 0x04 | 28 */ 29#ifndef DEV_XE_IF_XEREG_H 30#define DEV_XE_IF_XEREG_H 31 32/* 33 * Register definitions for Xircom PCMCIA Ethernet controllers, based on 34 * Rev. B of the "Dingo" 10/100 controller used in Xircom CEM56 and RealPort 35 * Ethernet/modem cards. The Dingo can be configured to be register --- 242 unchanged lines hidden (view full) --- 278#define XE_IMR0 0x0c /* Interrupt mask register 0 */ 279#define XE_IMR1 0x0d /* Interrupt mask register 1 (CE2 only) */ 280#define XE_ECR 0x0e /* Ethernet configuration register */ 281 282/* XE_IMR0 bits */ 283#define XE_IMR0_TX_OVERFLOW 0x01 /* Masks for bits in ISR */ 284#define XE_IMR0_TX_PACKET 0x02 285#define XE_IMR0_MAC_INTR 0x04 |
| 286#define XE_IMR0_TX_RESGRANT 0x08 /* Tx reservation granted (CE2) */ |
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| 286#define XE_IMR0_RX_EARLY 0x10 287#define XE_IMR0_RX_PACKET 0x20 288#define XE_IMR0_RX_REJECT 0x40 289#define XE_IMR0_FORCE_INTR 0x80 290 | 287#define XE_IMR0_RX_EARLY 0x10 288#define XE_IMR0_RX_PACKET 0x20 289#define XE_IMR0_RX_REJECT 0x40 290#define XE_IMR0_FORCE_INTR 0x80 291 |
| 292/* XE_IMR1 bits */ 293#define XE_IMR1_TX_UNDERRUN 0x01 294 |
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| 291/* XE_ECR bits */ 292#define XE_ECR_EARLY_TX 0x01 /* Enable early transmit mode */ 293#define XE_ECR_EARLY_RX 0x02 /* Enable early receive mode */ 294#define XE_ECR_FULL_DUPLEX 0x04 /* Enable full-duplex (disable collision detection) */ 295#define XE_ECR_LONG_TPCABLE 0x08 /* CE2 only */ 296#define XE_ECR_NO_POL_COL 0x10 /* CE2 only */ 297#define XE_ECR_NO_LINK_PULSE 0x20 /* Don't check/send link pulses (not 10BT compliant) */ 298#define XE_ECR_NO_AUTO_TX 0x40 /* CE2 only */ --- 62 unchanged lines hidden (view full) --- 361#define XE_GPR1 0x09 /* General purpose register 1 */ 362#define XE_BOV 0x0a /* Bonding version register (read) */ 363#define XE_EES 0x0b /* EEPROM control register */ 364#define XE_LMA 0x0c /* Local memory address (CE2 only) */ 365#define XE_LMD 0x0e /* Local memory data (CE2 only) */ 366 367/* XE_GPR0 bits */ 368#define XE_GPR0_GP1_OUT 0x01 /* Value written to GP1 line */ | 295/* XE_ECR bits */ 296#define XE_ECR_EARLY_TX 0x01 /* Enable early transmit mode */ 297#define XE_ECR_EARLY_RX 0x02 /* Enable early receive mode */ 298#define XE_ECR_FULL_DUPLEX 0x04 /* Enable full-duplex (disable collision detection) */ 299#define XE_ECR_LONG_TPCABLE 0x08 /* CE2 only */ 300#define XE_ECR_NO_POL_COL 0x10 /* CE2 only */ 301#define XE_ECR_NO_LINK_PULSE 0x20 /* Don't check/send link pulses (not 10BT compliant) */ 302#define XE_ECR_NO_AUTO_TX 0x40 /* CE2 only */ --- 62 unchanged lines hidden (view full) --- 365#define XE_GPR1 0x09 /* General purpose register 1 */ 366#define XE_BOV 0x0a /* Bonding version register (read) */ 367#define XE_EES 0x0b /* EEPROM control register */ 368#define XE_LMA 0x0c /* Local memory address (CE2 only) */ 369#define XE_LMD 0x0e /* Local memory data (CE2 only) */ 370 371/* XE_GPR0 bits */ 372#define XE_GPR0_GP1_OUT 0x01 /* Value written to GP1 line */ |
| 369#define XE_GPR0_GP2_OUT 0x02 /* Value wirtten to GP2 line */ | 373#define XE_GPR0_GP2_OUT 0x02 /* Value written to GP2 line */ |
| 370#define XE_GPR0_GP1_SELECT 0x04 /* 1 = GP1 is output, 0 = GP1 is input */ 371#define XE_GPR0_GP2_SELECT 0x08 /* 1 = GP2 is output, 0 = GP2 is input */ 372#define XE_GPR0_GP1_IN 0x10 /* Value read from GP1 line */ 373#define XE_GPR0_GP2_IN 0x20 /* Value read from GP2 line */ 374 375/* XE_GPR1 bits */ | 374#define XE_GPR0_GP1_SELECT 0x04 /* 1 = GP1 is output, 0 = GP1 is input */ 375#define XE_GPR0_GP2_SELECT 0x08 /* 1 = GP2 is output, 0 = GP2 is input */ 376#define XE_GPR0_GP1_IN 0x10 /* Value read from GP1 line */ 377#define XE_GPR0_GP2_IN 0x20 /* Value read from GP2 line */ 378 379/* XE_GPR1 bits */ |
| 376#define XE_GPR1_POWER_DOWN 0x01 /* Power down analog section (down to 20mA load) */ | 380#define XE_GPR1_POWER_DOWN 0x01 /* 0 = Power down analog section */ 381#define XE_GPR1_AIC 0x04 /* AIC bit (CE2 only) */ |
| 377 378/* XE_BOV values */ 379#define XE_BOV_DINGO 0x55 /* Dingo in Dingo mode */ 380#define XE_BOV_MOHAWK 0x41 /* Original Mohawk */ 381#define XE_BOV_MOHAWK_REV1 0x45 /* Rev. 1 Mohawk, or Dingo in Mohawk mode */ 382#define XE_BOV_CEM28 0x11 /* CEM28 */ 383 384/* XE_EES bits */ --- 81 unchanged lines hidden (view full) --- 466#define XE_TXST0_TX_ABORT 0x40 /* Transmit aborted: collisions, underrun or overrun */ 467#define XE_TXST0_TX_OK 0x80 /* Complete packet sent OK */ 468 469/* TXST1 bits */ 470#define XE_TXST1_RETRY_COUNT 0x0f /* Collision counter for current packet */ 471#define XE_TXST1_LINK_STATUS 0x10 /* Valid link status */ 472 473/* RX0Msk bits */ | 382 383/* XE_BOV values */ 384#define XE_BOV_DINGO 0x55 /* Dingo in Dingo mode */ 385#define XE_BOV_MOHAWK 0x41 /* Original Mohawk */ 386#define XE_BOV_MOHAWK_REV1 0x45 /* Rev. 1 Mohawk, or Dingo in Mohawk mode */ 387#define XE_BOV_CEM28 0x11 /* CEM28 */ 388 389/* XE_EES bits */ --- 81 unchanged lines hidden (view full) --- 471#define XE_TXST0_TX_ABORT 0x40 /* Transmit aborted: collisions, underrun or overrun */ 472#define XE_TXST0_TX_OK 0x80 /* Complete packet sent OK */ 473 474/* TXST1 bits */ 475#define XE_TXST1_RETRY_COUNT 0x0f /* Collision counter for current packet */ 476#define XE_TXST1_LINK_STATUS 0x10 /* Valid link status */ 477 478/* RX0Msk bits */ |
| 479#define XE_RX0M_MP 0x01 /* Multicast packet? (CE2 only) */ |
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| 474#define XE_RX0M_LONG_PACKET 0x02 /* Masks for bits in RXST0 */ 475#define XE_RX0M_ALIGN_ERROR 0x04 /* Alignment error (CE2 only) */ 476#define XE_RX0M_CRC_ERROR 0x08 477#define XE_RX0M_RX_OVERRUN 0x10 478#define XE_RX0M_RX_ABORT 0x40 479#define XE_RX0M_RX_OK 0x80 480 481/* TX0Msk bits */ --- 17 unchanged lines hidden (view full) --- 499#define XE_BOC 0x0a /* Back-off configuration */ 500#define XE_TCD 0x0b /* Transmit collision deferral */ 501 502/* SWC0 bits */ 503#define XE_SWC0_LOOPBACK_ENABLE 0x01 /* Enable loopback operation */ 504#define XE_SWC0_LOOPBACK_SOURCE 0x02 /* 1 = Transceiver, 0 = MAC */ 505#define XE_SWC0_ACCEPT_ERROR 0x04 /* Accept otherwise OK packets with CRC errors */ 506#define XE_SWC0_ACCEPT_SHORT 0x08 /* Accept otherwise OK packets that are too short */ | 480#define XE_RX0M_LONG_PACKET 0x02 /* Masks for bits in RXST0 */ 481#define XE_RX0M_ALIGN_ERROR 0x04 /* Alignment error (CE2 only) */ 482#define XE_RX0M_CRC_ERROR 0x08 483#define XE_RX0M_RX_OVERRUN 0x10 484#define XE_RX0M_RX_ABORT 0x40 485#define XE_RX0M_RX_OK 0x80 486 487/* TX0Msk bits */ --- 17 unchanged lines hidden (view full) --- 505#define XE_BOC 0x0a /* Back-off configuration */ 506#define XE_TCD 0x0b /* Transmit collision deferral */ 507 508/* SWC0 bits */ 509#define XE_SWC0_LOOPBACK_ENABLE 0x01 /* Enable loopback operation */ 510#define XE_SWC0_LOOPBACK_SOURCE 0x02 /* 1 = Transceiver, 0 = MAC */ 511#define XE_SWC0_ACCEPT_ERROR 0x04 /* Accept otherwise OK packets with CRC errors */ 512#define XE_SWC0_ACCEPT_SHORT 0x08 /* Accept otherwise OK packets that are too short */ |
| 513#define XE_SWC0_NO_SRC_INSERT 0x20 /* Disable source insertion (CE2) */ |
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| 507#define XE_SWC0_NO_CRC_INSERT 0x40 /* Don't add CRC to outgoing packets */ 508 509/* SWC1 bits */ 510#define XE_SWC1_IA_ENABLE 0x01 /* Enable individual address filters */ 511#define XE_SWC1_ALLMULTI 0x02 /* Accept all multicast packets */ 512#define XE_SWC1_PROMISCUOUS 0x04 /* Accept all non-multicast packets */ 513#define XE_SWC1_BCAST_DISABLE 0x08 /* Reject broadcast packets */ 514#define XE_SWC1_MEDIA_SELECT 0x40 /* AUI media select (Mohawk only) */ --- 179 unchanged lines hidden --- | 514#define XE_SWC0_NO_CRC_INSERT 0x40 /* Don't add CRC to outgoing packets */ 515 516/* SWC1 bits */ 517#define XE_SWC1_IA_ENABLE 0x01 /* Enable individual address filters */ 518#define XE_SWC1_ALLMULTI 0x02 /* Accept all multicast packets */ 519#define XE_SWC1_PROMISCUOUS 0x04 /* Accept all non-multicast packets */ 520#define XE_SWC1_BCAST_DISABLE 0x08 /* Reject broadcast packets */ 521#define XE_SWC1_MEDIA_SELECT 0x40 /* AUI media select (Mohawk only) */ --- 179 unchanged lines hidden --- |